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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/
Darmv8-2-fp16-simd.d114 198: f3b7608c vcvta.u16.f16 d6, d12
115 19c: f3b7c0e8 vcvta.u16.f16 q6, q12
116 1a0: f3b7638c vcvtm.u16.f16 d6, d12
117 1a4: f3b7c3e8 vcvtm.u16.f16 q6, q12
118 1a8: f3b7618c vcvtn.u16.f16 d6, d12
119 1ac: f3b7c1e8 vcvtn.u16.f16 q6, q12
120 1b0: f3b7628c vcvtp.u16.f16 d6, d12
121 1b4: f3b7c2e8 vcvtp.u16.f16 q6, q12
124 1c0: f3b7e780 vcvt.u16.f16 d14, d0
125 1c4: f3f7c7c0 vcvt.u16.f16 q14, q0
[all …]
Dvcvt-bad.l2 [^:]*:3: Error: immediate value out of range -- `vcvt.f64.u16 d1,d1,#-1'
4 [^:]*:5: Error: immediate value out of range, expected range \[0, 16\] -- `vcvt.f64.u16 d1,d1,#17'
8 [^:]*:10: Error: immediate value out of range -- `vcvt.f32.u16 s1,s1,#65535'
12 [^:]*:15: Error: immediate value out of range -- `vcvt.u16.f64 d1,d1,#-1'
14 [^:]*:17: Error: immediate value out of range, expected range \[0, 16\] -- `vcvt.u16.f64 d1,d1,#17'
18 [^:]*:22: Error: immediate value out of range -- `vcvt.u16.f32 s1,s1,#65535'
Darmv8-2-fp16-simd-thumb.d114 198: ffb7 608c vcvta.u16.f16 d6, d12
115 19c: ffb7 c0e8 vcvta.u16.f16 q6, q12
116 1a0: ffb7 638c vcvtm.u16.f16 d6, d12
117 1a4: ffb7 c3e8 vcvtm.u16.f16 q6, q12
118 1a8: ffb7 618c vcvtn.u16.f16 d6, d12
119 1ac: ffb7 c1e8 vcvtn.u16.f16 q6, q12
120 1b0: ffb7 628c vcvtp.u16.f16 d6, d12
121 1b4: ffb7 c2e8 vcvtp.u16.f16 q6, q12
124 1c0: ffb7 e780 vcvt.u16.f16 d14, d0
125 1c4: fff7 c7c0 vcvt.u16.f16 q14, q0
[all …]
Dneon-omit.s11 vshl.u16 q3,q4
48 vsra.u16 q3,#6
49 vrsra.u16 q4,#6
60 vshl.u16 q3,q4,q5
93 vsra.u16 q3,q1,#6
94 vrsra.u16 q15,q4,#6
Dneon-psyn.s14 vmull fish.u32, chips.u16, chips.u16[1]
41 vabal baa, moo.u16, sheep.u16
Dneon-cov.d20 0[0-9a-f]+ <[^>]+> f3100750 vaba\.u16 q0, q0, q0
21 0[0-9a-f]+ <[^>]+> f3100750 vaba\.u16 q0, q0, q0
22 0[0-9a-f]+ <[^>]+> f3100710 vaba\.u16 d0, d0, d0
38 0[0-9a-f]+ <[^>]+> f3100040 vhadd\.u16 q0, q0, q0
39 0[0-9a-f]+ <[^>]+> f3100040 vhadd\.u16 q0, q0, q0
40 0[0-9a-f]+ <[^>]+> f3100000 vhadd\.u16 d0, d0, d0
56 0[0-9a-f]+ <[^>]+> f3100140 vrhadd\.u16 q0, q0, q0
57 0[0-9a-f]+ <[^>]+> f3100140 vrhadd\.u16 q0, q0, q0
58 0[0-9a-f]+ <[^>]+> f3100100 vrhadd\.u16 d0, d0, d0
74 0[0-9a-f]+ <[^>]+> f3100240 vhsub\.u16 q0, q0, q0
[all …]
Dvfpv3-const-conv.d18 0[0-9a-f]+ <[^>]+> eefb8a63 (vcvt\.f32\.u16 s17, s17, #9|fuhtos s17, #9)
19 0[0-9a-f]+ <[^>]+> eefb1b63 (vcvt\.f64\.u16 d17, d17, #9|fuhtod d17, #9)
26 0[0-9a-f]+ <[^>]+> eeff9a64 (vcvt\.u16\.f32 s19, s19, #7|ftouhs s19, #7)
27 0[0-9a-f]+ <[^>]+> eeff3b64 (vcvt\.u16\.f64 d19, d19, #7|ftouhd d19, #7)
Dneon-cov.s41 regs3_1 \op \opq .u16
56 regs3_1 \op \opq .u16
81 regs2i_1 \op \opq \imm .u16
169 regs3_1 \op \opq .u16
222 dregs3_1 \op .u16
336 regs2i_1 \op \opq 15 .u16
365 regn3_1 \op 7 .u16
396 regl3_1 vshll 1 .u16
428 vmov.u16 r0,d0[0]
488 regl3_1 \op d0 .u16
[all …]
Darmv8-2-fp16-simd.s115 … vcvtm.s16.f16, vcvtn.s16.f16, vcvtp.s16.f16, vcvta.u16.f16, vcvtm.u16.f16, vcvtn.u16.f16, vcvtp.u…
122 .irp op, vcvt.s16.f16, vcvt.u16.f16, vcvt.f16.s16, vcvt.f16.u16,
129 .irp op, vcvt.s16.f16, vcvt.u16.f16, vcvt.f16.s16, vcvt.f16.u16,
Darmv8-2-fp16-simd-warning.l104 [^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvta.u16.f16 d6,d12'
106 [^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvtm.u16.f16 d6,d12'
108 [^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvtn.u16.f16 d6,d12'
110 [^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvtp.u16.f16 d6,d12'
114 [^:]*:218: Error: selected processor does not support fp16 instruction -- `vcvt.u16.f16 d14,d0'
118 [^:]*:218: Error: selected processor does not support fp16 instruction -- `vcvt.f16.u16 d14,d0'
122 [^:]*:221: Error: selected processor does not support fp16 instruction -- `vcvt.u16.f16 d14,d0,#3'
126 [^:]*:221: Error: selected processor does not support fp16 instruction -- `vcvt.f16.u16 d14,d0,#3'
Dvfp-neon-syntax-inc.s110 .macro cvti cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" s16=".s16" u16=".u16"
123 vcvt\cond\f32\u16 s0,s0,#1
125 vcvt\cond\f64\u16 d0,d0,#1
128 vcvt\cond\u16\f32 s0,s0,#1
130 vcvt\cond\u16\f64 d0,d0,#1
Dneon-omit.d12 0[0-9a-f]+ <[^>]+> f3186446 vshl\.u16 q3, q3, q4
49 0[0-9a-f]+ <[^>]+> f39a6156 vsra\.u16 q3, q3, #6
50 0[0-9a-f]+ <[^>]+> f39a8358 vrsra\.u16 q4, q4, #6
58 0[0-9a-f]+ <[^>]+> f31a6448 vshl\.u16 q3, q4, q5
91 0[0-9a-f]+ <[^>]+> f39a6152 vsra\.u16 q3, q1, #6
92 0[0-9a-f]+ <[^>]+> f3dae358 vrsra\.u16 q15, q4, #6
Dvfp-neon-syntax.d125 0[0-9a-f]+ <[^>]+> eebb0a67 (vcvt\.f32\.u16 s0, s0, #1|fuhtos s0, #1)
127 0[0-9a-f]+ <[^>]+> eebb0b67 (vcvt\.f64\.u16 d0, d0, #1|fuhtod d0, #1)
129 0[0-9a-f]+ <[^>]+> eebf0a67 (vcvt\.u16\.f32 s0, s0, #1|ftouhs s0, #1)
131 0[0-9a-f]+ <[^>]+> eebf0b67 (vcvt\.u16\.f64 d0, d0, #1|ftouhd d0, #1)
141 0[0-9a-f]+ <[^>]+> 0ebb0a67 (vcvteq\.f32\.u16 s0, s0, #1|fuhtoseq s0, #1)
143 0[0-9a-f]+ <[^>]+> 0ebb0b67 (vcvteq\.f64\.u16 d0, d0, #1|fuhtodeq d0, #1)
145 0[0-9a-f]+ <[^>]+> 0ebf0a67 (vcvteq\.u16\.f32 s0, s0, #1|ftouhseq s0, #1)
147 0[0-9a-f]+ <[^>]+> 0ebf0b67 (vcvteq\.u16\.f64 d0, d0, #1|ftouhdeq d0, #1)
Dneon-psyn.d12 0[0-9a-f]+ <[^>]+> f3924a4a vmull\.u16 q2, d2, d2\[1\]
22 0[0-9a-f]+ <[^>]+> f396a507 vabal\.u16 q5, d6, d7
Dvfp-neon-syntax_t2.d147 0[0-9a-f]+ <[^>]+> eebb 0a67 (vcvt\.f32\.u16 s0, s0, #1|fuhtos s0, #1)
149 0[0-9a-f]+ <[^>]+> eebb 0b67 (vcvt\.f64\.u16 d0, d0, #1|fuhtod d0, #1)
151 0[0-9a-f]+ <[^>]+> eebf 0a67 (vcvt\.u16\.f32 s0, s0, #1|ftouhs s0, #1)
153 0[0-9a-f]+ <[^>]+> eebf 0b67 (vcvt\.u16\.f64 d0, d0, #1|ftouhd d0, #1)
166 0[0-9a-f]+ <[^>]+> eebb 0a67 (vcvteq\.f32\.u16 s0, s0, #1|fuhtoseq s0, #1)
168 0[0-9a-f]+ <[^>]+> eebb 0b67 (vcvteq\.f64\.u16 d0, d0, #1|fuhtodeq d0, #1)
171 0[0-9a-f]+ <[^>]+> eebf 0a67 (vcvteq\.u16\.f32 s0, s0, #1|ftouhseq s0, #1)
173 0[0-9a-f]+ <[^>]+> eebf 0b67 (vcvteq\.u16\.f64 d0, d0, #1|ftouhdeq d0, #1)
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/
Dillegal-2.s15 add wsp, w0, u16, LSL #12
16 add wsp, w0, u16, LSL #0
22 .set u16, 0xfff0 define
Dreloc-insn.s149 svc u16
207 .set u16, 65535 define
/toolchain/binutils/binutils-2.27/cpu/
Dmep-ivc2.cpu136 (dnf f-ivc2-5u16 "sub opcode field" (all-mep-isas) 16 5)
141 (dnf f-ivc2-4u16 "sub opcode field" (all-mep-isas) 16 4)
334 (f-ivc2-4u16 #xF) (f-ivc2-4u20 0) (f-ivc2-4u24 0) (f-29 0) (f-30 0) (f-31 0))
345 (f-ivc2-4u16 #xF) (f-ivc2-4u20 0) (f-ivc2-4u24 0) (f-29 0) (f-30 0) (f-31 1))
356 (f-ivc2-4u16 #xF) (f-ivc2-4u20 0) (f-ivc2-4u24 0) (f-30 1) (f-31 0))
367 (f-ivc2-4u16 #xF) (f-ivc2-4u20 0) (f-ivc2-4u24 0) (f-30 1) (f-31 1))
378 (f-ivc2-4u16 #xF) (f-ivc2-4u20 1) (f-ivc2-4u24 0) (f-29 0) (f-30 0) (f-31 0))
389 (f-ivc2-4u16 #xF) (f-ivc2-4u20 1) (f-ivc2-4u24 0) (f-29 0) (f-30 0) (f-31 1))
460 (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) )
472 (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) )
[all …]
Dm32c.cpu437 (df f-dsp-8-u16 "16 bit unsigned" (all-isas) 8 16 UINT
457 (df f-dsp-16-u16 "16 bit unsigned" (all-isas) 16 16 UINT
477 (dnmf f-dsp-24-u16 "16 bit unsigned" (all-isas) UINT
480 (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u16) #xff))
481 (set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-24-u16) 8) #xff))
484 (set (ifield f-dsp-24-u16) (or (sll (ifield f-dsp-32-u8) 8)
505 (df f-dsp-32-u16 "16 bit unsigned" (all-isas) 32 16 UINT
525 (df f-dsp-40-u16 "16 bit unsigned" (all-isas) 40 16 UINT
545 (df f-dsp-48-u16 "16 bit unsigned" (all-isas) 48 16 UINT
565 (df f-dsp-64-u16 "16 bit unsigned" (all-isas) 64 16 UINT
[all …]
Dmep-c5.cpu234 (df f-c5-16u16 "general 16-bit u-val" (all-mep-isas) 16 16 UINT #f #f)
237 (f-c5-rm f-c5-16u16)
240 (set (ifield f-c5-16u16) (and (ifield f-c5-rmuimm20) #xffff))
243 (set (ifield f-c5-rmuimm20) (or (ifield f-c5-16u16)
250 (f-c5-rnm f-c5-16u16)
253 (set (ifield f-c5-16u16) (and (ifield f-c5-rnmuimm24) #xffff))
256 (set (ifield f-c5-rnmuimm24) (or (ifield f-c5-16u16)
Dmep-core.cpu464 (df f-24u5a2n-hi "24u5a2n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
504 (df f-16u16 "general 16-bit u-val" (all-mep-core-isas) 16 16 UINT #f #f)
505 (df f-12u16 "cmov fixed 1" (all-mep-core-isas) 16 12 UINT #f #f)
537 (df f-24u8a4n-hi "24u8a4n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
553 (df f-24u8n-hi "24u8n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
570 (df f-24u4n-lo "24u4n lo 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
747 (dpop uimm16 "unsigned imm (16 bits)" (all-mep-core-isas) h-uint f-16u16 "unsigned16")
748 (dnop code16 "uci/dsp code (16 bits)" (all-mep-core-isas) h-uint f-16u16)
2190 (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3004))
2204 (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3005))
[all …]
Dfrv.cpu1971 (df f-u16 "16 bit unsigned" () 15 16 UINT #f #f)
3167 (dnop u16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-u16)
3284 (index f-u16)
3302 (index f-u16)
4305 (+ pack GRk OP_3D (misc-null-4) u16)
4306 (set GRklo u16)
4316 (+ pack GRkhi OP_3E (misc-null-4) u16)
4317 (set GRkhi u16)
/toolchain/binutils/binutils-2.27/ld/testsuite/ld-nios2/
Du16.d2 #source: u16.s
/toolchain/binutils/binutils-2.27/ld/testsuite/
DChangeLog-20131427 * ld-nios2/u16.d: New.
1428 * ld-nios2/u16.s: New.