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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/
Dcrc32-bad.l2 [^:]*:4: Warning: using r15 results in unpredictable behaviour
3 [^:]*.s:5: Warning: using r15 results in unpredictable behaviour
4 [^:]*.s:6: Warning: using r15 results in unpredictable behaviour
5 [^:]*.s:7: Warning: using r15 results in unpredictable behaviour
6 [^:]*.s:8: Warning: using r15 results in unpredictable behaviour
7 [^:]*.s:9: Warning: using r15 results in unpredictable behaviour
8 [^:]*.s:12: Warning: using r13 results in unpredictable behaviour
9 [^:]*.s:13: Warning: using r15 results in unpredictable behaviour
10 [^:]*.s:14: Warning: using r13 results in unpredictable behaviour
11 [^:]*.s:15: Warning: using r15 results in unpredictable behaviour
[all …]
Dld-sp-warn-cortex-m4.l2 [^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interru…
3 [^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interru…
Dld-sp-warn-v7e-m.l2 [^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interru…
3 [^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interru…
Dld-sp-warn-cortex-m3.l2 [^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interru…
3 [^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interru…
Dld-sp-warn-v7.l2 [^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interru…
3 [^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interru…
Dld-sp-warn-v7m.l2 [^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interru…
3 [^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interru…
Dld-sp-warn.l2 [^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interru…
3 [^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interru…
Dldrd-unpredictable.d2 # error-output: ldrd-unpredictable.l
Dldrd-unpredictable.s6 ldrd r0,r1,[r0,r1] @ unpredictable
Dunpredictable.s3 unpredictable: label
84 nop @ Marker to indicated end of unpredictable insns.
Dthumb2_ldr_immediate_highregs_armv6t2.s27 # These should be encoded as ldr since mov immediate is unpredictable
Dsp-pc-validations-bad.s8 @No unpredictable or undefined combinations.
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/
Ddiagnostic.l109 [^:]*:116: Warning: unpredictable load of register pair -- `ldp d0,d0,\[sp\]'
111 [^:]*:118: Warning: unpredictable load of register pair -- `ldnp x0,x0,\[sp\]'
113 [^:]*:122: Warning: unpredictable transfer with writeback -- `str x0,\[x0,#8\]!'
115 [^:]*:124: Warning: unpredictable transfer with writeback -- `stp x0,x1,\[x0,#16\]!'
Ddiagnostic.s114 # test warning of unpredictable load pairs
120 # test warning of unpredictable writeback
/toolchain/binutils/binutils-2.27/ld/testsuite/ld-arm/
Dstm32l4xx-fix-ldm.s61 @ Write-back variant are unpredictable when rx appears also in
/toolchain/binutils/binutils-2.27/gas/testsuite/
DChangeLog-200920 * gas/arm/unpredictable.s: Add more unpredictable instructions.
21 * gas/arm/unpredictable.d: Add expected disassemblies.
26 * gas/arm/unpredictable.s: New test case - checks the disassembly
27 of instructions with unpredictable behaviour.
28 * gas/arm/unpredictable.d: New file - expected disassembly.
DChangeLog-20101757 * gas/arm/unpredictable.d: Likewise.
1758 * gas/arm/unpredictable.s: Likewise.
/toolchain/binutils/binutils-2.27/libiberty/
Dlibiberty.texi138 unpredictable on some operating systems.
/toolchain/binutils/binutils-2.27/opcodes/
DChangeLog-2009158 results in unpredictable behaviour.
212 post-indexed addressing as unpredictable.
316 unpredictable.
422 unpredictable addressing modes. Add support for %S format control
DChangeLog-2015625 (arm_opcodes): Fix for unpredictable nop being recognized as a
/toolchain/binutils/binutils-2.27/gas/
DChangeLog-2011124 * config/tc-arm.c (do_t_ldstd): Warn for unpredictable cases.
1168 * config/tc-arm.c (do_ldrd): Warn in unpredictable cases.
/toolchain/binutils/binutils-2.27/gas/po/
Dgas.pot1811 msgid "unpredictable transfer with writeback -- `%s'"
1816 msgid "unpredictable load of register pair -- `%s'"
3905 "This instruction may be unpredictable if executed on M-profile cores with "
17756 msgid "-(PC) unpredictable"
17760 msgid "[]index same as -()register: unpredictable"
17768 msgid "(PC)+ unpredictable"
17772 msgid "[]index same as ()+register: unpredictable"
17784 msgid "writing or modifying # is unpredictable"
17800 msgid "PC part of operand unpredictable"
Dja.po2668 msgid "This instruction may be unpredictable if executed on M-profile cores with interrupts enabled…
14522 msgid "-(PC) unpredictable"
14526 msgid "[]index same as -()register: unpredictable"
14534 msgid "(PC)+ unpredictable"
14538 msgid "[]index same as ()+register: unpredictable"
14550 msgid "writing or modifying # is unpredictable"
14566 msgid "PC part of operand unpredictable"
Dru.po13697 msgid "-(PC) unpredictable"
13701 msgid "[]index same as -()register: unpredictable"
13709 msgid "(PC)+ unpredictable"
13713 msgid "[]index same as ()+register: unpredictable"
13725 msgid "writing or modifying # is unpredictable"
13741 msgid "PC part of operand unpredictable"
Drw.po11747 msgid "-(PC) unpredictable"
11751 msgid "[]index same as -()register: unpredictable"
11759 msgid "(PC)+ unpredictable"
11763 msgid "[]index same as ()+register: unpredictable"
11775 msgid "writing or modifying # is unpredictable"
11791 msgid "PC part of operand unpredictable"

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