12015-12-31 Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> 2 Andrew Burgess <andrew.burgess@embecosm.com> 3 4 * arc-tbl.h (dmb): Add a no operand version of dmb. 5 62015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> 7 8 * arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex, 9 ldrexb, ldrexh, strex, strexb, strexh shared by ARMv6T2 and ARMv8-M by 10 ARM_EXT2_V6T2_V8M instead of ARM_EXT_V6T2. 11 122015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> 13 14 * arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl, 15 stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of 16 ARM_EXT_V8. 17 (thumb32_opcodes): Add entries for wide ARMv8-M instructions. 18 192015-12-22 Yoshinori Sato <ysato@users.sourceforge.jp> 20 21 * rx-decode.opc (movco): Use uniqe id. 22 (movli): Likewise. 23 (stnz): Condition fix. 24 (mvtacgu): Destination fix. 25 * rx-decode.c: Regenerate. 26 272015-12-14 Yoshinori Sato <ysato@users.sourceforge.jp> 28 29 * rx-deocde.opc: Add new instructions pattern. 30 * rx-deocde.c: Regenerate. 31 * rx-dis.c (register_name): Add new register. 32 332015-12-14 Matthew Wahab <matthew.wahab@arm.com> 34 35 * aarch64-asm-2.c: Regenerate. 36 * aarch64-dis-2.c: Regenerate. 37 * aarch64-opc-2.c: Regenerate. 38 * aarch64-tbl.h (QL_SSHIFT_H): New. 39 (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf 40 and fcvtzu to the Adv.SIMD scalar shift by immediate group. 41 422015-12-14 Matthew Wahab <matthew.wahab@arm.com> 43 44 * aarch64-asm-2.c: Regenerate. 45 * aarch64-dis-2.c: Regenerate. 46 * aarch64-opc-2.c: Regenerate. 47 * aarch64-tbl.h (QL_VSHIFT_H): New. 48 (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf 49 and fcvtzu to the Adv.SIMD shift by immediate group. 50 512015-12-14 Matthew Wahab <matthew.wahab@arm.com> 52 53 * aarch64-asm-2.c: Regenerate. 54 * aarch64-dis-2.c: Regenerate. 55 * aarch64-opc-2.c: Regenerate. 56 * aarch64-tbl.h (QL_SISD_PAIR_H): New. 57 (aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp, 58 fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group. 59 602015-12-14 Matthew Wahab <matthew.wahab@arm.coM> 61 62 * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment 63 and adjust calculation to ignore qualifier for type 2H. 64 * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H". 65 662015-12-14 Matthew Wahab <matthew.wahab@arm.com> 67 68 * aarch64-asm-2.c: Regenerate. 69 * aarch64-dis-2.c: Regenerate. 70 * aarch64-opc-2.c: Regenerate. 71 * aarch64-tbl.h (QL_SIMD_IMM_H): New. 72 (aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD 73 modified immediate group. 74 752015-12-14 Matthew Wahab <matthew.wahab@arm.com> 76 77 * aarch64-asm-2.c: Regenerate. 78 * aarch64-dis-2.c: Regenerate. 79 * aarch64-opc-2.c: Regenerate. 80 * aarch64-tbl.h (QL_XLANES_FP_H): New. 81 (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv, 82 fminnmv, fminv to the Adv.SIMD across lanes group. 83 842015-12-14 Matthew Wahab <matthew.wahab@arm.com> 85 86 * aarch64-asm-2.c: Regenerate. 87 * aarch64-dis-2.c: Regenerate. 88 * aarch64-opc-2.c: Regenerate. 89 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla, 90 fmls, fmul and fmulx to the scalar indexed element group. 91 922015-12-14 Matthew Wahab <matthew.wahab@arm.com> 93 94 * aarch64-asm-2.c: Regenerate. 95 * aarch64-dis-2.c: Regenerate. 96 * aarch64-opc-2.c: Regenerate. 97 * aarch64-tbl.h (QL_ELEMENT_FP_H): New. 98 (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and 99 fmulx to the vector indexed element group. 100 1012015-12-14 Matthew Wahab <matthew.wahab@arm.com> 102 103 * aarch64-asm-2.c: Regenerate. 104 * aarch64-dis-2.c: Regenerate. 105 * aarch64-opc-2.c: Regenerate. 106 * aarch64-tbl.h (QL_SISD_FCMP_H_0): new. 107 (QL_S_2SAMEH): New. 108 (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms, 109 fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe, 110 frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu, 111 fcvtzu and frsqrte to the scalar two register misc. group. 112 1132015-12-14 Matthew Wahab <matthew.wahab@arm.com> 114 115 * aarch64-asm-2.c: Regenerate. 116 * aarch64-dis-2.c: Regenerate. 117 * aarch64-opc-2.c: Regenerate. 118 * aarch64-tbl.h (QL_V2SAMEH): New. 119 (aarch64_opcode_table): Add fp16 versions of frintn, frintm, 120 fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp, 121 frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu, 122 fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte 123 and fsqrt to the vector register misc. group. 124 1252015-12-14 Matthew Wahab <matthew.wahab@arm.com> 126 127 * aarch64-asm-2.c: Regenerate. 128 * aarch64-dis-2.c: Regenerate. 129 * aarch64-opc-2.c: Regenerate. 130 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of 131 fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt 132 to the scalar three same group. 133 1342015-12-14 Matthew Wahab <matthew.wahab@arm.com> 135 136 * aarch64-asm-2.c: Regenerate. 137 * aarch64-dis-2.c: Regenerate. 138 * aarch64-opc-2.c: Regenerate. 139 * aarch64-tbl.h (QL_V3SAMEH): New. 140 (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd, 141 fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts, 142 fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd, 143 fcmgt, facgt and fminp to the vector three same group. 144 1452015-12-14 Matthew Wahab <matthew.wahab@arm.com> 146 147 * aarch64-tbl.h (aarch64_feature_simd_f16): New. 148 (SIMD_F16): New. 149 1502015-12-14 Matthew Wahab <matthew.wahab@arm.com> 151 152 * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly 153 removed statement. 154 (aarch64_pstatefield_supported_p): Move feature checks for AT 155 registers .. 156 (aarch64_sys_ins_reg_supported_p): .. to here. 157 1582015-12-12 Alan Modra <amodra@gmail.com> 159 160 PR 19359 161 * ppc-opc.c (insert_fxm): Remove "ignored" from error message. 162 (powerpc_opcodes): Remove single-operand mfcr. 163 1642015-12-11 Matthew Wahab <matthew.wahab@arm.com> 165 166 * aarch64-asm.c (aarch64_ins_hint): New. 167 * aarch64-asm.h (aarch64_ins_hint): Declare. 168 * aarch64-dis.c (aarch64_ext_hint): New. 169 * aarch64-dis.h (aarch64_ext_hint): Declare. 170 * aarch64-opc-2.c: Regenerate. 171 * aarch64-opc.c (aarch64_hint_options): New. 172 * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos. 173 1742015-12-11 Matthew Wahab <matthew.wahab@arm.com> 175 176 * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16. 177 1782015-12-11 Matthew Wahab <matthew.wahab@arm.com> 179 180 * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1, 181 pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1, 182 pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and 183 pmscr_el2. 184 (aarch64_sys_reg_supported_p): Add architecture feature tests for 185 the new registers. 186 1872015-12-10 Matthew Wahab <matthew.wahab@arm.com> 188 189 * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp". 190 (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register 191 feature test for "s1e1rp" and "s1e1wp". 192 1932015-12-10 Matthew Wahab <matthew.wahab@arm.com> 194 195 * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap". 196 (aarch64_sys_ins_reg_supported_p): New. 197 1982015-12-10 Matthew Wahab <matthew.wahab@arm.com> 199 200 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt 201 with aarch64_sys_ins_reg_has_xt. 202 (aarch64_ext_sysins_op): Likewise. 203 * aarch64-opc.c (operand_general_constraint_met_p): Likewise. 204 (F_HASXT): New. 205 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg. 206 (aarch64_sys_regs_dc): Likewise. 207 (aarch64_sys_regs_at): Likewise. 208 (aarch64_sys_regs_tlbi): Likewise. 209 (aarch64_sys_ins_reg_has_xt): New. 210 2112015-12-10 Matthew Wahab <matthew.wahab@arm.com> 212 213 * aarch64-opc.c (aarch64_sys_regs): Add "uao". 214 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao". 215 (aarch64_pstatefields): Add "uao". 216 (aarch64_pstatefield_supported_p): Add checks for "uao". 217 2182015-12-10 Matthew Wahab <matthew.wahab@arm.com> 219 220 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1", 221 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1", 222 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2". 223 (aarch64_sys_reg_supported_p): Add architecture feature tests for 224 new registers. 225 2262015-12-10 Matthew Wahab <matthew.wahab@arm.com> 227 228 * aarch64-asm-2.c: Regenerate. 229 * aarch64-dis-2.c: Regenerate. 230 * aarch64-tbl.h (aarch64_feature_ras): New. 231 (RAS): New. 232 (aarch64_opcode_table): Add "esb". 233 2342015-12-09 H.J. Lu <hongjiu.lu@intel.com> 235 236 * i386-dis.c (MOD_0F01_REG_5): New. 237 (RM_0F01_REG_5): Likewise. 238 (reg_table): Use MOD_0F01_REG_5. 239 (mod_table): Add MOD_0F01_REG_5. 240 (rm_table): Add RM_0F01_REG_5. 241 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS. 242 (cpu_flags): Add CpuOSPKE. 243 * i386-opc.h (CpuOSPKE): New. 244 (i386_cpu_flags): Add cpuospke. 245 * i386-opc.tbl: Add rdpkru and wrpkru instructions. 246 * i386-init.h: Regenerated. 247 * i386-tbl.h: Likewise. 248 2492015-12-07 DJ Delorie <dj@redhat.com> 250 251 * rl78-decode.opc: Enable MULU for all ISAs. 252 * rl78-decode.c: Regenerate. 253 2542015-12-07 Alan Modra <amodra@gmail.com> 255 256 * ppc-opc.c (powerpc_opcodes): Sort power9 insns by 257 major opcode/xop. 258 2592015-12-04 Claudiu Zissulescu <claziss@synopsys.com> 260 261 * arc-dis.c (special_flag_p): Match full mnemonic. 262 * arc-opc.c (print_insn_arc): Check section size to read 263 appropriate number of bytes. Fix printing. 264 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without 265 arguments. 266 2672015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> 268 269 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo... 270 <ldah>: ... to this. 271 2722015-11-27 Matthew Wahab <matthew.wahab@arm.com> 273 274 * aarch64-asm-2.c: Regenerate. 275 * aarch64-dis-2.c: Regenerate. 276 * aarch64-opc-2.c: Regenerate. 277 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New. 278 (QL_INT2FP_H, QL_FP2INT_H): New. 279 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New 280 (QL_DST_H): New. 281 (QL_FCCMP_H): New. 282 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf, 283 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau, 284 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp, 285 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm, 286 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax, 287 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and 288 fcsel. 289 2902015-11-27 Matthew Wahab <matthew.wahab@arm.com> 291 292 * aarch64-opc.c (half_conv_t): New. 293 (expand_fp_imm): Replace is_dp flag with the parameter size to 294 specify the number of bytes for the required expansion. Treat 295 a 16-bit expansion like a 32-bit expansion. Add check for an 296 unsupported size request. Update comment. 297 (aarch64_print_operand): Update to support 16-bit floating point 298 values. Update for changes to expand_fp_imm. 299 3002015-11-27 Matthew Wahab <matthew.wahab@arm.com> 301 302 * aarch64-tbl.h (aarch64_feature_fp_f16): New. 303 (FP_F16): New. 304 3052015-11-27 Matthew Wahab <matthew.wahab@arm.com> 306 307 * aarch64-asm-2.c: Regenerate. 308 * aarch64-dis-2.c: Regenerate. 309 * aarch64-opc-2.c: Regenerate. 310 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add 311 "rev64". 312 3132015-11-27 Matthew Wahab <matthew.wahab@arm.com> 314 315 * aarch64-asm-2.c: Regenerate. 316 * aarch64-asm.c (convert_bfc_to_bfm): New. 317 (convert_to_real): Add case for OP_BFC. 318 * aarch64-dis-2.c: Regenerate. 319 * aarch64-dis.c: (convert_bfm_to_bfc): New. 320 (convert_to_alias): Add case for OP_BFC. 321 * aarch64-opc-2.c: Regenerate. 322 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert 323 to allow width operand in three-operand instructions. 324 * aarch64-tbl.h (QL_BF1): New. 325 (aarch64_feature_v8_2): New. 326 (ARMV8_2): New. 327 (aarch64_opcode_table): Add "bfc". 328 3292015-11-27 Matthew Wahab <matthew.wahab@arm.com> 330 331 * aarch64-asm-2.c: Regenerate. 332 * aarch64-dis-2.c: Regenerate. 333 * aarch64-dis.c: Weaken assert. 334 * aarch64-gen.c: Include the instruction in the list of its 335 possible aliases. 336 3372015-11-27 Matthew Wahab <matthew.wahab@arm.com> 338 339 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1". 340 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register 341 feature test. 342 3432015-11-23 Tristan Gingold <gingold@adacore.com> 344 345 * arm-dis.c (print_insn): Also set is_thumb for Mach-O. 346 3472015-11-20 Matthew Wahab <matthew.wahab@arm.com> 348 349 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12, 350 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12, 351 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12, 352 amair_el12, vbar_el12, contextidr_el2, contextidr_el12, 353 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02, 354 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2, 355 cnthv_ctl_el2, cnthv_cval_el2. 356 (aarch64_sys_reg_supported_p): Update for the new system 357 registers. 358 3592015-11-20 Nick Clifton <nickc@redhat.com> 360 361 PR binutils/19224 362 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause. 363 3642015-11-20 Nick Clifton <nickc@redhat.com> 365 366 * po/zh_CN.po: Updated simplified Chinese translation. 367 3682015-11-19 Matthew Wahab <matthew.wahab@arm.com> 369 370 * aarch64-opc.c (operand_general_constraint_met_p): Check validity 371 of MSR PAN immediate operand. 372 3732015-11-16 Nick Clifton <nickc@redhat.com> 374 375 * rx-dis.c (condition_names): Replace always and never with 376 invalid, since the always/never conditions can never be legal. 377 3782015-11-13 Tristan Gingold <gingold@adacore.com> 379 380 * configure: Regenerate. 381 3822015-11-11 Alan Modra <amodra@gmail.com> 383 Peter Bergner <bergner@vnet.ibm.com> 384 385 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries. 386 Add PPC_OPCODE_VSX3 to the vsx entry. 387 (powerpc_init_dialect): Set default dialect to power9. 388 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, 389 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1, 390 extract_l1 insert_xtq6, extract_xtq6): New static functions. 391 (insert_esync): Test for illegal L operand value. 392 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6, 393 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA, 394 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK, 395 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3, 396 PPCVSX3): New defines. 397 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu, 398 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK. 399 <mcrxr>: Use XBFRARB_MASK. 400 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq., 401 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc., 402 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first, 403 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx, 404 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll, 405 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw, 406 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last, 407 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx, 408 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx, 409 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh, 410 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh., 411 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd, 412 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d, 413 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx, 414 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq, 415 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd, 416 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait, 417 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp, 418 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp, 419 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz, 420 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp, 421 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp, 422 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo, 423 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo, 424 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo, 425 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp, 426 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp, 427 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp, 428 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw, 429 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions. 430 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9. 431 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands. 432 4332015-11-02 Nick Clifton <nickc@redhat.com> 434 435 * rx-decode.opc (rx_decode_opcode): Decode extra NOP 436 instructions. 437 * rx-decode.c: Regenerate. 438 4392015-11-02 Nick Clifton <nickc@redhat.com> 440 441 * rx-decode.opc (rx_disp): If the displacement is zero, set the 442 type to RX_Operand_Zero_Indirect. 443 * rx-decode.c: Regenerate. 444 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect. 445 4462015-10-28 Yao Qi <yao.qi@linaro.org> 447 448 * aarch64-dis.c (aarch64_decode_insn): Add one argument 449 noaliases_p. Update comments. Pass noaliases_p rather than 450 no_aliases to aarch64_opcode_decode. 451 (print_insn_aarch64_word): Pass no_aliases to 452 aarch64_decode_insn. 453 4542015-10-27 Vinay <Vinay.G@kpit.com> 455 456 PR binutils/19159 457 * rl78-decode.opc (MOV): Added offset to DE register in index 458 addressing mode. 459 * rl78-decode.c: Regenerate. 460 4612015-10-27 Vinay Kumar <vinay.g@kpit.com> 462 463 PR binutils/19158 464 * rl78-decode.opc: Add 's' print operator to instructions that 465 access system registers. 466 * rl78-decode.c: Regenerate. 467 * rl78-dis.c (print_insn_rl78_common): Decode all system 468 registers. 469 4702015-10-27 Vinay Kumar <vinay.g@kpit.com> 471 472 PR binutils/19157 473 * rl78-decode.opc: Add 'a' print operator to mov instructions 474 using stack pointer plus index addressing. 475 * rl78-decode.c: Regenerate. 476 4772015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com> 478 479 * s390-opc.c: Fix comment. 480 * s390-opc.txt: Change instruction type for troo, trot, trto, and 481 trtt to RRF_U0RER since the second parameter does not need to be a 482 register pair. 483 4842015-10-08 Nick Clifton <nickc@redhat.com> 485 486 * arc-dis.c (print_insn_arc): Initiallise insn array. 487 4882015-10-07 Yao Qi <yao.qi@linaro.org> 489 490 * aarch64-dis.c (aarch64_ext_sysins_op): Access field 491 'name' rather than 'template'. 492 * aarch64-opc.c (aarch64_print_operand): Likewise. 493 4942015-10-07 Claudiu Zissulescu <claziss@synopsys.com> 495 496 * arc-dis.c: Revamped file for ARC support 497 * arc-dis.h: Likewise. 498 * arc-ext.c: Likewise. 499 * arc-ext.h: Likewise. 500 * arc-opc.c: Likewise. 501 * arc-fxi.h: New file. 502 * arc-regs.h: Likewise. 503 * arc-tbl.h: Likewise. 504 5052015-10-02 Yao Qi <yao.qi@linaro.org> 506 507 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change 508 argument insn type to aarch64_insn. Rename to ... 509 (aarch64_decode_insn): ... it. 510 (print_insn_aarch64_word): Caller updated. 511 5122015-10-02 Yao Qi <yao.qi@linaro.org> 513 514 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC. 515 (print_insn_aarch64_word): Caller updated. 516 5172015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com> 518 519 * s390-mkopc.c (main): Parse htm and vx flag. 520 * s390-opc.txt: Mark instructions from the hardware transactional 521 memory and vector facilities with the "htm"/"vx" flag. 522 5232015-09-28 Nick Clifton <nickc@redhat.com> 524 525 * po/de.po: Updated German translation. 526 5272015-09-28 Tom Rix <tom@bumblecow.com> 528 529 * ppc-opc.c (PPC500): Mark some opcodes as invalid 530 5312015-09-23 Nick Clifton <nickc@redhat.com> 532 533 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs 534 function. 535 * tic30-dis.c (print_branch): Likewise. 536 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed 537 value before left shifting. 538 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise. 539 * hppa-dis.c (print_insn_hppa): Likewise. 540 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static 541 array. 542 * msp430-dis.c (msp430_singleoperand): Likewise. 543 (msp430_doubleoperand): Likewise. 544 (print_insn_msp430): Likewise. 545 * nds32-asm.c (parse_operand): Likewise. 546 * sh-opc.h (MASK): Likewise. 547 * v850-dis.c (get_operand_value): Likewise. 548 5492015-09-22 Nick Clifton <nickc@redhat.com> 550 551 * rx-decode.opc (bwl): Use RX_Bad_Size. 552 (sbwl): Likewise. 553 (ubwl): Likewise. Rename to ubw. 554 (uBWL): Rename to uBW. 555 Replace all references to uBWL with uBW. 556 * rx-decode.c: Regenerate. 557 * rx-dis.c (size_names): Add entry for RX_Bad_Size. 558 (opsize_names): Likewise. 559 (print_insn_rx): Detect and report RX_Bad_Size. 560 5612015-09-22 Anton Blanchard <anton@samba.org> 562 563 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl. 564 5652015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com> 566 567 * sparc-dis.c (print_insn_sparc): Handle the privileged register 568 %pmcdper. 569 5702015-08-24 Jan Stancek <jstancek@redhat.com> 571 572 * i386-dis.c (print_insn): Fix decoding of three byte operands. 573 5742015-08-21 Alexander Fomin <alexander.fomin@intel.com> 575 576 PR binutils/18257 577 * i386-dis.c: Use MOD_TABLE for most of mask instructions. 578 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1, 579 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1, 580 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1, 581 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1, 582 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1, 583 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1, 584 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1, 585 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1, 586 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1, 587 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1, 588 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1, 589 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1, 590 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1, 591 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1, 592 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1, 593 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1, 594 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0, 595 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0, 596 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0, 597 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0, 598 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0, 599 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0, 600 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0, 601 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0, 602 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0, 603 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0, 604 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0, 605 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0, 606 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0, 607 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0. 608 (vex_w_table): Replace terminals with MOD_TABLE entries for 609 most of mask instructions. 610 6112015-08-17 Alan Modra <amodra@gmail.com> 612 613 * cgen.sh: Trim trailing space from cgen output. 614 * ia64-gen.c (print_dependency_table): Don't generate trailing space. 615 (print_dis_table): Likewise. 616 * opc2c.c (dump_lines): Likewise. 617 (orig_filename): Warning fix. 618 * ia64-asmtab.c: Regenerate. 619 6202015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com> 621 622 * arm-dis.c (print_insn_arm): Disassembling for all targets V6 623 and higher with ARM instruction set will now mark the 26-bit 624 versions of teq,tst,cmn and cmp as UNPREDICTABLE. 625 (arm_opcodes): Fix for unpredictable nop being recognized as a 626 teq. 627 6282015-08-12 Simon Dardis <simon.dardis@imgtec.com> 629 630 * micromips-opc.c (micromips_opcodes): Re-order table so that move 631 based on 'or' is first. 632 * mips-opc.c (mips_builtin_opcodes): Ditto. 633 6342015-08-11 Nick Clifton <nickc@redhat.com> 635 636 PR 18800 637 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT 638 instruction. 639 6402015-08-10 Robert Suchanek <robert.suchanek@imgtec.com> 641 642 * mips-opc.c (mips_builtin_opcodes): Add "sigrie". 643 6442015-08-07 Amit Pawar <Amit.Pawar@amd.com> 645 646 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS. 647 * i386-init.h: Regenerated. 648 6492015-07-30 H.J. Lu <hongjiu.lu@intel.com> 650 651 PR binutils/13571 652 * i386-dis.c (MOD_0FC3): New. 653 (PREFIX_0FC3): Renamed to ... 654 (PREFIX_MOD_0_0FC3): This. 655 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3. 656 (prefix_table): Replace Ma with Ev on movntiS. 657 (mod_table): Add MOD_0FC3. 658 6592015-07-27 H.J. Lu <hongjiu.lu@intel.com> 660 661 * configure: Regenerated. 662 6632015-07-23 Alan Modra <amodra@gmail.com> 664 665 PR 18708 666 * i386-dis.c (get64): Avoid signed integer overflow. 667 6682015-07-22 Alexander Fomin <alexander.fomin@intel.com> 669 670 PR binutils/18631 671 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with 672 "EXEvexHalfBcstXmmq" for the second operand. 673 (EVEX_W_0F79_P_2): Likewise. 674 (EVEX_W_0F7A_P_2): Likewise. 675 (EVEX_W_0F7B_P_2): Likewise. 676 6772015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com> 678 679 * arm-dis.c (print_insn_coprocessor): Added support for quarter 680 float bitfield format. 681 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new 682 quarter float bitfield format. 683 6842015-07-14 H.J. Lu <hongjiu.lu@intel.com> 685 686 * configure: Regenerated. 687 6882015-07-03 Alan Modra <amodra@gmail.com> 689 690 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*. 691 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add 692 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry. 693 6942015-07-01 Sandra Loosemore <sandra@codesourcery.com> 695 Cesar Philippidis <cesar@codesourcery.com> 696 697 * nios2-dis.c (nios2_extract_opcode): New. 698 (nios2_disassembler_state): New. 699 (nios2_find_opcode_hash): Use mach parameter to select correct 700 disassembler state. 701 (nios2_print_insn_arg): Extend to support new R2 argument letters 702 and formats. 703 (print_insn_nios2): Check for 16-bit instruction at end of memory. 704 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes. 705 (NIOS2_NUM_OPCODES): Rename to... 706 (NIOS2_NUM_R1_OPCODES): This. 707 (nios2_r2_opcodes): New. 708 (NIOS2_NUM_R2_OPCODES): New. 709 (nios2_num_r2_opcodes): New. 710 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New. 711 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New. 712 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New. 713 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New. 714 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New. 715 7162015-06-30 Amit Pawar <Amit.Pawar@amd.com> 717 718 * i386-dis.c (OP_Mwaitx): New. 719 (rm_table): Add monitorx/mwaitx. 720 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS 721 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS. 722 (operand_type_init): Add CpuMWAITX. 723 * i386-opc.h (CpuMWAITX): New. 724 (i386_cpu_flags): Add cpumwaitx. 725 * i386-opc.tbl: Add monitorx and mwaitx. 726 * i386-init.h: Regenerated. 727 * i386-tbl.h: Likewise. 728 7292015-06-22 Peter Bergner <bergner@vnet.ibm.com> 730 731 * ppc-opc.c (insert_ls): Test for invalid LS operands. 732 (insert_esync): New function. 733 (LS, WC): Use insert_ls. 734 (ESYNC): Use insert_esync. 735 7362015-06-22 Nick Clifton <nickc@redhat.com> 737 738 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the 739 requested region lies beyond it. 740 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when 741 looking for 32-bit insns. 742 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading 743 data. 744 * sh-dis.c (print_insn_sh): Likewise. 745 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading 746 blocks of instructions. 747 * vax-dis.c (print_insn_vax): Check that the requested address 748 does not clash with the stop_vma. 749 7502015-06-19 Peter Bergner <bergner@vnet.ibm.com> 751 752 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value. 753 * ppc-opc.c (FXM4): Add non-zero optional value. 754 (TBR): Likewise. 755 (SXL): Likewise. 756 (insert_fxm): Handle new default operand value. 757 (extract_fxm): Likewise. 758 (insert_tbr): Likewise. 759 (extract_tbr): Likewise. 760 7612015-06-16 Matthew Wahab <matthew.wahab@arm.com> 762 763 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1". 764 7652015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com> 766 767 * arm-dis.c (print_insn_coprocessor): Avoid negative shift. 768 7692015-06-12 Peter Bergner <bergner@vnet.ibm.com> 770 771 * ppc-opc.c: Add comment accidentally removed by old commit. 772 (MTMSRD_L): Delete. 773 7742015-06-04 Peter Bergner <bergner@vnet.ibm.com> 775 776 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic. 777 7782015-06-04 Nick Clifton <nickc@redhat.com> 779 780 PR 18474 781 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns. 782 7832015-06-02 Matthew Wahab <matthew.wahab@arm.com> 784 785 * arm-dis.c (arm_opcodes): Add "setpan". 786 (thumb_opcodes): Add "setpan". 787 7882015-06-02 Matthew Wahab <matthew.wahab@arm.com> 789 790 * arm-dis.c (select_arm_features): Rework to avoid used of redefined 791 macros. 792 7932015-06-02 Matthew Wahab <matthew.wahab@arm.com> 794 795 * aarch64-tbl.h (aarch64_feature_rdma): New. 796 (RDMA): New. 797 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions. 798 * aarch64-asm-2.c: Regenerate. 799 * aarch64-dis-2.c: Regenerate. 800 * aarch64-opc-2.c: Regenerate. 801 8022015-06-02 Matthew Wahab <matthew.wahab@arm.com> 803 804 * aarch64-tbl.h (aarch64_feature_lor): New. 805 (LOR): New. 806 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr", 807 "stllrb", "stllrh". 808 * aarch64-asm-2.c: Regenerate. 809 * aarch64-dis-2.c: Regenerate. 810 * aarch64-opc-2.c: Regenerate. 811 8122015-06-01 Matthew Wahab <matthew.wahab@arm.com> 813 814 * aarch64-opc.c (F_ARCHEXT): New. 815 (aarch64_sys_regs): Add "pan". 816 (aarch64_sys_reg_supported_p): New. 817 (aarch64_pstatefields): Add "pan". 818 (aarch64_pstatefield_supported_p): New. 819 8202015-06-01 Jan Beulich <jbeulich@suse.com> 821 822 * i386-tbl.h: Regenerate. 823 8242015-06-01 Jan Beulich <jbeulich@suse.com> 825 826 * i386-dis.c (print_insn): Swap rounding mode specifier and 827 general purpose register in Intel mode. 828 8292015-06-01 Jan Beulich <jbeulich@suse.com> 830 831 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}. 832 * i386-tbl.h: Regenerate. 833 8342015-05-18 H.J. Lu <hongjiu.lu@intel.com> 835 836 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp. 837 * i386-init.h: Regenerated. 838 8392015-05-15 H.J. Lu <hongjiu.lu@intel.com> 840 841 PR binutis/18386 842 * i386-dis.c: Add comments for '@'. 843 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9. 844 (enum x86_64_isa): New. 845 (isa64): Likewise. 846 (print_i386_disassembler_options): Add amd64 and intel64. 847 (print_insn): Handle amd64 and intel64. 848 (putop): Handle '@'. 849 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit. 850 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64. 851 * i386-opc.h (AMD64): New. 852 (CpuIntel64): Likewise. 853 (i386_cpu_flags): Add cpuamd64 and cpuintel64. 854 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64. 855 Mark direct call/jmp without Disp16|Disp32 as Intel64. 856 * i386-init.h: Regenerated. 857 * i386-tbl.h: Likewise. 858 8592015-05-14 Peter Bergner <bergner@vnet.ibm.com> 860 861 * ppc-opc.c (IH) New define. 862 (powerpc_opcodes) <wait>: Do not enable for POWER7. 863 <tlbie>: Add RS operand for POWER7. 864 <slbia>: Add IH operand for POWER6. 865 8662015-05-11 H.J. Lu <hongjiu.lu@intel.com> 867 868 * i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit 869 direct branch. 870 (jmp): Likewise. 871 * i386-tbl.h: Regenerated. 872 8732015-05-11 H.J. Lu <hongjiu.lu@intel.com> 874 875 * configure.ac: Support bfd_iamcu_arch. 876 * disassemble.c (disassembler): Support bfd_iamcu_arch. 877 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and 878 CPU_IAMCU_COMPAT_FLAGS. 879 (cpu_flags): Add CpuIAMCU. 880 * i386-opc.h (CpuIAMCU): New. 881 (i386_cpu_flags): Add cpuiamcu. 882 * configure: Regenerated. 883 * i386-init.h: Likewise. 884 * i386-tbl.h: Likewise. 885 8862015-05-08 H.J. Lu <hongjiu.lu@intel.com> 887 888 PR binutis/18386 889 * i386-dis.c (X86_64_E8): New. 890 (X86_64_E9): Likewise. 891 Update comments on 'T', 'U', 'V'. Add comments for '^'. 892 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9. 893 (x86_64_table): Add X86_64_E8 and X86_64_E9. 894 (mod_table): Replace {T|} with ^ on Jcall/Jmp. 895 (putop): Handle '^'. 896 (OP_J): Ignore the operand size prefix in 64-bit. Don't check 897 REX_W. 898 8992015-04-30 DJ Delorie <dj@redhat.com> 900 901 * disassemble.c (disassembler): Choose suitable disassembler based 902 on E_ABI. 903 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use 904 it to decode mul/div insns. 905 * rl78-decode.c: Regenerate. 906 * rl78-dis.c (print_insn_rl78): Rename to... 907 (print_insn_rl78_common): ...this, take ISA parameter. 908 (print_insn_rl78): New. 909 (print_insn_rl78_g10): New. 910 (print_insn_rl78_g13): New. 911 (print_insn_rl78_g14): New. 912 (rl78_get_disassembler): New. 913 9142015-04-29 Nick Clifton <nickc@redhat.com> 915 916 * po/fr.po: Updated French translation. 917 9182015-04-27 Peter Bergner <bergner@vnet.ibm.com> 919 920 * ppc-opc.c (DCBT_EO): New define. 921 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later. 922 <lharx>: Likewise. 923 <stbcx.>: Likewise. 924 <sthcx.>: Likewise. 925 <waitrsv>: Do not enable for POWER7 and later. 926 <waitimpl>: Likewise. 927 <dcbt>: Default to the two operand form of the instruction for all 928 "old" cpus. For "new" cpus, use the operand ordering that matches 929 whether the cpu is server or embedded. 930 <dcbtst>: Likewise. 931 9322015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com> 933 934 * s390-opc.c: New instruction type VV0UU2. 935 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK, 936 and WFC. 937 9382015-04-23 Jan Beulich <jbeulich@suse.com> 939 940 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ". 941 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq, 942 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY. 943 (vfpclasspd, vfpclassps): Add %XZ. 944 9452015-04-15 H.J. Lu <hongjiu.lu@intel.com> 946 947 * i386-dis.c (PREFIX_UD_SHIFT): Removed. 948 (PREFIX_UD_REPZ): Likewise. 949 (PREFIX_UD_REPNZ): Likewise. 950 (PREFIX_UD_DATA): Likewise. 951 (PREFIX_UD_ADDR): Likewise. 952 (PREFIX_UD_LOCK): Likewise. 953 9542015-04-15 H.J. Lu <hongjiu.lu@intel.com> 955 956 * i386-dis.c (prefix_requirement): Removed. 957 (print_insn): Don't set prefix_requirement. Check 958 dp->prefix_requirement instead of prefix_requirement. 959 9602015-04-15 H.J. Lu <hongjiu.lu@intel.com> 961 962 PR binutils/17898 963 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ... 964 (PREFIX_MOD_0_0FC7_REG_6): This. 965 (PREFIX_MOD_3_0FC7_REG_6): New. 966 (PREFIX_MOD_3_0FC7_REG_7): Likewise. 967 (prefix_table): Replace PREFIX_0FC7_REG_6 with 968 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and 969 PREFIX_MOD_3_0FC7_REG_7. 970 (mod_table): Replace PREFIX_0FC7_REG_6 with 971 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and 972 PREFIX_MOD_3_0FC7_REG_7. 973 9742015-04-15 H.J. Lu <hongjiu.lu@intel.com> 975 976 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed. 977 (PREFIX_MANDATORY_REPNZ): Likewise. 978 (PREFIX_MANDATORY_DATA): Likewise. 979 (PREFIX_MANDATORY_ADDR): Likewise. 980 (PREFIX_MANDATORY_LOCK): Likewise. 981 (PREFIX_MANDATORY): Likewise. 982 (PREFIX_UD_SHIFT): Set to 8 983 (PREFIX_UD_REPZ): Updated. 984 (PREFIX_UD_REPNZ): Likewise. 985 (PREFIX_UD_DATA): Likewise. 986 (PREFIX_UD_ADDR): Likewise. 987 (PREFIX_UD_LOCK): Likewise. 988 (PREFIX_IGNORED_SHIFT): New. 989 (PREFIX_IGNORED_REPZ): Likewise. 990 (PREFIX_IGNORED_REPNZ): Likewise. 991 (PREFIX_IGNORED_DATA): Likewise. 992 (PREFIX_IGNORED_ADDR): Likewise. 993 (PREFIX_IGNORED_LOCK): Likewise. 994 (PREFIX_OPCODE): Likewise. 995 (PREFIX_IGNORED): Likewise. 996 (Bad_Opcode): Replace PREFIX_MANDATORY with 0. 997 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE. 998 (three_byte_table): Likewise. 999 (mod_table): Likewise. 1000 (mandatory_prefix): Renamed to ... 1001 (prefix_requirement): This. 1002 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE. 1003 Update PREFIX_90 entry. 1004 (get_valid_dis386): Check prefix_requirement to see if a prefix 1005 should be ignored. 1006 (print_insn): Replace mandatory_prefix with prefix_requirement. 1007 10082015-04-15 Renlin Li <renlin.li@arm.com> 1009 1010 * arm-dis.c (thumb32_opcodes): Define 'D' format control code, 1011 use it for ssat and ssat16. 1012 (print_insn_thumb32): Add handle case for 'D' control code. 1013 10142015-04-06 Ilya Tocar <ilya.tocar@intel.com> 1015 H.J. Lu <hongjiu.lu@intel.com> 1016 1017 * i386-dis-evex.h (evex_table): Fill prefix_requirement field. 1018 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ, 1019 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK, 1020 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA, 1021 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define. 1022 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX): 1023 Fill prefix_requirement field. 1024 (struct dis386): Add prefix_requirement field. 1025 (dis386): Fill prefix_requirement field. 1026 (dis386_twobyte): Ditto. 1027 (twobyte_has_mandatory_prefix_: Remove. 1028 (reg_table): Fill prefix_requirement field. 1029 (prefix_table): Ditto. 1030 (x86_64_table): Ditto. 1031 (three_byte_table): Ditto. 1032 (xop_table): Ditto. 1033 (vex_table): Ditto. 1034 (vex_len_table): Ditto. 1035 (vex_w_table): Ditto. 1036 (mod_table): Ditto. 1037 (bad_opcode): Ditto. 1038 (print_insn): Use prefix_requirement. 1039 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4, 1040 FGRPde_3, FGRPdf_4): Fill prefix_requirement field. 1041 (float_reg): Ditto. 1042 10432015-03-30 Mike Frysinger <vapier@gentoo.org> 1044 1045 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype. 1046 10472015-03-29 H.J. Lu <hongjiu.lu@intel.com> 1048 1049 * Makefile.in: Regenerated. 1050 10512015-03-25 Anton Blanchard <anton@samba.org> 1052 1053 * ppc-dis.c (disassemble_init_powerpc): Only initialise 1054 powerpc_opcd_indices and vle_opcd_indices once. 1055 10562015-03-25 Anton Blanchard <anton@samba.org> 1057 1058 * ppc-opc.c (powerpc_opcodes): Add slbfee. 1059 10602015-03-24 Terry Guo <terry.guo@arm.com> 1061 1062 * arm-dis.c (opcode32): Updated to use new arm feature struct. 1063 (opcode16): Likewise. 1064 (coprocessor_opcodes): Replace bit with feature struct. 1065 (neon_opcodes): Likewise. 1066 (arm_opcodes): Likewise. 1067 (thumb_opcodes): Likewise. 1068 (thumb32_opcodes): Likewise. 1069 (print_insn_coprocessor): Likewise. 1070 (print_insn_arm): Likewise. 1071 (select_arm_features): Follow new feature struct. 1072 10732015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> 1074 1075 * i386-dis.c (rm_table): Add clzero. 1076 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS. 1077 Add CPU_CLZERO_FLAGS. 1078 (cpu_flags): Add CpuCLZERO. 1079 * i386-opc.h: Add CpuCLZERO. 1080 * i386-opc.tbl: Add clzero. 1081 * i386-init.h: Re-generated. 1082 * i386-tbl.h: Re-generated. 1083 10842015-03-13 Andrew Bennett <andrew.bennett@imgtec.com> 1085 1086 * mips-opc.c (decode_mips_operand): Fix constraint issues 1087 with u and y operands. 1088 10892015-03-13 Andrew Bennett <andrew.bennett@imgtec.com> 1090 1091 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions. 1092 10932015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> 1094 1095 * s390-opc.c: Add new IBM z13 instructions. 1096 * s390-opc.txt: Likewise. 1097 10982015-03-10 Renlin Li <renlin.li@arm.com> 1099 1100 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb, 1101 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and 1102 related alias. 1103 * aarch64-asm-2.c: Regenerate. 1104 * aarch64-dis-2.c: Likewise. 1105 * aarch64-opc-2.c: Likewise. 1106 11072015-03-03 Jiong Wang <jiong.wang@arm.com> 1108 1109 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols. 1110 11112015-02-25 Oleg Endo <olegendo@gcc.gnu.org> 1112 1113 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of 1114 arch_sh_up. 1115 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of 1116 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up. 1117 11182015-02-23 Vinay <Vinay.G@kpit.com> 1119 1120 * rl78-decode.opc (MOV): Added space between two operands for 1121 'mov' instruction in index addressing mode. 1122 * rl78-decode.c: Regenerate. 1123 11242015-02-19 Pedro Alves <palves@redhat.com> 1125 1126 * microblaze-dis.h [__cplusplus]: Wrap in extern "C". 1127 11282015-02-10 Pedro Alves <palves@redhat.com> 1129 Tom Tromey <tromey@redhat.com> 1130 1131 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or, 1132 microblaze_and, microblaze_xor. 1133 * microblaze-opc.h (opcodes): Adjust. 1134 11352015-01-28 James Bowman <james.bowman@ftdichip.com> 1136 1137 * Makefile.am: Add FT32 files. 1138 * configure.ac: Handle FT32. 1139 * disassemble.c (disassembler): Call print_insn_ft32. 1140 * ft32-dis.c: New file. 1141 * ft32-opc.c: New file. 1142 * Makefile.in: Regenerate. 1143 * configure: Regenerate. 1144 * po/POTFILES.in: Regenerate. 1145 11462015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com> 1147 1148 * nds32-asm.c (keyword_sr): Add new system registers. 1149 11502015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com> 1151 1152 * s390-dis.c (s390_extract_operand): Support vector register 1153 operands. 1154 (s390_print_insn_with_opcode): Support new operands types and add 1155 new handling of optional operands. 1156 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove 1157 and include opcode/s390.h instead. 1158 (struct op_struct): New field `flags'. 1159 (insertOpcode, insertExpandedMnemonic): New parameter `flags'. 1160 (dumpTable): Dump flags. 1161 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu 1162 string. 1163 * s390-opc.c: Add new operands types, instruction formats, and 1164 instruction masks. 1165 (s390_opformats): Add new formats for .insn. 1166 * s390-opc.txt: Add new instructions. 1167 11682015-01-01 Alan Modra <amodra@gmail.com> 1169 1170 Update year range in copyright notice of all files. 1171 1172For older changes see ChangeLog-2014 1173 1174Copyright (C) 2015 Free Software Foundation, Inc. 1175 1176Copying and distribution of this file, with or without modification, 1177are permitted in any medium without royalty provided the copyright 1178notice and this notice are preserved. 1179 1180Local Variables: 1181mode: change-log 1182left-margin: 8 1183fill-column: 74 1184version-control: never 1185End: 1186