1 /*
2 * Copyright (C) 2017 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include "managed_register_mips64.h"
18 #include "globals.h"
19 #include "gtest/gtest.h"
20
21 namespace art {
22 namespace mips64 {
23
TEST(Mips64ManagedRegister,NoRegister)24 TEST(Mips64ManagedRegister, NoRegister) {
25 Mips64ManagedRegister reg = ManagedRegister::NoRegister().AsMips64();
26 EXPECT_TRUE(reg.IsNoRegister());
27 EXPECT_FALSE(reg.Overlaps(reg));
28 }
29
TEST(Mips64ManagedRegister,GpuRegister)30 TEST(Mips64ManagedRegister, GpuRegister) {
31 Mips64ManagedRegister reg = Mips64ManagedRegister::FromGpuRegister(ZERO);
32 EXPECT_FALSE(reg.IsNoRegister());
33 EXPECT_TRUE(reg.IsGpuRegister());
34 EXPECT_FALSE(reg.IsFpuRegister());
35 EXPECT_FALSE(reg.IsVectorRegister());
36 EXPECT_EQ(ZERO, reg.AsGpuRegister());
37
38 reg = Mips64ManagedRegister::FromGpuRegister(AT);
39 EXPECT_FALSE(reg.IsNoRegister());
40 EXPECT_TRUE(reg.IsGpuRegister());
41 EXPECT_FALSE(reg.IsFpuRegister());
42 EXPECT_FALSE(reg.IsVectorRegister());
43 EXPECT_EQ(AT, reg.AsGpuRegister());
44
45 reg = Mips64ManagedRegister::FromGpuRegister(V0);
46 EXPECT_FALSE(reg.IsNoRegister());
47 EXPECT_TRUE(reg.IsGpuRegister());
48 EXPECT_FALSE(reg.IsFpuRegister());
49 EXPECT_FALSE(reg.IsVectorRegister());
50 EXPECT_EQ(V0, reg.AsGpuRegister());
51
52 reg = Mips64ManagedRegister::FromGpuRegister(A0);
53 EXPECT_FALSE(reg.IsNoRegister());
54 EXPECT_TRUE(reg.IsGpuRegister());
55 EXPECT_FALSE(reg.IsFpuRegister());
56 EXPECT_FALSE(reg.IsVectorRegister());
57 EXPECT_EQ(A0, reg.AsGpuRegister());
58
59 reg = Mips64ManagedRegister::FromGpuRegister(A7);
60 EXPECT_FALSE(reg.IsNoRegister());
61 EXPECT_TRUE(reg.IsGpuRegister());
62 EXPECT_FALSE(reg.IsFpuRegister());
63 EXPECT_FALSE(reg.IsVectorRegister());
64 EXPECT_EQ(A7, reg.AsGpuRegister());
65
66 reg = Mips64ManagedRegister::FromGpuRegister(T0);
67 EXPECT_FALSE(reg.IsNoRegister());
68 EXPECT_TRUE(reg.IsGpuRegister());
69 EXPECT_FALSE(reg.IsFpuRegister());
70 EXPECT_FALSE(reg.IsVectorRegister());
71 EXPECT_EQ(T0, reg.AsGpuRegister());
72
73 reg = Mips64ManagedRegister::FromGpuRegister(T3);
74 EXPECT_FALSE(reg.IsNoRegister());
75 EXPECT_TRUE(reg.IsGpuRegister());
76 EXPECT_FALSE(reg.IsFpuRegister());
77 EXPECT_FALSE(reg.IsVectorRegister());
78 EXPECT_EQ(T3, reg.AsGpuRegister());
79
80 reg = Mips64ManagedRegister::FromGpuRegister(S0);
81 EXPECT_FALSE(reg.IsNoRegister());
82 EXPECT_TRUE(reg.IsGpuRegister());
83 EXPECT_FALSE(reg.IsFpuRegister());
84 EXPECT_FALSE(reg.IsVectorRegister());
85 EXPECT_EQ(S0, reg.AsGpuRegister());
86
87 reg = Mips64ManagedRegister::FromGpuRegister(GP);
88 EXPECT_FALSE(reg.IsNoRegister());
89 EXPECT_TRUE(reg.IsGpuRegister());
90 EXPECT_FALSE(reg.IsFpuRegister());
91 EXPECT_FALSE(reg.IsVectorRegister());
92 EXPECT_EQ(GP, reg.AsGpuRegister());
93
94 reg = Mips64ManagedRegister::FromGpuRegister(SP);
95 EXPECT_FALSE(reg.IsNoRegister());
96 EXPECT_TRUE(reg.IsGpuRegister());
97 EXPECT_FALSE(reg.IsFpuRegister());
98 EXPECT_FALSE(reg.IsVectorRegister());
99 EXPECT_EQ(SP, reg.AsGpuRegister());
100
101 reg = Mips64ManagedRegister::FromGpuRegister(RA);
102 EXPECT_FALSE(reg.IsNoRegister());
103 EXPECT_TRUE(reg.IsGpuRegister());
104 EXPECT_FALSE(reg.IsFpuRegister());
105 EXPECT_FALSE(reg.IsVectorRegister());
106 EXPECT_EQ(RA, reg.AsGpuRegister());
107 }
108
TEST(Mips64ManagedRegister,FpuRegister)109 TEST(Mips64ManagedRegister, FpuRegister) {
110 Mips64ManagedRegister reg = Mips64ManagedRegister::FromFpuRegister(F0);
111 Mips64ManagedRegister vreg = Mips64ManagedRegister::FromVectorRegister(W0);
112 EXPECT_FALSE(reg.IsNoRegister());
113 EXPECT_FALSE(reg.IsGpuRegister());
114 EXPECT_TRUE(reg.IsFpuRegister());
115 EXPECT_FALSE(reg.IsVectorRegister());
116 EXPECT_TRUE(reg.Overlaps(vreg));
117 EXPECT_EQ(F0, reg.AsFpuRegister());
118 EXPECT_EQ(W0, reg.AsOverlappingVectorRegister());
119 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
120
121 reg = Mips64ManagedRegister::FromFpuRegister(F1);
122 vreg = Mips64ManagedRegister::FromVectorRegister(W1);
123 EXPECT_FALSE(reg.IsNoRegister());
124 EXPECT_FALSE(reg.IsGpuRegister());
125 EXPECT_TRUE(reg.IsFpuRegister());
126 EXPECT_FALSE(reg.IsVectorRegister());
127 EXPECT_TRUE(reg.Overlaps(vreg));
128 EXPECT_EQ(F1, reg.AsFpuRegister());
129 EXPECT_EQ(W1, reg.AsOverlappingVectorRegister());
130 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromFpuRegister(F1)));
131
132 reg = Mips64ManagedRegister::FromFpuRegister(F20);
133 vreg = Mips64ManagedRegister::FromVectorRegister(W20);
134 EXPECT_FALSE(reg.IsNoRegister());
135 EXPECT_FALSE(reg.IsGpuRegister());
136 EXPECT_TRUE(reg.IsFpuRegister());
137 EXPECT_FALSE(reg.IsVectorRegister());
138 EXPECT_TRUE(reg.Overlaps(vreg));
139 EXPECT_EQ(F20, reg.AsFpuRegister());
140 EXPECT_EQ(W20, reg.AsOverlappingVectorRegister());
141 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromFpuRegister(F20)));
142
143 reg = Mips64ManagedRegister::FromFpuRegister(F31);
144 vreg = Mips64ManagedRegister::FromVectorRegister(W31);
145 EXPECT_FALSE(reg.IsNoRegister());
146 EXPECT_FALSE(reg.IsGpuRegister());
147 EXPECT_TRUE(reg.IsFpuRegister());
148 EXPECT_FALSE(reg.IsVectorRegister());
149 EXPECT_TRUE(reg.Overlaps(vreg));
150 EXPECT_EQ(F31, reg.AsFpuRegister());
151 EXPECT_EQ(W31, reg.AsOverlappingVectorRegister());
152 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromFpuRegister(F31)));
153 }
154
TEST(Mips64ManagedRegister,VectorRegister)155 TEST(Mips64ManagedRegister, VectorRegister) {
156 Mips64ManagedRegister reg = Mips64ManagedRegister::FromVectorRegister(W0);
157 Mips64ManagedRegister freg = Mips64ManagedRegister::FromFpuRegister(F0);
158 EXPECT_FALSE(reg.IsNoRegister());
159 EXPECT_FALSE(reg.IsGpuRegister());
160 EXPECT_FALSE(reg.IsFpuRegister());
161 EXPECT_TRUE(reg.IsVectorRegister());
162 EXPECT_TRUE(reg.Overlaps(freg));
163 EXPECT_EQ(W0, reg.AsVectorRegister());
164 EXPECT_EQ(F0, reg.AsOverlappingFpuRegister());
165 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromVectorRegister(W0)));
166
167 reg = Mips64ManagedRegister::FromVectorRegister(W2);
168 freg = Mips64ManagedRegister::FromFpuRegister(F2);
169 EXPECT_FALSE(reg.IsNoRegister());
170 EXPECT_FALSE(reg.IsGpuRegister());
171 EXPECT_FALSE(reg.IsFpuRegister());
172 EXPECT_TRUE(reg.IsVectorRegister());
173 EXPECT_TRUE(reg.Overlaps(freg));
174 EXPECT_EQ(W2, reg.AsVectorRegister());
175 EXPECT_EQ(F2, reg.AsOverlappingFpuRegister());
176 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromVectorRegister(W2)));
177
178 reg = Mips64ManagedRegister::FromVectorRegister(W13);
179 freg = Mips64ManagedRegister::FromFpuRegister(F13);
180 EXPECT_FALSE(reg.IsNoRegister());
181 EXPECT_FALSE(reg.IsGpuRegister());
182 EXPECT_FALSE(reg.IsFpuRegister());
183 EXPECT_TRUE(reg.IsVectorRegister());
184 EXPECT_TRUE(reg.Overlaps(freg));
185 EXPECT_EQ(W13, reg.AsVectorRegister());
186 EXPECT_EQ(F13, reg.AsOverlappingFpuRegister());
187 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromVectorRegister(W13)));
188
189 reg = Mips64ManagedRegister::FromVectorRegister(W29);
190 freg = Mips64ManagedRegister::FromFpuRegister(F29);
191 EXPECT_FALSE(reg.IsNoRegister());
192 EXPECT_FALSE(reg.IsGpuRegister());
193 EXPECT_FALSE(reg.IsFpuRegister());
194 EXPECT_TRUE(reg.IsVectorRegister());
195 EXPECT_TRUE(reg.Overlaps(freg));
196 EXPECT_EQ(W29, reg.AsVectorRegister());
197 EXPECT_EQ(F29, reg.AsOverlappingFpuRegister());
198 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromVectorRegister(W29)));
199 }
200
TEST(Mips64ManagedRegister,Equals)201 TEST(Mips64ManagedRegister, Equals) {
202 ManagedRegister no_reg = ManagedRegister::NoRegister();
203 EXPECT_TRUE(no_reg.Equals(Mips64ManagedRegister::NoRegister()));
204 EXPECT_FALSE(no_reg.Equals(Mips64ManagedRegister::FromGpuRegister(ZERO)));
205 EXPECT_FALSE(no_reg.Equals(Mips64ManagedRegister::FromGpuRegister(A1)));
206 EXPECT_FALSE(no_reg.Equals(Mips64ManagedRegister::FromGpuRegister(S2)));
207 EXPECT_FALSE(no_reg.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
208 EXPECT_FALSE(no_reg.Equals(Mips64ManagedRegister::FromVectorRegister(W0)));
209
210 Mips64ManagedRegister reg_ZERO = Mips64ManagedRegister::FromGpuRegister(ZERO);
211 EXPECT_FALSE(reg_ZERO.Equals(Mips64ManagedRegister::NoRegister()));
212 EXPECT_TRUE(reg_ZERO.Equals(Mips64ManagedRegister::FromGpuRegister(ZERO)));
213 EXPECT_FALSE(reg_ZERO.Equals(Mips64ManagedRegister::FromGpuRegister(A1)));
214 EXPECT_FALSE(reg_ZERO.Equals(Mips64ManagedRegister::FromGpuRegister(S2)));
215 EXPECT_FALSE(reg_ZERO.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
216 EXPECT_FALSE(reg_ZERO.Equals(Mips64ManagedRegister::FromVectorRegister(W0)));
217
218 Mips64ManagedRegister reg_A1 = Mips64ManagedRegister::FromGpuRegister(A1);
219 EXPECT_FALSE(reg_A1.Equals(Mips64ManagedRegister::NoRegister()));
220 EXPECT_FALSE(reg_A1.Equals(Mips64ManagedRegister::FromGpuRegister(ZERO)));
221 EXPECT_FALSE(reg_A1.Equals(Mips64ManagedRegister::FromGpuRegister(A0)));
222 EXPECT_TRUE(reg_A1.Equals(Mips64ManagedRegister::FromGpuRegister(A1)));
223 EXPECT_FALSE(reg_A1.Equals(Mips64ManagedRegister::FromGpuRegister(S2)));
224 EXPECT_FALSE(reg_A1.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
225 EXPECT_FALSE(reg_A1.Equals(Mips64ManagedRegister::FromVectorRegister(W0)));
226
227 Mips64ManagedRegister reg_S2 = Mips64ManagedRegister::FromGpuRegister(S2);
228 EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::NoRegister()));
229 EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::FromGpuRegister(ZERO)));
230 EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::FromGpuRegister(A1)));
231 EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::FromGpuRegister(S1)));
232 EXPECT_TRUE(reg_S2.Equals(Mips64ManagedRegister::FromGpuRegister(S2)));
233 EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
234 EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::FromVectorRegister(W0)));
235
236 Mips64ManagedRegister reg_F0 = Mips64ManagedRegister::FromFpuRegister(F0);
237 EXPECT_FALSE(reg_F0.Equals(Mips64ManagedRegister::NoRegister()));
238 EXPECT_FALSE(reg_F0.Equals(Mips64ManagedRegister::FromGpuRegister(ZERO)));
239 EXPECT_FALSE(reg_F0.Equals(Mips64ManagedRegister::FromGpuRegister(A1)));
240 EXPECT_FALSE(reg_F0.Equals(Mips64ManagedRegister::FromGpuRegister(S2)));
241 EXPECT_TRUE(reg_F0.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
242 EXPECT_FALSE(reg_F0.Equals(Mips64ManagedRegister::FromFpuRegister(F1)));
243 EXPECT_FALSE(reg_F0.Equals(Mips64ManagedRegister::FromFpuRegister(F31)));
244 EXPECT_FALSE(reg_F0.Equals(Mips64ManagedRegister::FromVectorRegister(W0)));
245
246 Mips64ManagedRegister reg_F31 = Mips64ManagedRegister::FromFpuRegister(F31);
247 EXPECT_FALSE(reg_F31.Equals(Mips64ManagedRegister::NoRegister()));
248 EXPECT_FALSE(reg_F31.Equals(Mips64ManagedRegister::FromGpuRegister(ZERO)));
249 EXPECT_FALSE(reg_F31.Equals(Mips64ManagedRegister::FromGpuRegister(A1)));
250 EXPECT_FALSE(reg_F31.Equals(Mips64ManagedRegister::FromGpuRegister(S2)));
251 EXPECT_FALSE(reg_F31.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
252 EXPECT_FALSE(reg_F31.Equals(Mips64ManagedRegister::FromFpuRegister(F1)));
253 EXPECT_TRUE(reg_F31.Equals(Mips64ManagedRegister::FromFpuRegister(F31)));
254 EXPECT_FALSE(reg_F31.Equals(Mips64ManagedRegister::FromVectorRegister(W0)));
255
256 Mips64ManagedRegister reg_W0 = Mips64ManagedRegister::FromVectorRegister(W0);
257 EXPECT_FALSE(reg_W0.Equals(Mips64ManagedRegister::NoRegister()));
258 EXPECT_FALSE(reg_W0.Equals(Mips64ManagedRegister::FromGpuRegister(ZERO)));
259 EXPECT_FALSE(reg_W0.Equals(Mips64ManagedRegister::FromGpuRegister(A1)));
260 EXPECT_FALSE(reg_W0.Equals(Mips64ManagedRegister::FromGpuRegister(S1)));
261 EXPECT_FALSE(reg_W0.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
262 EXPECT_TRUE(reg_W0.Equals(Mips64ManagedRegister::FromVectorRegister(W0)));
263 EXPECT_FALSE(reg_W0.Equals(Mips64ManagedRegister::FromVectorRegister(W1)));
264 EXPECT_FALSE(reg_W0.Equals(Mips64ManagedRegister::FromVectorRegister(W31)));
265
266 Mips64ManagedRegister reg_W31 = Mips64ManagedRegister::FromVectorRegister(W31);
267 EXPECT_FALSE(reg_W31.Equals(Mips64ManagedRegister::NoRegister()));
268 EXPECT_FALSE(reg_W31.Equals(Mips64ManagedRegister::FromGpuRegister(ZERO)));
269 EXPECT_FALSE(reg_W31.Equals(Mips64ManagedRegister::FromGpuRegister(A1)));
270 EXPECT_FALSE(reg_W31.Equals(Mips64ManagedRegister::FromGpuRegister(S1)));
271 EXPECT_FALSE(reg_W31.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
272 EXPECT_FALSE(reg_W31.Equals(Mips64ManagedRegister::FromVectorRegister(W0)));
273 EXPECT_FALSE(reg_W31.Equals(Mips64ManagedRegister::FromVectorRegister(W1)));
274 EXPECT_TRUE(reg_W31.Equals(Mips64ManagedRegister::FromVectorRegister(W31)));
275 }
276
TEST(Mips64ManagedRegister,Overlaps)277 TEST(Mips64ManagedRegister, Overlaps) {
278 Mips64ManagedRegister reg = Mips64ManagedRegister::FromFpuRegister(F0);
279 Mips64ManagedRegister reg_o = Mips64ManagedRegister::FromVectorRegister(W0);
280 EXPECT_TRUE(reg.Overlaps(reg_o));
281 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
282 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
283 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
284 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
285 EXPECT_EQ(F0, reg_o.AsOverlappingFpuRegister());
286 EXPECT_EQ(W0, reg.AsOverlappingVectorRegister());
287 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
288 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
289 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
290 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
291 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
292 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
293 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
294 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
295
296 reg = Mips64ManagedRegister::FromFpuRegister(F4);
297 reg_o = Mips64ManagedRegister::FromVectorRegister(W4);
298 EXPECT_TRUE(reg.Overlaps(reg_o));
299 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
300 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
301 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
302 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
303 EXPECT_EQ(F4, reg_o.AsOverlappingFpuRegister());
304 EXPECT_EQ(W4, reg.AsOverlappingVectorRegister());
305 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
306 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
307 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
308 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
309 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
310 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
311 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
312 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
313
314 reg = Mips64ManagedRegister::FromFpuRegister(F16);
315 reg_o = Mips64ManagedRegister::FromVectorRegister(W16);
316 EXPECT_TRUE(reg.Overlaps(reg_o));
317 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
318 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
319 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
320 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
321 EXPECT_EQ(F16, reg_o.AsOverlappingFpuRegister());
322 EXPECT_EQ(W16, reg.AsOverlappingVectorRegister());
323 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
324 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
325 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
326 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
327 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
328 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
329 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
330 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
331
332 reg = Mips64ManagedRegister::FromFpuRegister(F31);
333 reg_o = Mips64ManagedRegister::FromVectorRegister(W31);
334 EXPECT_TRUE(reg.Overlaps(reg_o));
335 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
336 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
337 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
338 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
339 EXPECT_EQ(F31, reg_o.AsOverlappingFpuRegister());
340 EXPECT_EQ(W31, reg.AsOverlappingVectorRegister());
341 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
342 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
343 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
344 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
345 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
346 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
347 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
348 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
349
350 reg = Mips64ManagedRegister::FromVectorRegister(W0);
351 reg_o = Mips64ManagedRegister::FromFpuRegister(F0);
352 EXPECT_TRUE(reg.Overlaps(reg_o));
353 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
354 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
355 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
356 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
357 EXPECT_EQ(W0, reg_o.AsOverlappingVectorRegister());
358 EXPECT_EQ(F0, reg.AsOverlappingFpuRegister());
359 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
360 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
361 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
362 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
363 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
364 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
365 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
366 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
367
368 reg = Mips64ManagedRegister::FromVectorRegister(W4);
369 reg_o = Mips64ManagedRegister::FromFpuRegister(F4);
370 EXPECT_TRUE(reg.Overlaps(reg_o));
371 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
372 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
373 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
374 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
375 EXPECT_EQ(W4, reg_o.AsOverlappingVectorRegister());
376 EXPECT_EQ(F4, reg.AsOverlappingFpuRegister());
377 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
378 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
379 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
380 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
381 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
382 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
383 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
384 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
385
386 reg = Mips64ManagedRegister::FromVectorRegister(W16);
387 reg_o = Mips64ManagedRegister::FromFpuRegister(F16);
388 EXPECT_TRUE(reg.Overlaps(reg_o));
389 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
390 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
391 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
392 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
393 EXPECT_EQ(W16, reg_o.AsOverlappingVectorRegister());
394 EXPECT_EQ(F16, reg.AsOverlappingFpuRegister());
395 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
396 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
397 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
398 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
399 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
400 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
401 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
402 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
403
404 reg = Mips64ManagedRegister::FromVectorRegister(W31);
405 reg_o = Mips64ManagedRegister::FromFpuRegister(F31);
406 EXPECT_TRUE(reg.Overlaps(reg_o));
407 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
408 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
409 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
410 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
411 EXPECT_EQ(W31, reg_o.AsOverlappingVectorRegister());
412 EXPECT_EQ(F31, reg.AsOverlappingFpuRegister());
413 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
414 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
415 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
416 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
417 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
418 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
419 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
420 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
421
422 reg = Mips64ManagedRegister::FromGpuRegister(ZERO);
423 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
424 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
425 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
426 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
427 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
428 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
429 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
430 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
431 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
432 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
433 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
434 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
435
436 reg = Mips64ManagedRegister::FromGpuRegister(A0);
437 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
438 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
439 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
440 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
441 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
442 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
443 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
444 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
445 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
446 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
447 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
448 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
449
450 reg = Mips64ManagedRegister::FromGpuRegister(S0);
451 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
452 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
453 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
454 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
455 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
456 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
457 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
458 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
459 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
460 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
461 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
462 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
463
464 reg = Mips64ManagedRegister::FromGpuRegister(RA);
465 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO)));
466 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0)));
467 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0)));
468 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA)));
469 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0)));
470 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4)));
471 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16)));
472 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31)));
473 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0)));
474 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4)));
475 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
476 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31)));
477 }
478
479 } // namespace mips64
480 } // namespace art
481