1%default {"extract":"asr     r1, r3, #8", "result":"r0", "chkzero":"0"}
2    /*
3     * Generic 32-bit "lit8" binary operation.  Provide an "instr" line
4     * that specifies an instruction that performs "result = r0 op r1".
5     * This could be an ARM instruction or a function call.  (If the result
6     * comes back in a register other than r0, you can override "result".)
7     *
8     * You can override "extract" if the extraction of the literal value
9     * from r3 to r1 is not the default "asr r1, r3, #8". The extraction
10     * can be omitted completely if the shift is embedded in "instr".
11     *
12     * If "chkzero" is set to 1, we perform a divide-by-zero check on
13     * vCC (r1).  Useful for integer division and modulus.
14     *
15     * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
16     *      rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
17     *      shl-int/lit8, shr-int/lit8, ushr-int/lit8
18     */
19    /* binop/lit8 vAA, vBB, #+CC */
20    FETCH_S r3, 1                       @ r3<- ssssCCBB (sign-extended for CC)
21    mov     r9, rINST, lsr #8           @ r9<- AA
22    and     r2, r3, #255                @ r2<- BB
23    GET_VREG r0, r2                     @ r0<- vBB
24    $extract                            @ optional; typically r1<- ssssssCC (sign extended)
25    .if $chkzero
26    @cmp     r1, #0                     @ is second operand zero?
27    beq     common_errDivideByZero
28    .endif
29    FETCH_ADVANCE_INST 2                @ advance rPC, load rINST
30
31    $instr                              @ $result<- op, r0-r3 changed
32    GET_INST_OPCODE ip                  @ extract opcode from rINST
33    SET_VREG $result, r9                @ vAA<- $result
34    GOTO_OPCODE ip                      @ jump to next instruction
35    /* 10-12 instructions */
36