1%default {}
2    /*
3     * Specialized 32-bit binary operation
4     *
5     * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper
6     * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for
7     * ARMv7 CPUs that have hardware division support).
8     *
9     * div-int
10     *
11     */
12    FETCH r0, 1                         @ r0<- CCBB
13    mov     r9, rINST, lsr #8           @ r9<- AA
14    mov     r3, r0, lsr #8              @ r3<- CC
15    and     r2, r0, #255                @ r2<- BB
16    GET_VREG r1, r3                     @ r1<- vCC
17    GET_VREG r0, r2                     @ r0<- vBB
18    cmp     r1, #0                      @ is second operand zero?
19    beq     common_errDivideByZero
20
21    FETCH_ADVANCE_INST 2                @ advance rPC, load rINST
22#ifdef __ARM_ARCH_EXT_IDIV__
23    sdiv    r0, r0, r1                  @ r0<- op
24#else
25    bl    __aeabi_idiv                  @ r0<- op, r0-r3 changed
26#endif
27    GET_INST_OPCODE ip                  @ extract opcode from rINST
28    SET_VREG r0, r9                     @ vAA<- r0
29    GOTO_OPCODE ip                      @ jump to next instruction
30    /* 11-14 instructions */
31