1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|*Target Register Enum Values                                                 *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9/* Capstone Disassembly Engine, http://www.capstone-engine.org */
10/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
11
12
13#ifdef GET_REGINFO_ENUM
14#undef GET_REGINFO_ENUM
15
16enum {
17  Mips_NoRegister,
18  Mips_AT = 1,
19  Mips_DSPCCond = 2,
20  Mips_DSPCarry = 3,
21  Mips_DSPEFI = 4,
22  Mips_DSPOutFlag = 5,
23  Mips_DSPPos = 6,
24  Mips_DSPSCount = 7,
25  Mips_FP = 8,
26  Mips_GP = 9,
27  Mips_MSAAccess = 10,
28  Mips_MSACSR = 11,
29  Mips_MSAIR = 12,
30  Mips_MSAMap = 13,
31  Mips_MSAModify = 14,
32  Mips_MSARequest = 15,
33  Mips_MSASave = 16,
34  Mips_MSAUnmap = 17,
35  Mips_PC = 18,
36  Mips_RA = 19,
37  Mips_SP = 20,
38  Mips_ZERO = 21,
39  Mips_A0 = 22,
40  Mips_A1 = 23,
41  Mips_A2 = 24,
42  Mips_A3 = 25,
43  Mips_AC0 = 26,
44  Mips_AC1 = 27,
45  Mips_AC2 = 28,
46  Mips_AC3 = 29,
47  Mips_AT_64 = 30,
48  Mips_CC0 = 31,
49  Mips_CC1 = 32,
50  Mips_CC2 = 33,
51  Mips_CC3 = 34,
52  Mips_CC4 = 35,
53  Mips_CC5 = 36,
54  Mips_CC6 = 37,
55  Mips_CC7 = 38,
56  Mips_COP20 = 39,
57  Mips_COP21 = 40,
58  Mips_COP22 = 41,
59  Mips_COP23 = 42,
60  Mips_COP24 = 43,
61  Mips_COP25 = 44,
62  Mips_COP26 = 45,
63  Mips_COP27 = 46,
64  Mips_COP28 = 47,
65  Mips_COP29 = 48,
66  Mips_COP30 = 49,
67  Mips_COP31 = 50,
68  Mips_COP32 = 51,
69  Mips_COP33 = 52,
70  Mips_COP34 = 53,
71  Mips_COP35 = 54,
72  Mips_COP36 = 55,
73  Mips_COP37 = 56,
74  Mips_COP38 = 57,
75  Mips_COP39 = 58,
76  Mips_COP210 = 59,
77  Mips_COP211 = 60,
78  Mips_COP212 = 61,
79  Mips_COP213 = 62,
80  Mips_COP214 = 63,
81  Mips_COP215 = 64,
82  Mips_COP216 = 65,
83  Mips_COP217 = 66,
84  Mips_COP218 = 67,
85  Mips_COP219 = 68,
86  Mips_COP220 = 69,
87  Mips_COP221 = 70,
88  Mips_COP222 = 71,
89  Mips_COP223 = 72,
90  Mips_COP224 = 73,
91  Mips_COP225 = 74,
92  Mips_COP226 = 75,
93  Mips_COP227 = 76,
94  Mips_COP228 = 77,
95  Mips_COP229 = 78,
96  Mips_COP230 = 79,
97  Mips_COP231 = 80,
98  Mips_COP310 = 81,
99  Mips_COP311 = 82,
100  Mips_COP312 = 83,
101  Mips_COP313 = 84,
102  Mips_COP314 = 85,
103  Mips_COP315 = 86,
104  Mips_COP316 = 87,
105  Mips_COP317 = 88,
106  Mips_COP318 = 89,
107  Mips_COP319 = 90,
108  Mips_COP320 = 91,
109  Mips_COP321 = 92,
110  Mips_COP322 = 93,
111  Mips_COP323 = 94,
112  Mips_COP324 = 95,
113  Mips_COP325 = 96,
114  Mips_COP326 = 97,
115  Mips_COP327 = 98,
116  Mips_COP328 = 99,
117  Mips_COP329 = 100,
118  Mips_COP330 = 101,
119  Mips_COP331 = 102,
120  Mips_D0 = 103,
121  Mips_D1 = 104,
122  Mips_D2 = 105,
123  Mips_D3 = 106,
124  Mips_D4 = 107,
125  Mips_D5 = 108,
126  Mips_D6 = 109,
127  Mips_D7 = 110,
128  Mips_D8 = 111,
129  Mips_D9 = 112,
130  Mips_D10 = 113,
131  Mips_D11 = 114,
132  Mips_D12 = 115,
133  Mips_D13 = 116,
134  Mips_D14 = 117,
135  Mips_D15 = 118,
136  Mips_DSPOutFlag20 = 119,
137  Mips_DSPOutFlag21 = 120,
138  Mips_DSPOutFlag22 = 121,
139  Mips_DSPOutFlag23 = 122,
140  Mips_F0 = 123,
141  Mips_F1 = 124,
142  Mips_F2 = 125,
143  Mips_F3 = 126,
144  Mips_F4 = 127,
145  Mips_F5 = 128,
146  Mips_F6 = 129,
147  Mips_F7 = 130,
148  Mips_F8 = 131,
149  Mips_F9 = 132,
150  Mips_F10 = 133,
151  Mips_F11 = 134,
152  Mips_F12 = 135,
153  Mips_F13 = 136,
154  Mips_F14 = 137,
155  Mips_F15 = 138,
156  Mips_F16 = 139,
157  Mips_F17 = 140,
158  Mips_F18 = 141,
159  Mips_F19 = 142,
160  Mips_F20 = 143,
161  Mips_F21 = 144,
162  Mips_F22 = 145,
163  Mips_F23 = 146,
164  Mips_F24 = 147,
165  Mips_F25 = 148,
166  Mips_F26 = 149,
167  Mips_F27 = 150,
168  Mips_F28 = 151,
169  Mips_F29 = 152,
170  Mips_F30 = 153,
171  Mips_F31 = 154,
172  Mips_FCC0 = 155,
173  Mips_FCC1 = 156,
174  Mips_FCC2 = 157,
175  Mips_FCC3 = 158,
176  Mips_FCC4 = 159,
177  Mips_FCC5 = 160,
178  Mips_FCC6 = 161,
179  Mips_FCC7 = 162,
180  Mips_FCR0 = 163,
181  Mips_FCR1 = 164,
182  Mips_FCR2 = 165,
183  Mips_FCR3 = 166,
184  Mips_FCR4 = 167,
185  Mips_FCR5 = 168,
186  Mips_FCR6 = 169,
187  Mips_FCR7 = 170,
188  Mips_FCR8 = 171,
189  Mips_FCR9 = 172,
190  Mips_FCR10 = 173,
191  Mips_FCR11 = 174,
192  Mips_FCR12 = 175,
193  Mips_FCR13 = 176,
194  Mips_FCR14 = 177,
195  Mips_FCR15 = 178,
196  Mips_FCR16 = 179,
197  Mips_FCR17 = 180,
198  Mips_FCR18 = 181,
199  Mips_FCR19 = 182,
200  Mips_FCR20 = 183,
201  Mips_FCR21 = 184,
202  Mips_FCR22 = 185,
203  Mips_FCR23 = 186,
204  Mips_FCR24 = 187,
205  Mips_FCR25 = 188,
206  Mips_FCR26 = 189,
207  Mips_FCR27 = 190,
208  Mips_FCR28 = 191,
209  Mips_FCR29 = 192,
210  Mips_FCR30 = 193,
211  Mips_FCR31 = 194,
212  Mips_FP_64 = 195,
213  Mips_F_HI0 = 196,
214  Mips_F_HI1 = 197,
215  Mips_F_HI2 = 198,
216  Mips_F_HI3 = 199,
217  Mips_F_HI4 = 200,
218  Mips_F_HI5 = 201,
219  Mips_F_HI6 = 202,
220  Mips_F_HI7 = 203,
221  Mips_F_HI8 = 204,
222  Mips_F_HI9 = 205,
223  Mips_F_HI10 = 206,
224  Mips_F_HI11 = 207,
225  Mips_F_HI12 = 208,
226  Mips_F_HI13 = 209,
227  Mips_F_HI14 = 210,
228  Mips_F_HI15 = 211,
229  Mips_F_HI16 = 212,
230  Mips_F_HI17 = 213,
231  Mips_F_HI18 = 214,
232  Mips_F_HI19 = 215,
233  Mips_F_HI20 = 216,
234  Mips_F_HI21 = 217,
235  Mips_F_HI22 = 218,
236  Mips_F_HI23 = 219,
237  Mips_F_HI24 = 220,
238  Mips_F_HI25 = 221,
239  Mips_F_HI26 = 222,
240  Mips_F_HI27 = 223,
241  Mips_F_HI28 = 224,
242  Mips_F_HI29 = 225,
243  Mips_F_HI30 = 226,
244  Mips_F_HI31 = 227,
245  Mips_GP_64 = 228,
246  Mips_HI0 = 229,
247  Mips_HI1 = 230,
248  Mips_HI2 = 231,
249  Mips_HI3 = 232,
250  Mips_HWR0 = 233,
251  Mips_HWR1 = 234,
252  Mips_HWR2 = 235,
253  Mips_HWR3 = 236,
254  Mips_HWR4 = 237,
255  Mips_HWR5 = 238,
256  Mips_HWR6 = 239,
257  Mips_HWR7 = 240,
258  Mips_HWR8 = 241,
259  Mips_HWR9 = 242,
260  Mips_HWR10 = 243,
261  Mips_HWR11 = 244,
262  Mips_HWR12 = 245,
263  Mips_HWR13 = 246,
264  Mips_HWR14 = 247,
265  Mips_HWR15 = 248,
266  Mips_HWR16 = 249,
267  Mips_HWR17 = 250,
268  Mips_HWR18 = 251,
269  Mips_HWR19 = 252,
270  Mips_HWR20 = 253,
271  Mips_HWR21 = 254,
272  Mips_HWR22 = 255,
273  Mips_HWR23 = 256,
274  Mips_HWR24 = 257,
275  Mips_HWR25 = 258,
276  Mips_HWR26 = 259,
277  Mips_HWR27 = 260,
278  Mips_HWR28 = 261,
279  Mips_HWR29 = 262,
280  Mips_HWR30 = 263,
281  Mips_HWR31 = 264,
282  Mips_K0 = 265,
283  Mips_K1 = 266,
284  Mips_LO0 = 267,
285  Mips_LO1 = 268,
286  Mips_LO2 = 269,
287  Mips_LO3 = 270,
288  Mips_MPL0 = 271,
289  Mips_MPL1 = 272,
290  Mips_MPL2 = 273,
291  Mips_P0 = 274,
292  Mips_P1 = 275,
293  Mips_P2 = 276,
294  Mips_RA_64 = 277,
295  Mips_S0 = 278,
296  Mips_S1 = 279,
297  Mips_S2 = 280,
298  Mips_S3 = 281,
299  Mips_S4 = 282,
300  Mips_S5 = 283,
301  Mips_S6 = 284,
302  Mips_S7 = 285,
303  Mips_SP_64 = 286,
304  Mips_T0 = 287,
305  Mips_T1 = 288,
306  Mips_T2 = 289,
307  Mips_T3 = 290,
308  Mips_T4 = 291,
309  Mips_T5 = 292,
310  Mips_T6 = 293,
311  Mips_T7 = 294,
312  Mips_T8 = 295,
313  Mips_T9 = 296,
314  Mips_V0 = 297,
315  Mips_V1 = 298,
316  Mips_W0 = 299,
317  Mips_W1 = 300,
318  Mips_W2 = 301,
319  Mips_W3 = 302,
320  Mips_W4 = 303,
321  Mips_W5 = 304,
322  Mips_W6 = 305,
323  Mips_W7 = 306,
324  Mips_W8 = 307,
325  Mips_W9 = 308,
326  Mips_W10 = 309,
327  Mips_W11 = 310,
328  Mips_W12 = 311,
329  Mips_W13 = 312,
330  Mips_W14 = 313,
331  Mips_W15 = 314,
332  Mips_W16 = 315,
333  Mips_W17 = 316,
334  Mips_W18 = 317,
335  Mips_W19 = 318,
336  Mips_W20 = 319,
337  Mips_W21 = 320,
338  Mips_W22 = 321,
339  Mips_W23 = 322,
340  Mips_W24 = 323,
341  Mips_W25 = 324,
342  Mips_W26 = 325,
343  Mips_W27 = 326,
344  Mips_W28 = 327,
345  Mips_W29 = 328,
346  Mips_W30 = 329,
347  Mips_W31 = 330,
348  Mips_ZERO_64 = 331,
349  Mips_A0_64 = 332,
350  Mips_A1_64 = 333,
351  Mips_A2_64 = 334,
352  Mips_A3_64 = 335,
353  Mips_AC0_64 = 336,
354  Mips_D0_64 = 337,
355  Mips_D1_64 = 338,
356  Mips_D2_64 = 339,
357  Mips_D3_64 = 340,
358  Mips_D4_64 = 341,
359  Mips_D5_64 = 342,
360  Mips_D6_64 = 343,
361  Mips_D7_64 = 344,
362  Mips_D8_64 = 345,
363  Mips_D9_64 = 346,
364  Mips_D10_64 = 347,
365  Mips_D11_64 = 348,
366  Mips_D12_64 = 349,
367  Mips_D13_64 = 350,
368  Mips_D14_64 = 351,
369  Mips_D15_64 = 352,
370  Mips_D16_64 = 353,
371  Mips_D17_64 = 354,
372  Mips_D18_64 = 355,
373  Mips_D19_64 = 356,
374  Mips_D20_64 = 357,
375  Mips_D21_64 = 358,
376  Mips_D22_64 = 359,
377  Mips_D23_64 = 360,
378  Mips_D24_64 = 361,
379  Mips_D25_64 = 362,
380  Mips_D26_64 = 363,
381  Mips_D27_64 = 364,
382  Mips_D28_64 = 365,
383  Mips_D29_64 = 366,
384  Mips_D30_64 = 367,
385  Mips_D31_64 = 368,
386  Mips_DSPOutFlag16_19 = 369,
387  Mips_HI0_64 = 370,
388  Mips_K0_64 = 371,
389  Mips_K1_64 = 372,
390  Mips_LO0_64 = 373,
391  Mips_S0_64 = 374,
392  Mips_S1_64 = 375,
393  Mips_S2_64 = 376,
394  Mips_S3_64 = 377,
395  Mips_S4_64 = 378,
396  Mips_S5_64 = 379,
397  Mips_S6_64 = 380,
398  Mips_S7_64 = 381,
399  Mips_T0_64 = 382,
400  Mips_T1_64 = 383,
401  Mips_T2_64 = 384,
402  Mips_T3_64 = 385,
403  Mips_T4_64 = 386,
404  Mips_T5_64 = 387,
405  Mips_T6_64 = 388,
406  Mips_T7_64 = 389,
407  Mips_T8_64 = 390,
408  Mips_T9_64 = 391,
409  Mips_V0_64 = 392,
410  Mips_V1_64 = 393,
411  Mips_NUM_TARGET_REGS 	// 394
412};
413
414// Register classes
415enum {
416  Mips_OddSPRegClassID = 0,
417  Mips_CCRRegClassID = 1,
418  Mips_COP2RegClassID = 2,
419  Mips_COP3RegClassID = 3,
420  Mips_DSPRRegClassID = 4,
421  Mips_FGR32RegClassID = 5,
422  Mips_FGRCCRegClassID = 6,
423  Mips_FGRH32RegClassID = 7,
424  Mips_GPR32RegClassID = 8,
425  Mips_HWRegsRegClassID = 9,
426  Mips_OddSP_with_sub_hiRegClassID = 10,
427  Mips_FGR32_and_OddSPRegClassID = 11,
428  Mips_FGRH32_and_OddSPRegClassID = 12,
429  Mips_OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID = 13,
430  Mips_CPU16RegsPlusSPRegClassID = 14,
431  Mips_CCRegClassID = 15,
432  Mips_CPU16RegsRegClassID = 16,
433  Mips_FCCRegClassID = 17,
434  Mips_MSACtrlRegClassID = 18,
435  Mips_OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID = 19,
436  Mips_HI32DSPRegClassID = 20,
437  Mips_LO32DSPRegClassID = 21,
438  Mips_CPURARegRegClassID = 22,
439  Mips_CPUSPRegRegClassID = 23,
440  Mips_DSPCCRegClassID = 24,
441  Mips_HI32RegClassID = 25,
442  Mips_LO32RegClassID = 26,
443  Mips_FGR64RegClassID = 27,
444  Mips_GPR64RegClassID = 28,
445  Mips_AFGR64RegClassID = 29,
446  Mips_FGR64_and_OddSPRegClassID = 30,
447  Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 31,
448  Mips_AFGR64_and_OddSPRegClassID = 32,
449  Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID = 33,
450  Mips_ACC64DSPRegClassID = 34,
451  Mips_OCTEON_MPLRegClassID = 35,
452  Mips_OCTEON_PRegClassID = 36,
453  Mips_ACC64RegClassID = 37,
454  Mips_GPR64_with_sub_32_in_CPURARegRegClassID = 38,
455  Mips_GPR64_with_sub_32_in_CPUSPRegRegClassID = 39,
456  Mips_HI64RegClassID = 40,
457  Mips_LO64RegClassID = 41,
458  Mips_MSA128BRegClassID = 42,
459  Mips_MSA128DRegClassID = 43,
460  Mips_MSA128HRegClassID = 44,
461  Mips_MSA128WRegClassID = 45,
462  Mips_MSA128B_with_sub_64_in_OddSPRegClassID = 46,
463  Mips_ACC128RegClassID = 47
464};
465
466// Subregister indices
467enum {
468  Mips_NoSubRegister,
469  Mips_sub_32,	// 1
470  Mips_sub_64,	// 2
471  Mips_sub_dsp16_19,	// 3
472  Mips_sub_dsp20,	// 4
473  Mips_sub_dsp21,	// 5
474  Mips_sub_dsp22,	// 6
475  Mips_sub_dsp23,	// 7
476  Mips_sub_hi,	// 8
477  Mips_sub_lo,	// 9
478  Mips_sub_hi_then_sub_32,	// 10
479  Mips_sub_32_sub_hi_then_sub_32,	// 11
480  Mips_NUM_TARGET_SUBREGS
481};
482
483#endif // GET_REGINFO_ENUM
484
485/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
486|*                                                                            *|
487|*MC Register Information                                                     *|
488|*                                                                            *|
489|* Automatically generated file, do not edit!                                 *|
490|*                                                                            *|
491\*===----------------------------------------------------------------------===*/
492
493/* Capstone Disassembly Engine, http://www.capstone-engine.org */
494/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
495
496
497#ifdef GET_REGINFO_MC_DESC
498#undef GET_REGINFO_MC_DESC
499
500static MCPhysReg MipsRegDiffLists[] = {
501  /* 0 */ 0, 0,
502  /* 2 */ 4, 1, 1, 1, 1, 0,
503  /* 8 */ 364, 65286, 1, 1, 1, 0,
504  /* 14 */ 20, 1, 0,
505  /* 17 */ 21, 1, 0,
506  /* 20 */ 22, 1, 0,
507  /* 23 */ 23, 1, 0,
508  /* 26 */ 24, 1, 0,
509  /* 29 */ 25, 1, 0,
510  /* 32 */ 26, 1, 0,
511  /* 35 */ 27, 1, 0,
512  /* 38 */ 28, 1, 0,
513  /* 41 */ 29, 1, 0,
514  /* 44 */ 30, 1, 0,
515  /* 47 */ 31, 1, 0,
516  /* 50 */ 32, 1, 0,
517  /* 53 */ 33, 1, 0,
518  /* 56 */ 34, 1, 0,
519  /* 59 */ 35, 1, 0,
520  /* 62 */ 65439, 1, 0,
521  /* 65 */ 65513, 1, 0,
522  /* 68 */ 3, 0,
523  /* 70 */ 4, 0,
524  /* 72 */ 6, 0,
525  /* 74 */ 11, 0,
526  /* 76 */ 12, 0,
527  /* 78 */ 22, 0,
528  /* 80 */ 23, 0,
529  /* 82 */ 29, 0,
530  /* 84 */ 30, 0,
531  /* 86 */ 65308, 72, 0,
532  /* 89 */ 65346, 72, 0,
533  /* 92 */ 38, 65322, 73, 0,
534  /* 96 */ 95, 0,
535  /* 98 */ 96, 0,
536  /* 100 */ 106, 0,
537  /* 102 */ 187, 0,
538  /* 104 */ 219, 0,
539  /* 106 */ 258, 0,
540  /* 108 */ 266, 0,
541  /* 110 */ 310, 0,
542  /* 112 */ 65031, 0,
543  /* 114 */ 65108, 0,
544  /* 116 */ 65172, 0,
545  /* 118 */ 65226, 0,
546  /* 120 */ 65229, 0,
547  /* 122 */ 65270, 0,
548  /* 124 */ 65278, 0,
549  /* 126 */ 65295, 0,
550  /* 128 */ 65317, 0,
551  /* 130 */ 37, 65430, 103, 65395, 65333, 0,
552  /* 136 */ 65349, 0,
553  /* 138 */ 65395, 0,
554  /* 140 */ 65410, 0,
555  /* 142 */ 65415, 0,
556  /* 144 */ 65419, 0,
557  /* 146 */ 65420, 0,
558  /* 148 */ 65421, 0,
559  /* 150 */ 65422, 0,
560  /* 152 */ 65430, 0,
561  /* 154 */ 65440, 0,
562  /* 156 */ 65441, 0,
563  /* 158 */ 141, 65498, 0,
564  /* 161 */ 65516, 234, 65498, 0,
565  /* 165 */ 65515, 235, 65498, 0,
566  /* 169 */ 65514, 236, 65498, 0,
567  /* 173 */ 65513, 237, 65498, 0,
568  /* 177 */ 65512, 238, 65498, 0,
569  /* 181 */ 65511, 239, 65498, 0,
570  /* 185 */ 65510, 240, 65498, 0,
571  /* 189 */ 65509, 241, 65498, 0,
572  /* 193 */ 65508, 242, 65498, 0,
573  /* 197 */ 65507, 243, 65498, 0,
574  /* 201 */ 65506, 244, 65498, 0,
575  /* 205 */ 65505, 245, 65498, 0,
576  /* 209 */ 65504, 246, 65498, 0,
577  /* 213 */ 65503, 247, 65498, 0,
578  /* 217 */ 65502, 248, 65498, 0,
579  /* 221 */ 65501, 249, 65498, 0,
580  /* 225 */ 65500, 250, 65498, 0,
581  /* 229 */ 65295, 347, 65499, 0,
582  /* 233 */ 65333, 344, 65502, 0,
583  /* 237 */ 65507, 0,
584  /* 239 */ 65510, 0,
585  /* 241 */ 65511, 0,
586  /* 243 */ 65512, 0,
587  /* 245 */ 65516, 0,
588  /* 247 */ 65521, 0,
589  /* 249 */ 65522, 0,
590  /* 251 */ 65535, 0,
591};
592
593static uint16_t MipsSubRegIdxLists[] = {
594  /* 0 */ 1, 0,
595  /* 2 */ 3, 4, 5, 6, 7, 0,
596  /* 8 */ 2, 9, 8, 0,
597  /* 12 */ 9, 1, 8, 10, 11, 0,
598};
599
600static MCRegisterDesc MipsRegDesc[] = { // Descriptors
601  { 6, 0, 0, 0, 0 },
602  { 2007, 1, 82, 1, 4017 },
603  { 2010, 1, 1, 1, 4017 },
604  { 2102, 1, 1, 1, 4017 },
605  { 1973, 1, 1, 1, 4017 },
606  { 2027, 8, 1, 2, 32 },
607  { 2054, 1, 1, 1, 1089 },
608  { 2071, 1, 1, 1, 1089 },
609  { 1985, 1, 102, 1, 1089 },
610  { 1988, 1, 104, 1, 1089 },
611  { 2061, 1, 1, 1, 1089 },
612  { 2000, 1, 1, 1, 1089 },
613  { 1994, 1, 1, 1, 1089 },
614  { 2038, 1, 1, 1, 1089 },
615  { 2092, 1, 1, 1, 1089 },
616  { 2081, 1, 1, 1, 1089 },
617  { 2019, 1, 1, 1, 1089 },
618  { 2045, 1, 1, 1, 1089 },
619  { 1970, 1, 1, 1, 1089 },
620  { 1967, 1, 106, 1, 1089 },
621  { 1991, 1, 108, 1, 1089 },
622  { 1980, 1, 110, 1, 1089 },
623  { 152, 1, 110, 1, 1089 },
624  { 365, 1, 110, 1, 1089 },
625  { 537, 1, 110, 1, 1089 },
626  { 703, 1, 110, 1, 1089 },
627  { 155, 190, 110, 9, 1042 },
628  { 368, 190, 1, 9, 1042 },
629  { 540, 190, 1, 9, 1042 },
630  { 706, 190, 1, 9, 1042 },
631  { 1271, 237, 1, 0, 0 },
632  { 160, 1, 1, 1, 1153 },
633  { 373, 1, 1, 1, 1153 },
634  { 545, 1, 1, 1, 1153 },
635  { 711, 1, 1, 1, 1153 },
636  { 1278, 1, 1, 1, 1153 },
637  { 1412, 1, 1, 1, 1153 },
638  { 1542, 1, 1, 1, 1153 },
639  { 1672, 1, 1, 1, 1153 },
640  { 70, 1, 1, 1, 1153 },
641  { 283, 1, 1, 1, 1153 },
642  { 496, 1, 1, 1, 1153 },
643  { 662, 1, 1, 1, 1153 },
644  { 820, 1, 1, 1, 1153 },
645  { 1383, 1, 1, 1, 1153 },
646  { 1513, 1, 1, 1, 1153 },
647  { 1643, 1, 1, 1, 1153 },
648  { 1773, 1, 1, 1, 1153 },
649  { 1911, 1, 1, 1, 1153 },
650  { 130, 1, 1, 1, 1153 },
651  { 343, 1, 1, 1, 1153 },
652  { 531, 1, 1, 1, 1153 },
653  { 697, 1, 1, 1, 1153 },
654  { 842, 1, 1, 1, 1153 },
655  { 1405, 1, 1, 1, 1153 },
656  { 1535, 1, 1, 1, 1153 },
657  { 1665, 1, 1, 1, 1153 },
658  { 1795, 1, 1, 1, 1153 },
659  { 1933, 1, 1, 1, 1153 },
660  { 0, 1, 1, 1, 1153 },
661  { 213, 1, 1, 1, 1153 },
662  { 426, 1, 1, 1, 1153 },
663  { 592, 1, 1, 1, 1153 },
664  { 750, 1, 1, 1, 1153 },
665  { 1313, 1, 1, 1, 1153 },
666  { 1447, 1, 1, 1, 1153 },
667  { 1577, 1, 1, 1, 1153 },
668  { 1707, 1, 1, 1, 1153 },
669  { 1829, 1, 1, 1, 1153 },
670  { 45, 1, 1, 1, 1153 },
671  { 258, 1, 1, 1, 1153 },
672  { 471, 1, 1, 1, 1153 },
673  { 637, 1, 1, 1, 1153 },
674  { 795, 1, 1, 1, 1153 },
675  { 1358, 1, 1, 1, 1153 },
676  { 1488, 1, 1, 1, 1153 },
677  { 1618, 1, 1, 1, 1153 },
678  { 1748, 1, 1, 1, 1153 },
679  { 1886, 1, 1, 1, 1153 },
680  { 105, 1, 1, 1, 1153 },
681  { 318, 1, 1, 1, 1153 },
682  { 7, 1, 1, 1, 1153 },
683  { 220, 1, 1, 1, 1153 },
684  { 433, 1, 1, 1, 1153 },
685  { 599, 1, 1, 1, 1153 },
686  { 757, 1, 1, 1, 1153 },
687  { 1320, 1, 1, 1, 1153 },
688  { 1454, 1, 1, 1, 1153 },
689  { 1584, 1, 1, 1, 1153 },
690  { 1714, 1, 1, 1, 1153 },
691  { 1836, 1, 1, 1, 1153 },
692  { 52, 1, 1, 1, 1153 },
693  { 265, 1, 1, 1, 1153 },
694  { 478, 1, 1, 1, 1153 },
695  { 644, 1, 1, 1, 1153 },
696  { 802, 1, 1, 1, 1153 },
697  { 1365, 1, 1, 1, 1153 },
698  { 1495, 1, 1, 1, 1153 },
699  { 1625, 1, 1, 1, 1153 },
700  { 1755, 1, 1, 1, 1153 },
701  { 1893, 1, 1, 1, 1153 },
702  { 112, 1, 1, 1, 1153 },
703  { 325, 1, 1, 1, 1153 },
704  { 164, 14, 1, 9, 994 },
705  { 377, 17, 1, 9, 994 },
706  { 549, 20, 1, 9, 994 },
707  { 715, 23, 1, 9, 994 },
708  { 1282, 26, 1, 9, 994 },
709  { 1416, 29, 1, 9, 994 },
710  { 1546, 32, 1, 9, 994 },
711  { 1676, 35, 1, 9, 994 },
712  { 1801, 38, 1, 9, 994 },
713  { 1939, 41, 1, 9, 994 },
714  { 14, 44, 1, 9, 994 },
715  { 227, 47, 1, 9, 994 },
716  { 440, 50, 1, 9, 994 },
717  { 606, 53, 1, 9, 994 },
718  { 764, 56, 1, 9, 994 },
719  { 1327, 59, 1, 9, 994 },
720  { 92, 1, 150, 1, 2401 },
721  { 305, 1, 148, 1, 2401 },
722  { 518, 1, 146, 1, 2401 },
723  { 684, 1, 144, 1, 2401 },
724  { 167, 1, 161, 1, 3985 },
725  { 380, 1, 165, 1, 3985 },
726  { 552, 1, 165, 1, 3985 },
727  { 718, 1, 169, 1, 3985 },
728  { 1285, 1, 169, 1, 3985 },
729  { 1419, 1, 173, 1, 3985 },
730  { 1549, 1, 173, 1, 3985 },
731  { 1679, 1, 177, 1, 3985 },
732  { 1804, 1, 177, 1, 3985 },
733  { 1942, 1, 181, 1, 3985 },
734  { 18, 1, 181, 1, 3985 },
735  { 231, 1, 185, 1, 3985 },
736  { 444, 1, 185, 1, 3985 },
737  { 610, 1, 189, 1, 3985 },
738  { 768, 1, 189, 1, 3985 },
739  { 1331, 1, 193, 1, 3985 },
740  { 1461, 1, 193, 1, 3985 },
741  { 1591, 1, 197, 1, 3985 },
742  { 1721, 1, 197, 1, 3985 },
743  { 1843, 1, 201, 1, 3985 },
744  { 59, 1, 201, 1, 3985 },
745  { 272, 1, 205, 1, 3985 },
746  { 485, 1, 205, 1, 3985 },
747  { 651, 1, 209, 1, 3985 },
748  { 809, 1, 209, 1, 3985 },
749  { 1372, 1, 213, 1, 3985 },
750  { 1502, 1, 213, 1, 3985 },
751  { 1632, 1, 217, 1, 3985 },
752  { 1762, 1, 217, 1, 3985 },
753  { 1900, 1, 221, 1, 3985 },
754  { 119, 1, 221, 1, 3985 },
755  { 332, 1, 225, 1, 3985 },
756  { 159, 1, 1, 1, 3985 },
757  { 372, 1, 1, 1, 3985 },
758  { 544, 1, 1, 1, 3985 },
759  { 710, 1, 1, 1, 3985 },
760  { 1277, 1, 1, 1, 3985 },
761  { 1411, 1, 1, 1, 3985 },
762  { 1541, 1, 1, 1, 3985 },
763  { 1671, 1, 1, 1, 3985 },
764  { 191, 1, 1, 1, 3985 },
765  { 404, 1, 1, 1, 3985 },
766  { 573, 1, 1, 1, 3985 },
767  { 731, 1, 1, 1, 3985 },
768  { 1294, 1, 1, 1, 3985 },
769  { 1428, 1, 1, 1, 3985 },
770  { 1558, 1, 1, 1, 3985 },
771  { 1688, 1, 1, 1, 3985 },
772  { 1813, 1, 1, 1, 3985 },
773  { 1951, 1, 1, 1, 3985 },
774  { 29, 1, 1, 1, 3985 },
775  { 242, 1, 1, 1, 3985 },
776  { 455, 1, 1, 1, 3985 },
777  { 621, 1, 1, 1, 3985 },
778  { 779, 1, 1, 1, 3985 },
779  { 1342, 1, 1, 1, 3985 },
780  { 1472, 1, 1, 1, 3985 },
781  { 1602, 1, 1, 1, 3985 },
782  { 1732, 1, 1, 1, 3985 },
783  { 1854, 1, 1, 1, 3985 },
784  { 76, 1, 1, 1, 3985 },
785  { 289, 1, 1, 1, 3985 },
786  { 502, 1, 1, 1, 3985 },
787  { 668, 1, 1, 1, 3985 },
788  { 826, 1, 1, 1, 3985 },
789  { 1389, 1, 1, 1, 3985 },
790  { 1519, 1, 1, 1, 3985 },
791  { 1649, 1, 1, 1, 3985 },
792  { 1779, 1, 1, 1, 3985 },
793  { 1917, 1, 1, 1, 3985 },
794  { 136, 1, 1, 1, 3985 },
795  { 349, 1, 1, 1, 3985 },
796  { 1253, 136, 1, 0, 1184 },
797  { 170, 1, 158, 1, 3953 },
798  { 383, 1, 158, 1, 3953 },
799  { 555, 1, 158, 1, 3953 },
800  { 721, 1, 158, 1, 3953 },
801  { 1288, 1, 158, 1, 3953 },
802  { 1422, 1, 158, 1, 3953 },
803  { 1552, 1, 158, 1, 3953 },
804  { 1682, 1, 158, 1, 3953 },
805  { 1807, 1, 158, 1, 3953 },
806  { 1945, 1, 158, 1, 3953 },
807  { 22, 1, 158, 1, 3953 },
808  { 235, 1, 158, 1, 3953 },
809  { 448, 1, 158, 1, 3953 },
810  { 614, 1, 158, 1, 3953 },
811  { 772, 1, 158, 1, 3953 },
812  { 1335, 1, 158, 1, 3953 },
813  { 1465, 1, 158, 1, 3953 },
814  { 1595, 1, 158, 1, 3953 },
815  { 1725, 1, 158, 1, 3953 },
816  { 1847, 1, 158, 1, 3953 },
817  { 63, 1, 158, 1, 3953 },
818  { 276, 1, 158, 1, 3953 },
819  { 489, 1, 158, 1, 3953 },
820  { 655, 1, 158, 1, 3953 },
821  { 813, 1, 158, 1, 3953 },
822  { 1376, 1, 158, 1, 3953 },
823  { 1506, 1, 158, 1, 3953 },
824  { 1636, 1, 158, 1, 3953 },
825  { 1766, 1, 158, 1, 3953 },
826  { 1904, 1, 158, 1, 3953 },
827  { 123, 1, 158, 1, 3953 },
828  { 336, 1, 158, 1, 3953 },
829  { 1259, 128, 1, 0, 1216 },
830  { 172, 1, 233, 1, 1826 },
831  { 385, 1, 134, 1, 1826 },
832  { 557, 1, 134, 1, 1826 },
833  { 723, 1, 134, 1, 1826 },
834  { 196, 1, 1, 1, 3921 },
835  { 409, 1, 1, 1, 3921 },
836  { 578, 1, 1, 1, 3921 },
837  { 736, 1, 1, 1, 3921 },
838  { 1299, 1, 1, 1, 3921 },
839  { 1433, 1, 1, 1, 3921 },
840  { 1563, 1, 1, 1, 3921 },
841  { 1693, 1, 1, 1, 3921 },
842  { 1818, 1, 1, 1, 3921 },
843  { 1956, 1, 1, 1, 3921 },
844  { 35, 1, 1, 1, 3921 },
845  { 248, 1, 1, 1, 3921 },
846  { 461, 1, 1, 1, 3921 },
847  { 627, 1, 1, 1, 3921 },
848  { 785, 1, 1, 1, 3921 },
849  { 1348, 1, 1, 1, 3921 },
850  { 1478, 1, 1, 1, 3921 },
851  { 1608, 1, 1, 1, 3921 },
852  { 1738, 1, 1, 1, 3921 },
853  { 1860, 1, 1, 1, 3921 },
854  { 82, 1, 1, 1, 3921 },
855  { 295, 1, 1, 1, 3921 },
856  { 508, 1, 1, 1, 3921 },
857  { 674, 1, 1, 1, 3921 },
858  { 832, 1, 1, 1, 3921 },
859  { 1395, 1, 1, 1, 3921 },
860  { 1525, 1, 1, 1, 3921 },
861  { 1655, 1, 1, 1, 3921 },
862  { 1785, 1, 1, 1, 3921 },
863  { 1923, 1, 1, 1, 3921 },
864  { 142, 1, 1, 1, 3921 },
865  { 355, 1, 1, 1, 3921 },
866  { 176, 1, 100, 1, 3921 },
867  { 389, 1, 100, 1, 3921 },
868  { 184, 1, 229, 1, 1794 },
869  { 397, 1, 126, 1, 1794 },
870  { 566, 1, 126, 1, 1794 },
871  { 727, 1, 126, 1, 1794 },
872  { 179, 1, 1, 1, 3889 },
873  { 392, 1, 1, 1, 3889 },
874  { 561, 1, 1, 1, 3889 },
875  { 188, 1, 1, 1, 3889 },
876  { 401, 1, 1, 1, 3889 },
877  { 570, 1, 1, 1, 3889 },
878  { 1239, 124, 1, 0, 1248 },
879  { 201, 1, 98, 1, 3857 },
880  { 414, 1, 98, 1, 3857 },
881  { 583, 1, 98, 1, 3857 },
882  { 741, 1, 98, 1, 3857 },
883  { 1304, 1, 98, 1, 3857 },
884  { 1438, 1, 98, 1, 3857 },
885  { 1568, 1, 98, 1, 3857 },
886  { 1698, 1, 98, 1, 3857 },
887  { 1265, 122, 1, 0, 1280 },
888  { 204, 1, 96, 1, 3825 },
889  { 417, 1, 96, 1, 3825 },
890  { 586, 1, 96, 1, 3825 },
891  { 744, 1, 96, 1, 3825 },
892  { 1307, 1, 96, 1, 3825 },
893  { 1441, 1, 96, 1, 3825 },
894  { 1571, 1, 96, 1, 3825 },
895  { 1701, 1, 96, 1, 3825 },
896  { 1823, 1, 96, 1, 3825 },
897  { 1961, 1, 96, 1, 3825 },
898  { 207, 1, 96, 1, 3825 },
899  { 420, 1, 96, 1, 3825 },
900  { 210, 92, 1, 8, 1425 },
901  { 423, 92, 1, 8, 1425 },
902  { 589, 92, 1, 8, 1425 },
903  { 747, 92, 1, 8, 1425 },
904  { 1310, 92, 1, 8, 1425 },
905  { 1444, 92, 1, 8, 1425 },
906  { 1574, 92, 1, 8, 1425 },
907  { 1704, 92, 1, 8, 1425 },
908  { 1826, 92, 1, 8, 1425 },
909  { 1964, 92, 1, 8, 1425 },
910  { 41, 92, 1, 8, 1425 },
911  { 254, 92, 1, 8, 1425 },
912  { 467, 92, 1, 8, 1425 },
913  { 633, 92, 1, 8, 1425 },
914  { 791, 92, 1, 8, 1425 },
915  { 1354, 92, 1, 8, 1425 },
916  { 1484, 92, 1, 8, 1425 },
917  { 1614, 92, 1, 8, 1425 },
918  { 1744, 92, 1, 8, 1425 },
919  { 1866, 92, 1, 8, 1425 },
920  { 88, 92, 1, 8, 1425 },
921  { 301, 92, 1, 8, 1425 },
922  { 514, 92, 1, 8, 1425 },
923  { 680, 92, 1, 8, 1425 },
924  { 838, 92, 1, 8, 1425 },
925  { 1401, 92, 1, 8, 1425 },
926  { 1531, 92, 1, 8, 1425 },
927  { 1661, 92, 1, 8, 1425 },
928  { 1791, 92, 1, 8, 1425 },
929  { 1929, 92, 1, 8, 1425 },
930  { 148, 92, 1, 8, 1425 },
931  { 361, 92, 1, 8, 1425 },
932  { 1245, 118, 1, 0, 1921 },
933  { 869, 118, 1, 0, 1921 },
934  { 947, 118, 1, 0, 1921 },
935  { 997, 118, 1, 0, 1921 },
936  { 1035, 118, 1, 0, 1921 },
937  { 875, 130, 1, 12, 656 },
938  { 882, 93, 159, 9, 1377 },
939  { 953, 93, 159, 9, 1377 },
940  { 1003, 93, 159, 9, 1377 },
941  { 1041, 93, 159, 9, 1377 },
942  { 1073, 93, 159, 9, 1377 },
943  { 1105, 93, 159, 9, 1377 },
944  { 1137, 93, 159, 9, 1377 },
945  { 1169, 93, 159, 9, 1377 },
946  { 1201, 93, 159, 9, 1377 },
947  { 1227, 93, 159, 9, 1377 },
948  { 848, 93, 159, 9, 1377 },
949  { 926, 93, 159, 9, 1377 },
950  { 983, 93, 159, 9, 1377 },
951  { 1021, 93, 159, 9, 1377 },
952  { 1059, 93, 159, 9, 1377 },
953  { 1091, 93, 159, 9, 1377 },
954  { 1123, 93, 159, 9, 1377 },
955  { 1155, 93, 159, 9, 1377 },
956  { 1187, 93, 159, 9, 1377 },
957  { 1213, 93, 159, 9, 1377 },
958  { 855, 93, 159, 9, 1377 },
959  { 933, 93, 159, 9, 1377 },
960  { 990, 93, 159, 9, 1377 },
961  { 1028, 93, 159, 9, 1377 },
962  { 1066, 93, 159, 9, 1377 },
963  { 1098, 93, 159, 9, 1377 },
964  { 1130, 93, 159, 9, 1377 },
965  { 1162, 93, 159, 9, 1377 },
966  { 1194, 93, 159, 9, 1377 },
967  { 1220, 93, 159, 9, 1377 },
968  { 862, 93, 159, 9, 1377 },
969  { 940, 93, 159, 9, 1377 },
970  { 1870, 1, 116, 1, 1120 },
971  { 888, 138, 235, 0, 1344 },
972  { 895, 152, 1, 0, 2241 },
973  { 959, 152, 1, 0, 2241 },
974  { 901, 152, 231, 0, 1312 },
975  { 908, 154, 1, 0, 2273 },
976  { 965, 154, 1, 0, 2273 },
977  { 1009, 154, 1, 0, 2273 },
978  { 1047, 154, 1, 0, 2273 },
979  { 1079, 154, 1, 0, 2273 },
980  { 1111, 154, 1, 0, 2273 },
981  { 1143, 154, 1, 0, 2273 },
982  { 1175, 154, 1, 0, 2273 },
983  { 914, 156, 1, 0, 2273 },
984  { 971, 156, 1, 0, 2273 },
985  { 1015, 156, 1, 0, 2273 },
986  { 1053, 156, 1, 0, 2273 },
987  { 1085, 156, 1, 0, 2273 },
988  { 1117, 156, 1, 0, 2273 },
989  { 1149, 156, 1, 0, 2273 },
990  { 1181, 156, 1, 0, 2273 },
991  { 1207, 156, 1, 0, 2273 },
992  { 1233, 156, 1, 0, 2273 },
993  { 920, 156, 1, 0, 2273 },
994  { 977, 156, 1, 0, 2273 },
995};
996
997  static MCPhysReg OddSP[] = {
998    Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
999  };
1000
1001  // OddSP Bit set.
1002  static uint8_t OddSPBits[] = {
1003    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
1004  };
1005
1006  // CCR Register Class...
1007  static MCPhysReg CCR[] = {
1008    Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, Mips_FCR30, Mips_FCR31,
1009  };
1010
1011  // CCR Bit set.
1012  static uint8_t CCRBits[] = {
1013    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1014  };
1015
1016  // COP2 Register Class...
1017  static MCPhysReg COP2[] = {
1018    Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, Mips_COP230, Mips_COP231,
1019  };
1020
1021  // COP2 Bit set.
1022  static uint8_t COP2Bits[] = {
1023    0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0xf8, 0xff, 0xff, 0x01,
1024  };
1025
1026  // COP3 Register Class...
1027  static MCPhysReg COP3[] = {
1028    Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, Mips_COP330, Mips_COP331,
1029  };
1030
1031  // COP3 Bit set.
1032  static uint8_t COP3Bits[] = {
1033    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0xfe, 0xff, 0x7f,
1034  };
1035
1036  // DSPR Register Class...
1037  static MCPhysReg DSPR[] = {
1038    Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA,
1039  };
1040
1041  // DSPR Bit set.
1042  static uint8_t DSPRBits[] = {
1043    0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
1044  };
1045
1046  // FGR32 Register Class...
1047  static MCPhysReg FGR32[] = {
1048    Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31,
1049  };
1050
1051  // FGR32 Bit set.
1052  static uint8_t FGR32Bits[] = {
1053    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1054  };
1055
1056  // FGRCC Register Class...
1057  static MCPhysReg FGRCC[] = {
1058    Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31,
1059  };
1060
1061  // FGRCC Bit set.
1062  static uint8_t FGRCCBits[] = {
1063    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1064  };
1065
1066  // FGRH32 Register Class...
1067  static MCPhysReg FGRH32[] = {
1068    Mips_F_HI0, Mips_F_HI1, Mips_F_HI2, Mips_F_HI3, Mips_F_HI4, Mips_F_HI5, Mips_F_HI6, Mips_F_HI7, Mips_F_HI8, Mips_F_HI9, Mips_F_HI10, Mips_F_HI11, Mips_F_HI12, Mips_F_HI13, Mips_F_HI14, Mips_F_HI15, Mips_F_HI16, Mips_F_HI17, Mips_F_HI18, Mips_F_HI19, Mips_F_HI20, Mips_F_HI21, Mips_F_HI22, Mips_F_HI23, Mips_F_HI24, Mips_F_HI25, Mips_F_HI26, Mips_F_HI27, Mips_F_HI28, Mips_F_HI29, Mips_F_HI30, Mips_F_HI31,
1069  };
1070
1071  // FGRH32 Bit set.
1072  static uint8_t FGRH32Bits[] = {
1073    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
1074  };
1075
1076  // GPR32 Register Class...
1077  static MCPhysReg GPR32[] = {
1078    Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA,
1079  };
1080
1081  // GPR32 Bit set.
1082  static uint8_t GPR32Bits[] = {
1083    0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
1084  };
1085
1086  // HWRegs Register Class...
1087  static MCPhysReg HWRegs[] = {
1088    Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, Mips_HWR30, Mips_HWR31,
1089  };
1090
1091  // HWRegs Bit set.
1092  static uint8_t HWRegsBits[] = {
1093    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
1094  };
1095
1096  // OddSP_with_sub_hi Register Class...
1097  static MCPhysReg OddSP_with_sub_hi[] = {
1098    Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
1099  };
1100
1101  // OddSP_with_sub_hi Bit set.
1102  static uint8_t OddSP_with_sub_hiBits[] = {
1103    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
1104  };
1105
1106  // FGR32_and_OddSP Register Class...
1107  static MCPhysReg FGR32_and_OddSP[] = {
1108    Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31,
1109  };
1110
1111  // FGR32_and_OddSP Bit set.
1112  static uint8_t FGR32_and_OddSPBits[] = {
1113    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
1114  };
1115
1116  // FGRH32_and_OddSP Register Class...
1117  static MCPhysReg FGRH32_and_OddSP[] = {
1118    Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31,
1119  };
1120
1121  // FGRH32_and_OddSP Bit set.
1122  static uint8_t FGRH32_and_OddSPBits[] = {
1123    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a,
1124  };
1125
1126  // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class...
1127  static MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = {
1128    Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
1129  };
1130
1131  // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set.
1132  static uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = {
1133    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
1134  };
1135
1136  // CPU16RegsPlusSP Register Class...
1137  static MCPhysReg CPU16RegsPlusSP[] = {
1138    Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, Mips_SP,
1139  };
1140
1141  // CPU16RegsPlusSP Bit set.
1142  static uint8_t CPU16RegsPlusSPBits[] = {
1143    0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
1144  };
1145
1146  // CC Register Class...
1147  static MCPhysReg CC[] = {
1148    Mips_CC0, Mips_CC1, Mips_CC2, Mips_CC3, Mips_CC4, Mips_CC5, Mips_CC6, Mips_CC7,
1149  };
1150
1151  // CC Bit set.
1152  static uint8_t CCBits[] = {
1153    0x00, 0x00, 0x00, 0x80, 0x7f,
1154  };
1155
1156  // CPU16Regs Register Class...
1157  static MCPhysReg CPU16Regs[] = {
1158    Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1,
1159  };
1160
1161  // CPU16Regs Bit set.
1162  static uint8_t CPU16RegsBits[] = {
1163    0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
1164  };
1165
1166  // FCC Register Class...
1167  static MCPhysReg FCC[] = {
1168    Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7,
1169  };
1170
1171  // FCC Bit set.
1172  static uint8_t FCCBits[] = {
1173    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
1174  };
1175
1176  // MSACtrl Register Class...
1177  static MCPhysReg MSACtrl[] = {
1178    Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap,
1179  };
1180
1181  // MSACtrl Bit set.
1182  static uint8_t MSACtrlBits[] = {
1183    0x00, 0xfc, 0x03,
1184  };
1185
1186  // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class...
1187  static MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = {
1188    Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15,
1189  };
1190
1191  // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set.
1192  static uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = {
1193    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
1194  };
1195
1196  // HI32DSP Register Class...
1197  static MCPhysReg HI32DSP[] = {
1198    Mips_HI0, Mips_HI1, Mips_HI2, Mips_HI3,
1199  };
1200
1201  // HI32DSP Bit set.
1202  static uint8_t HI32DSPBits[] = {
1203    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
1204  };
1205
1206  // LO32DSP Register Class...
1207  static MCPhysReg LO32DSP[] = {
1208    Mips_LO0, Mips_LO1, Mips_LO2, Mips_LO3,
1209  };
1210
1211  // LO32DSP Bit set.
1212  static uint8_t LO32DSPBits[] = {
1213    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
1214  };
1215
1216  // CPURAReg Register Class...
1217  static MCPhysReg CPURAReg[] = {
1218    Mips_RA,
1219  };
1220
1221  // CPURAReg Bit set.
1222  static uint8_t CPURARegBits[] = {
1223    0x00, 0x00, 0x08,
1224  };
1225
1226  // CPUSPReg Register Class...
1227  static MCPhysReg CPUSPReg[] = {
1228    Mips_SP,
1229  };
1230
1231  // CPUSPReg Bit set.
1232  static uint8_t CPUSPRegBits[] = {
1233    0x00, 0x00, 0x10,
1234  };
1235
1236  // DSPCC Register Class...
1237  static MCPhysReg DSPCC[] = {
1238    Mips_DSPCCond,
1239  };
1240
1241  // DSPCC Bit set.
1242  static uint8_t DSPCCBits[] = {
1243    0x04,
1244  };
1245
1246  // HI32 Register Class...
1247  static MCPhysReg HI32[] = {
1248    Mips_HI0,
1249  };
1250
1251  // HI32 Bit set.
1252  static uint8_t HI32Bits[] = {
1253    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
1254  };
1255
1256  // LO32 Register Class...
1257  static MCPhysReg LO32[] = {
1258    Mips_LO0,
1259  };
1260
1261  // LO32 Bit set.
1262  static uint8_t LO32Bits[] = {
1263    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
1264  };
1265
1266  // FGR64 Register Class...
1267  static MCPhysReg FGR64[] = {
1268    Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, Mips_D30_64, Mips_D31_64,
1269  };
1270
1271  // FGR64 Bit set.
1272  static uint8_t FGR64Bits[] = {
1273    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
1274  };
1275
1276  // GPR64 Register Class...
1277  static MCPhysReg GPR64[] = {
1278    Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64,
1279  };
1280
1281  // GPR64 Bit set.
1282  static uint8_t GPR64Bits[] = {
1283    0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
1284  };
1285
1286  // AFGR64 Register Class...
1287  static MCPhysReg AFGR64[] = {
1288    Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, Mips_D12, Mips_D13, Mips_D14, Mips_D15,
1289  };
1290
1291  // AFGR64 Bit set.
1292  static uint8_t AFGR64Bits[] = {
1293    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1294  };
1295
1296  // FGR64_and_OddSP Register Class...
1297  static MCPhysReg FGR64_and_OddSP[] = {
1298    Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
1299  };
1300
1301  // FGR64_and_OddSP Bit set.
1302  static uint8_t FGR64_and_OddSPBits[] = {
1303    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
1304  };
1305
1306  // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...
1307  static MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {
1308    Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64,
1309  };
1310
1311  // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.
1312  static uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {
1313    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
1314  };
1315
1316  // AFGR64_and_OddSP Register Class...
1317  static MCPhysReg AFGR64_and_OddSP[] = {
1318    Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15,
1319  };
1320
1321  // AFGR64_and_OddSP Bit set.
1322  static uint8_t AFGR64_and_OddSPBits[] = {
1323    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
1324  };
1325
1326  // GPR64_with_sub_32_in_CPU16Regs Register Class...
1327  static MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {
1328    Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64,
1329  };
1330
1331  // GPR64_with_sub_32_in_CPU16Regs Bit set.
1332  static uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {
1333    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
1334  };
1335
1336  // ACC64DSP Register Class...
1337  static MCPhysReg ACC64DSP[] = {
1338    Mips_AC0, Mips_AC1, Mips_AC2, Mips_AC3,
1339  };
1340
1341  // ACC64DSP Bit set.
1342  static uint8_t ACC64DSPBits[] = {
1343    0x00, 0x00, 0x00, 0x3c,
1344  };
1345
1346  // OCTEON_MPL Register Class...
1347  static MCPhysReg OCTEON_MPL[] = {
1348    Mips_MPL0, Mips_MPL1, Mips_MPL2,
1349  };
1350
1351  // OCTEON_MPL Bit set.
1352  static uint8_t OCTEON_MPLBits[] = {
1353    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,
1354  };
1355
1356  // OCTEON_P Register Class...
1357  static MCPhysReg OCTEON_P[] = {
1358    Mips_P0, Mips_P1, Mips_P2,
1359  };
1360
1361  // OCTEON_P Bit set.
1362  static uint8_t OCTEON_PBits[] = {
1363    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
1364  };
1365
1366  // ACC64 Register Class...
1367  static MCPhysReg ACC64[] = {
1368    Mips_AC0,
1369  };
1370
1371  // ACC64 Bit set.
1372  static uint8_t ACC64Bits[] = {
1373    0x00, 0x00, 0x00, 0x04,
1374  };
1375
1376  // GPR64_with_sub_32_in_CPURAReg Register Class...
1377  static MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {
1378    Mips_RA_64,
1379  };
1380
1381  // GPR64_with_sub_32_in_CPURAReg Bit set.
1382  static uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {
1383    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
1384  };
1385
1386  // GPR64_with_sub_32_in_CPUSPReg Register Class...
1387  static MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = {
1388    Mips_SP_64,
1389  };
1390
1391  // GPR64_with_sub_32_in_CPUSPReg Bit set.
1392  static uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = {
1393    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
1394  };
1395
1396  // HI64 Register Class...
1397  static MCPhysReg HI64[] = {
1398    Mips_HI0_64,
1399  };
1400
1401  // HI64 Bit set.
1402  static uint8_t HI64Bits[] = {
1403    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
1404  };
1405
1406  // LO64 Register Class...
1407  static MCPhysReg LO64[] = {
1408    Mips_LO0_64,
1409  };
1410
1411  // LO64 Bit set.
1412  static uint8_t LO64Bits[] = {
1413    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
1414  };
1415
1416  // MSA128B Register Class...
1417  static MCPhysReg MSA128B[] = {
1418    Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
1419  };
1420
1421  // MSA128B Bit set.
1422  static uint8_t MSA128BBits[] = {
1423    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1424  };
1425
1426  // MSA128D Register Class...
1427  static MCPhysReg MSA128D[] = {
1428    Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
1429  };
1430
1431  // MSA128D Bit set.
1432  static uint8_t MSA128DBits[] = {
1433    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1434  };
1435
1436  // MSA128H Register Class...
1437  static MCPhysReg MSA128H[] = {
1438    Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
1439  };
1440
1441  // MSA128H Bit set.
1442  static uint8_t MSA128HBits[] = {
1443    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1444  };
1445
1446  // MSA128W Register Class...
1447  static MCPhysReg MSA128W[] = {
1448    Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
1449  };
1450
1451  // MSA128W Bit set.
1452  static uint8_t MSA128WBits[] = {
1453    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1454  };
1455
1456  // MSA128B_with_sub_64_in_OddSP Register Class...
1457  static MCPhysReg MSA128B_with_sub_64_in_OddSP[] = {
1458    Mips_W1, Mips_W3, Mips_W5, Mips_W7, Mips_W9, Mips_W11, Mips_W13, Mips_W15, Mips_W17, Mips_W19, Mips_W21, Mips_W23, Mips_W25, Mips_W27, Mips_W29, Mips_W31,
1459  };
1460
1461  // MSA128B_with_sub_64_in_OddSP Bit set.
1462  static uint8_t MSA128B_with_sub_64_in_OddSPBits[] = {
1463    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
1464  };
1465
1466  // ACC128 Register Class...
1467  static MCPhysReg ACC128[] = {
1468    Mips_AC0_64,
1469  };
1470
1471  // ACC128 Bit set.
1472  static uint8_t ACC128Bits[] = {
1473    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
1474  };
1475
1476static MCRegisterClass MipsMCRegisterClasses[] = {
1477  { "OddSP", OddSP, OddSPBits, 56, sizeof(OddSPBits), Mips_OddSPRegClassID, 4, 4, 1, 0 },
1478  { "CCR", CCR, CCRBits, 32, sizeof(CCRBits), Mips_CCRRegClassID, 4, 4, 1, 0 },
1479  { "COP2", COP2, COP2Bits, 32, sizeof(COP2Bits), Mips_COP2RegClassID, 4, 4, 1, 0 },
1480  { "COP3", COP3, COP3Bits, 32, sizeof(COP3Bits), Mips_COP3RegClassID, 4, 4, 1, 0 },
1481  { "DSPR", DSPR, DSPRBits, 32, sizeof(DSPRBits), Mips_DSPRRegClassID, 4, 4, 1, 1 },
1482  { "FGR32", FGR32, FGR32Bits, 32, sizeof(FGR32Bits), Mips_FGR32RegClassID, 4, 4, 1, 1 },
1483  { "FGRCC", FGRCC, FGRCCBits, 32, sizeof(FGRCCBits), Mips_FGRCCRegClassID, 4, 4, 1, 1 },
1484  { "FGRH32", FGRH32, FGRH32Bits, 32, sizeof(FGRH32Bits), Mips_FGRH32RegClassID, 4, 4, 1, 0 },
1485  { "GPR32", GPR32, GPR32Bits, 32, sizeof(GPR32Bits), Mips_GPR32RegClassID, 4, 4, 1, 1 },
1486  { "HWRegs", HWRegs, HWRegsBits, 32, sizeof(HWRegsBits), Mips_HWRegsRegClassID, 4, 4, 1, 0 },
1487  { "OddSP_with_sub_hi", OddSP_with_sub_hi, OddSP_with_sub_hiBits, 24, sizeof(OddSP_with_sub_hiBits), Mips_OddSP_with_sub_hiRegClassID, 4, 4, 1, 0 },
1488  { "FGR32_and_OddSP", FGR32_and_OddSP, FGR32_and_OddSPBits, 16, sizeof(FGR32_and_OddSPBits), Mips_FGR32_and_OddSPRegClassID, 4, 4, 1, 1 },
1489  { "FGRH32_and_OddSP", FGRH32_and_OddSP, FGRH32_and_OddSPBits, 16, sizeof(FGRH32_and_OddSPBits), Mips_FGRH32_and_OddSPRegClassID, 4, 4, 1, 0 },
1490  { "OddSP_with_sub_hi_with_sub_hi_in_FGRH32", OddSP_with_sub_hi_with_sub_hi_in_FGRH32, OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits, 16, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits), Mips_OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID, 4, 4, 1, 0 },
1491  { "CPU16RegsPlusSP", CPU16RegsPlusSP, CPU16RegsPlusSPBits, 9, sizeof(CPU16RegsPlusSPBits), Mips_CPU16RegsPlusSPRegClassID, 4, 4, 1, 1 },
1492  { "CC", CC, CCBits, 8, sizeof(CCBits), Mips_CCRegClassID, 4, 4, 1, 0 },
1493  { "CPU16Regs", CPU16Regs, CPU16RegsBits, 8, sizeof(CPU16RegsBits), Mips_CPU16RegsRegClassID, 4, 4, 1, 1 },
1494  { "FCC", FCC, FCCBits, 8, sizeof(FCCBits), Mips_FCCRegClassID, 4, 4, 1, 0 },
1495  { "MSACtrl", MSACtrl, MSACtrlBits, 8, sizeof(MSACtrlBits), Mips_MSACtrlRegClassID, 4, 4, 1, 1 },
1496  { "OddSP_with_sub_hi_with_sub_hi_in_FGR32", OddSP_with_sub_hi_with_sub_hi_in_FGR32, OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits, 8, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits), Mips_OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID, 4, 4, 1, 0 },
1497  { "HI32DSP", HI32DSP, HI32DSPBits, 4, sizeof(HI32DSPBits), Mips_HI32DSPRegClassID, 4, 4, 1, 1 },
1498  { "LO32DSP", LO32DSP, LO32DSPBits, 4, sizeof(LO32DSPBits), Mips_LO32DSPRegClassID, 4, 4, 1, 1 },
1499  { "CPURAReg", CPURAReg, CPURARegBits, 1, sizeof(CPURARegBits), Mips_CPURARegRegClassID, 4, 4, 1, 0 },
1500  { "CPUSPReg", CPUSPReg, CPUSPRegBits, 1, sizeof(CPUSPRegBits), Mips_CPUSPRegRegClassID, 4, 4, 1, 0 },
1501  { "DSPCC", DSPCC, DSPCCBits, 1, sizeof(DSPCCBits), Mips_DSPCCRegClassID, 4, 4, 1, 1 },
1502  { "HI32", HI32, HI32Bits, 1, sizeof(HI32Bits), Mips_HI32RegClassID, 4, 4, 1, 1 },
1503  { "LO32", LO32, LO32Bits, 1, sizeof(LO32Bits), Mips_LO32RegClassID, 4, 4, 1, 1 },
1504  { "FGR64", FGR64, FGR64Bits, 32, sizeof(FGR64Bits), Mips_FGR64RegClassID, 8, 8, 1, 1 },
1505  { "GPR64", GPR64, GPR64Bits, 32, sizeof(GPR64Bits), Mips_GPR64RegClassID, 8, 8, 1, 1 },
1506  { "AFGR64", AFGR64, AFGR64Bits, 16, sizeof(AFGR64Bits), Mips_AFGR64RegClassID, 8, 8, 1, 1 },
1507  { "FGR64_and_OddSP", FGR64_and_OddSP, FGR64_and_OddSPBits, 16, sizeof(FGR64_and_OddSPBits), Mips_FGR64_and_OddSPRegClassID, 8, 8, 1, 1 },
1508  { "GPR64_with_sub_32_in_CPU16RegsPlusSP", GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 8, 8, 1, 1 },
1509  { "AFGR64_and_OddSP", AFGR64_and_OddSP, AFGR64_and_OddSPBits, 8, sizeof(AFGR64_and_OddSPBits), Mips_AFGR64_and_OddSPRegClassID, 8, 8, 1, 1 },
1510  { "GPR64_with_sub_32_in_CPU16Regs", GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID, 8, 8, 1, 1 },
1511  { "ACC64DSP", ACC64DSP, ACC64DSPBits, 4, sizeof(ACC64DSPBits), Mips_ACC64DSPRegClassID, 8, 8, 1, 1 },
1512  { "OCTEON_MPL", OCTEON_MPL, OCTEON_MPLBits, 3, sizeof(OCTEON_MPLBits), Mips_OCTEON_MPLRegClassID, 8, 8, 1, 0 },
1513  { "OCTEON_P", OCTEON_P, OCTEON_PBits, 3, sizeof(OCTEON_PBits), Mips_OCTEON_PRegClassID, 8, 8, 1, 0 },
1514  { "ACC64", ACC64, ACC64Bits, 1, sizeof(ACC64Bits), Mips_ACC64RegClassID, 8, 8, 1, 1 },
1515  { "GPR64_with_sub_32_in_CPURAReg", GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips_GPR64_with_sub_32_in_CPURARegRegClassID, 8, 8, 1, 1 },
1516  { "GPR64_with_sub_32_in_CPUSPReg", GPR64_with_sub_32_in_CPUSPReg, GPR64_with_sub_32_in_CPUSPRegBits, 1, sizeof(GPR64_with_sub_32_in_CPUSPRegBits), Mips_GPR64_with_sub_32_in_CPUSPRegRegClassID, 8, 8, 1, 1 },
1517  { "HI64", HI64, HI64Bits, 1, sizeof(HI64Bits), Mips_HI64RegClassID, 8, 8, 1, 1 },
1518  { "LO64", LO64, LO64Bits, 1, sizeof(LO64Bits), Mips_LO64RegClassID, 8, 8, 1, 1 },
1519  { "MSA128B", MSA128B, MSA128BBits, 32, sizeof(MSA128BBits), Mips_MSA128BRegClassID, 16, 16, 1, 1 },
1520  { "MSA128D", MSA128D, MSA128DBits, 32, sizeof(MSA128DBits), Mips_MSA128DRegClassID, 16, 16, 1, 1 },
1521  { "MSA128H", MSA128H, MSA128HBits, 32, sizeof(MSA128HBits), Mips_MSA128HRegClassID, 16, 16, 1, 1 },
1522  { "MSA128W", MSA128W, MSA128WBits, 32, sizeof(MSA128WBits), Mips_MSA128WRegClassID, 16, 16, 1, 1 },
1523  { "MSA128B_with_sub_64_in_OddSP", MSA128B_with_sub_64_in_OddSP, MSA128B_with_sub_64_in_OddSPBits, 16, sizeof(MSA128B_with_sub_64_in_OddSPBits), Mips_MSA128B_with_sub_64_in_OddSPRegClassID, 16, 16, 1, 1 },
1524  { "ACC128", ACC128, ACC128Bits, 1, sizeof(ACC128Bits), Mips_ACC128RegClassID, 16, 16, 1, 1 },
1525};
1526
1527#endif // GET_REGINFO_MC_DESC
1528