1#!/usr/bin/env python
2
3# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
4from __future__ import print_function
5from capstone import *
6from capstone.x86 import *
7from xprint import to_hex, to_x, to_x_32
8
9
10X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00"
11X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
12X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
13
14all_tests = (
15        (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", 0),
16        (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (AT&T syntax)", CS_OPT_SYNTAX_ATT),
17        (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", 0),
18        (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", 0),
19        )
20
21
22def print_insn_detail(mode, insn):
23    def print_string_hex(comment, str):
24        print(comment, end=' '),
25        for c in str:
26            print("0x%02x " % c, end=''),
27        print()
28
29    # print address, mnemonic and operands
30    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
31
32    # "data" instruction generated by SKIPDATA option has no detail
33    if insn.id == 0:
34        return
35
36    # print instruction prefix
37    print_string_hex("\tPrefix:", insn.prefix)
38
39    # print instruction's opcode
40    print_string_hex("\tOpcode:", insn.opcode)
41
42    # print operand's REX prefix (non-zero value is relavant for x86_64 instructions)
43    print("\trex: 0x%x" % (insn.rex))
44
45    # print operand's address size
46    print("\taddr_size: %u" % (insn.addr_size))
47
48    # print modRM byte
49    print("\tmodrm: 0x%x" % (insn.modrm))
50
51    # print displacement value
52    print("\tdisp: 0x%s" % to_x_32(insn.disp))
53
54    # SIB is not available in 16-bit mode
55    if (mode & CS_MODE_16 == 0):
56        # print SIB byte
57        print("\tsib: 0x%x" % (insn.sib))
58        if (insn.sib):
59            if insn.sib_base != 0:
60                print("\t\tsib_base: %s" % (insn.reg_name(insn.sib_base)))
61            if insn.sib_index != 0:
62                print("\t\tsib_index: %s" % (insn.reg_name(insn.sib_index)))
63            if insn.sib_scale != 0:
64                print("\t\tsib_scale: %d" % (insn.sib_scale))
65
66    # SSE CC type
67    if insn.sse_cc != X86_SSE_CC_INVALID:
68        print("\tsse_cc: %u" % (insn.sse_cc))
69
70    # AVX CC type
71    if insn.avx_cc != X86_AVX_CC_INVALID:
72        print("\tavx_cc: %u" % (insn.avx_cc))
73
74    # AVX Suppress All Exception
75    if insn.avx_sae:
76        print("\tavx_sae: TRUE")
77
78    # AVX Rounding Mode type
79    if insn.avx_rm != X86_AVX_RM_INVALID:
80        print("\tavx_rm: %u" % (insn.avx_rm))
81
82    count = insn.op_count(X86_OP_IMM)
83    if count > 0:
84        print("\timm_count: %u" % count)
85        for i in range(count):
86            op = insn.op_find(X86_OP_IMM, i + 1)
87            print("\t\timms[%u]: 0x%s" % (i + 1, to_x(op.imm)))
88
89    if len(insn.operands) > 0:
90        print("\top_count: %u" % len(insn.operands))
91        c = -1
92        for i in insn.operands:
93            c += 1
94            if i.type == X86_OP_REG:
95                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
96            if i.type == X86_OP_IMM:
97                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
98            if i.type == X86_OP_FP:
99                print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
100            if i.type == X86_OP_MEM:
101                print("\t\toperands[%u].type: MEM" % c)
102                if i.mem.segment != 0:
103                    print("\t\t\toperands[%u].mem.segment: REG = %s" % (c, insn.reg_name(i.mem.segment)))
104                if i.mem.base != 0:
105                    print("\t\t\toperands[%u].mem.base: REG = %s" % (c, insn.reg_name(i.mem.base)))
106                if i.mem.index != 0:
107                    print("\t\t\toperands[%u].mem.index: REG = %s" % (c, insn.reg_name(i.mem.index)))
108                if i.mem.scale != 1:
109                    print("\t\t\toperands[%u].mem.scale: %u" % (c, i.mem.scale))
110                if i.mem.disp != 0:
111                    print("\t\t\toperands[%u].mem.disp: 0x%s" % (c, to_x(i.mem.disp)))
112
113            # AVX broadcast type
114            if i.avx_bcast != X86_AVX_BCAST_INVALID:
115                print("\t\toperands[%u].avx_bcast: %u" % (c, i.avx_bcast))
116
117            # AVX zero opmask {z}
118            if i.avx_zero_opmask:
119                print("\t\toperands[%u].avx_zero_opmask: TRUE" % (c))
120
121            print("\t\toperands[%u].size: %u" % (c, i.size))
122
123
124# ## Test class Cs
125def test_class():
126
127    for (arch, mode, code, comment, syntax) in all_tests:
128        print("*" * 16)
129        print("Platform: %s" % comment)
130        print("Code: %s" % to_hex(code))
131        print("Disasm:")
132
133        try:
134            md = Cs(arch, mode)
135            md.detail = True
136
137            if syntax != 0:
138                md.syntax = syntax
139
140            for insn in md.disasm(code, 0x1000):
141                print_insn_detail(mode, insn)
142                print ()
143            print ("0x%x:\n" % (insn.address + insn.size))
144        except CsError as e:
145            print("ERROR: %s" % e)
146
147
148if __name__ == '__main__':
149    test_class()
150