1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /*
3  * linux/mdio.h: definitions for MDIO (clause 45) transceivers
4  * Copyright 2006-2009 Solarflare Communications Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License version 2 as published
8  * by the Free Software Foundation, incorporated herein by reference.
9  */
10 
11 #ifndef _UAPI__LINUX_MDIO_H__
12 #define _UAPI__LINUX_MDIO_H__
13 
14 #include <linux/types.h>
15 #include <linux/mii.h>
16 
17 /* MDIO Manageable Devices (MMDs). */
18 #define MDIO_MMD_PMAPMD		1	/* Physical Medium Attachment/
19 					 * Physical Medium Dependent */
20 #define MDIO_MMD_WIS		2	/* WAN Interface Sublayer */
21 #define MDIO_MMD_PCS		3	/* Physical Coding Sublayer */
22 #define MDIO_MMD_PHYXS		4	/* PHY Extender Sublayer */
23 #define MDIO_MMD_DTEXS		5	/* DTE Extender Sublayer */
24 #define MDIO_MMD_TC		6	/* Transmission Convergence */
25 #define MDIO_MMD_AN		7	/* Auto-Negotiation */
26 #define MDIO_MMD_C22EXT		29	/* Clause 22 extension */
27 #define MDIO_MMD_VEND1		30	/* Vendor specific 1 */
28 #define MDIO_MMD_VEND2		31	/* Vendor specific 2 */
29 
30 /* Generic MDIO registers. */
31 #define MDIO_CTRL1		MII_BMCR
32 #define MDIO_STAT1		MII_BMSR
33 #define MDIO_DEVID1		MII_PHYSID1
34 #define MDIO_DEVID2		MII_PHYSID2
35 #define MDIO_SPEED		4	/* Speed ability */
36 #define MDIO_DEVS1		5	/* Devices in package */
37 #define MDIO_DEVS2		6
38 #define MDIO_CTRL2		7	/* 10G control 2 */
39 #define MDIO_STAT2		8	/* 10G status 2 */
40 #define MDIO_PMA_TXDIS		9	/* 10G PMA/PMD transmit disable */
41 #define MDIO_PMA_RXDET		10	/* 10G PMA/PMD receive signal detect */
42 #define MDIO_PMA_EXTABLE	11	/* 10G PMA/PMD extended ability */
43 #define MDIO_PKGID1		14	/* Package identifier */
44 #define MDIO_PKGID2		15
45 #define MDIO_AN_ADVERTISE	16	/* AN advertising (base page) */
46 #define MDIO_AN_LPA		19	/* AN LP abilities (base page) */
47 #define MDIO_PCS_EEE_ABLE	20	/* EEE Capability register */
48 #define MDIO_PCS_EEE_WK_ERR	22	/* EEE wake error counter */
49 #define MDIO_PHYXS_LNSTAT	24	/* PHY XGXS lane state */
50 #define MDIO_AN_EEE_ADV		60	/* EEE advertisement */
51 #define MDIO_AN_EEE_LPABLE	61	/* EEE link partner ability */
52 
53 /* Media-dependent registers. */
54 #define MDIO_PMA_10GBT_SWAPPOL	130	/* 10GBASE-T pair swap & polarity */
55 #define MDIO_PMA_10GBT_TXPWR	131	/* 10GBASE-T TX power control */
56 #define MDIO_PMA_10GBT_SNR	133	/* 10GBASE-T SNR margin, lane A.
57 					 * Lanes B-D are numbered 134-136. */
58 #define MDIO_PMA_10GBR_FECABLE	170	/* 10GBASE-R FEC ability */
59 #define MDIO_PCS_10GBX_STAT1	24	/* 10GBASE-X PCS status 1 */
60 #define MDIO_PCS_10GBRT_STAT1	32	/* 10GBASE-R/-T PCS status 1 */
61 #define MDIO_PCS_10GBRT_STAT2	33	/* 10GBASE-R/-T PCS status 2 */
62 #define MDIO_AN_10GBT_CTRL	32	/* 10GBASE-T auto-negotiation control */
63 #define MDIO_AN_10GBT_STAT	33	/* 10GBASE-T auto-negotiation status */
64 
65 /* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
66 #define MDIO_PMA_LASI_RXCTRL	0x9000	/* RX_ALARM control */
67 #define MDIO_PMA_LASI_TXCTRL	0x9001	/* TX_ALARM control */
68 #define MDIO_PMA_LASI_CTRL	0x9002	/* LASI control */
69 #define MDIO_PMA_LASI_RXSTAT	0x9003	/* RX_ALARM status */
70 #define MDIO_PMA_LASI_TXSTAT	0x9004	/* TX_ALARM status */
71 #define MDIO_PMA_LASI_STAT	0x9005	/* LASI status */
72 
73 /* Control register 1. */
74 /* Enable extended speed selection */
75 #define MDIO_CTRL1_SPEEDSELEXT		(BMCR_SPEED1000 | BMCR_SPEED100)
76 /* All speed selection bits */
77 #define MDIO_CTRL1_SPEEDSEL		(MDIO_CTRL1_SPEEDSELEXT | 0x003c)
78 #define MDIO_CTRL1_FULLDPLX		BMCR_FULLDPLX
79 #define MDIO_CTRL1_LPOWER		BMCR_PDOWN
80 #define MDIO_CTRL1_RESET		BMCR_RESET
81 #define MDIO_PMA_CTRL1_LOOPBACK		0x0001
82 #define MDIO_PMA_CTRL1_SPEED1000	BMCR_SPEED1000
83 #define MDIO_PMA_CTRL1_SPEED100		BMCR_SPEED100
84 #define MDIO_PCS_CTRL1_LOOPBACK		BMCR_LOOPBACK
85 #define MDIO_PHYXS_CTRL1_LOOPBACK	BMCR_LOOPBACK
86 #define MDIO_AN_CTRL1_RESTART		BMCR_ANRESTART
87 #define MDIO_AN_CTRL1_ENABLE		BMCR_ANENABLE
88 #define MDIO_AN_CTRL1_XNP		0x2000	/* Enable extended next page */
89 #define MDIO_PCS_CTRL1_CLKSTOP_EN	0x400	/* Stop the clock during LPI */
90 
91 /* 10 Gb/s */
92 #define MDIO_CTRL1_SPEED10G		(MDIO_CTRL1_SPEEDSELEXT | 0x00)
93 /* 10PASS-TS/2BASE-TL */
94 #define MDIO_CTRL1_SPEED10P2B		(MDIO_CTRL1_SPEEDSELEXT | 0x04)
95 
96 /* Status register 1. */
97 #define MDIO_STAT1_LPOWERABLE		0x0002	/* Low-power ability */
98 #define MDIO_STAT1_LSTATUS		BMSR_LSTATUS
99 #define MDIO_STAT1_FAULT		0x0080	/* Fault */
100 #define MDIO_AN_STAT1_LPABLE		0x0001	/* Link partner AN ability */
101 #define MDIO_AN_STAT1_ABLE		BMSR_ANEGCAPABLE
102 #define MDIO_AN_STAT1_RFAULT		BMSR_RFAULT
103 #define MDIO_AN_STAT1_COMPLETE		BMSR_ANEGCOMPLETE
104 #define MDIO_AN_STAT1_PAGE		0x0040	/* Page received */
105 #define MDIO_AN_STAT1_XNP		0x0080	/* Extended next page status */
106 
107 /* Speed register. */
108 #define MDIO_SPEED_10G			0x0001	/* 10G capable */
109 #define MDIO_PMA_SPEED_2B		0x0002	/* 2BASE-TL capable */
110 #define MDIO_PMA_SPEED_10P		0x0004	/* 10PASS-TS capable */
111 #define MDIO_PMA_SPEED_1000		0x0010	/* 1000M capable */
112 #define MDIO_PMA_SPEED_100		0x0020	/* 100M capable */
113 #define MDIO_PMA_SPEED_10		0x0040	/* 10M capable */
114 #define MDIO_PCS_SPEED_10P2B		0x0002	/* 10PASS-TS/2BASE-TL capable */
115 
116 /* Device present registers. */
117 #define MDIO_DEVS_PRESENT(devad)	(1 << (devad))
118 #define MDIO_DEVS_PMAPMD		MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD)
119 #define MDIO_DEVS_WIS			MDIO_DEVS_PRESENT(MDIO_MMD_WIS)
120 #define MDIO_DEVS_PCS			MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
121 #define MDIO_DEVS_PHYXS			MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS)
122 #define MDIO_DEVS_DTEXS			MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS)
123 #define MDIO_DEVS_TC			MDIO_DEVS_PRESENT(MDIO_MMD_TC)
124 #define MDIO_DEVS_AN			MDIO_DEVS_PRESENT(MDIO_MMD_AN)
125 #define MDIO_DEVS_C22EXT		MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT)
126 
127 /* Control register 2. */
128 #define MDIO_PMA_CTRL2_TYPE		0x000f	/* PMA/PMD type selection */
129 #define MDIO_PMA_CTRL2_10GBCX4		0x0000	/* 10GBASE-CX4 type */
130 #define MDIO_PMA_CTRL2_10GBEW		0x0001	/* 10GBASE-EW type */
131 #define MDIO_PMA_CTRL2_10GBLW		0x0002	/* 10GBASE-LW type */
132 #define MDIO_PMA_CTRL2_10GBSW		0x0003	/* 10GBASE-SW type */
133 #define MDIO_PMA_CTRL2_10GBLX4		0x0004	/* 10GBASE-LX4 type */
134 #define MDIO_PMA_CTRL2_10GBER		0x0005	/* 10GBASE-ER type */
135 #define MDIO_PMA_CTRL2_10GBLR		0x0006	/* 10GBASE-LR type */
136 #define MDIO_PMA_CTRL2_10GBSR		0x0007	/* 10GBASE-SR type */
137 #define MDIO_PMA_CTRL2_10GBLRM		0x0008	/* 10GBASE-LRM type */
138 #define MDIO_PMA_CTRL2_10GBT		0x0009	/* 10GBASE-T type */
139 #define MDIO_PMA_CTRL2_10GBKX4		0x000a	/* 10GBASE-KX4 type */
140 #define MDIO_PMA_CTRL2_10GBKR		0x000b	/* 10GBASE-KR type */
141 #define MDIO_PMA_CTRL2_1000BT		0x000c	/* 1000BASE-T type */
142 #define MDIO_PMA_CTRL2_1000BKX		0x000d	/* 1000BASE-KX type */
143 #define MDIO_PMA_CTRL2_100BTX		0x000e	/* 100BASE-TX type */
144 #define MDIO_PMA_CTRL2_10BT		0x000f	/* 10BASE-T type */
145 #define MDIO_PCS_CTRL2_TYPE		0x0003	/* PCS type selection */
146 #define MDIO_PCS_CTRL2_10GBR		0x0000	/* 10GBASE-R type */
147 #define MDIO_PCS_CTRL2_10GBX		0x0001	/* 10GBASE-X type */
148 #define MDIO_PCS_CTRL2_10GBW		0x0002	/* 10GBASE-W type */
149 #define MDIO_PCS_CTRL2_10GBT		0x0003	/* 10GBASE-T type */
150 
151 /* Status register 2. */
152 #define MDIO_STAT2_RXFAULT		0x0400	/* Receive fault */
153 #define MDIO_STAT2_TXFAULT		0x0800	/* Transmit fault */
154 #define MDIO_STAT2_DEVPRST		0xc000	/* Device present */
155 #define MDIO_STAT2_DEVPRST_VAL		0x8000	/* Device present value */
156 #define MDIO_PMA_STAT2_LBABLE		0x0001	/* PMA loopback ability */
157 #define MDIO_PMA_STAT2_10GBEW		0x0002	/* 10GBASE-EW ability */
158 #define MDIO_PMA_STAT2_10GBLW		0x0004	/* 10GBASE-LW ability */
159 #define MDIO_PMA_STAT2_10GBSW		0x0008	/* 10GBASE-SW ability */
160 #define MDIO_PMA_STAT2_10GBLX4		0x0010	/* 10GBASE-LX4 ability */
161 #define MDIO_PMA_STAT2_10GBER		0x0020	/* 10GBASE-ER ability */
162 #define MDIO_PMA_STAT2_10GBLR		0x0040	/* 10GBASE-LR ability */
163 #define MDIO_PMA_STAT2_10GBSR		0x0080	/* 10GBASE-SR ability */
164 #define MDIO_PMD_STAT2_TXDISAB		0x0100	/* PMD TX disable ability */
165 #define MDIO_PMA_STAT2_EXTABLE		0x0200	/* Extended abilities */
166 #define MDIO_PMA_STAT2_RXFLTABLE	0x1000	/* Receive fault ability */
167 #define MDIO_PMA_STAT2_TXFLTABLE	0x2000	/* Transmit fault ability */
168 #define MDIO_PCS_STAT2_10GBR		0x0001	/* 10GBASE-R capable */
169 #define MDIO_PCS_STAT2_10GBX		0x0002	/* 10GBASE-X capable */
170 #define MDIO_PCS_STAT2_10GBW		0x0004	/* 10GBASE-W capable */
171 #define MDIO_PCS_STAT2_RXFLTABLE	0x1000	/* Receive fault ability */
172 #define MDIO_PCS_STAT2_TXFLTABLE	0x2000	/* Transmit fault ability */
173 
174 /* Transmit disable register. */
175 #define MDIO_PMD_TXDIS_GLOBAL		0x0001	/* Global PMD TX disable */
176 #define MDIO_PMD_TXDIS_0		0x0002	/* PMD TX disable 0 */
177 #define MDIO_PMD_TXDIS_1		0x0004	/* PMD TX disable 1 */
178 #define MDIO_PMD_TXDIS_2		0x0008	/* PMD TX disable 2 */
179 #define MDIO_PMD_TXDIS_3		0x0010	/* PMD TX disable 3 */
180 
181 /* Receive signal detect register. */
182 #define MDIO_PMD_RXDET_GLOBAL		0x0001	/* Global PMD RX signal detect */
183 #define MDIO_PMD_RXDET_0		0x0002	/* PMD RX signal detect 0 */
184 #define MDIO_PMD_RXDET_1		0x0004	/* PMD RX signal detect 1 */
185 #define MDIO_PMD_RXDET_2		0x0008	/* PMD RX signal detect 2 */
186 #define MDIO_PMD_RXDET_3		0x0010	/* PMD RX signal detect 3 */
187 
188 /* Extended abilities register. */
189 #define MDIO_PMA_EXTABLE_10GCX4		0x0001	/* 10GBASE-CX4 ability */
190 #define MDIO_PMA_EXTABLE_10GBLRM	0x0002	/* 10GBASE-LRM ability */
191 #define MDIO_PMA_EXTABLE_10GBT		0x0004	/* 10GBASE-T ability */
192 #define MDIO_PMA_EXTABLE_10GBKX4	0x0008	/* 10GBASE-KX4 ability */
193 #define MDIO_PMA_EXTABLE_10GBKR		0x0010	/* 10GBASE-KR ability */
194 #define MDIO_PMA_EXTABLE_1000BT		0x0020	/* 1000BASE-T ability */
195 #define MDIO_PMA_EXTABLE_1000BKX	0x0040	/* 1000BASE-KX ability */
196 #define MDIO_PMA_EXTABLE_100BTX		0x0080	/* 100BASE-TX ability */
197 #define MDIO_PMA_EXTABLE_10BT		0x0100	/* 10BASE-T ability */
198 
199 /* PHY XGXS lane state register. */
200 #define MDIO_PHYXS_LNSTAT_SYNC0		0x0001
201 #define MDIO_PHYXS_LNSTAT_SYNC1		0x0002
202 #define MDIO_PHYXS_LNSTAT_SYNC2		0x0004
203 #define MDIO_PHYXS_LNSTAT_SYNC3		0x0008
204 #define MDIO_PHYXS_LNSTAT_ALIGN		0x1000
205 
206 /* PMA 10GBASE-T pair swap & polarity */
207 #define MDIO_PMA_10GBT_SWAPPOL_ABNX	0x0001	/* Pair A/B uncrossed */
208 #define MDIO_PMA_10GBT_SWAPPOL_CDNX	0x0002	/* Pair C/D uncrossed */
209 #define MDIO_PMA_10GBT_SWAPPOL_AREV	0x0100	/* Pair A polarity reversed */
210 #define MDIO_PMA_10GBT_SWAPPOL_BREV	0x0200	/* Pair B polarity reversed */
211 #define MDIO_PMA_10GBT_SWAPPOL_CREV	0x0400	/* Pair C polarity reversed */
212 #define MDIO_PMA_10GBT_SWAPPOL_DREV	0x0800	/* Pair D polarity reversed */
213 
214 /* PMA 10GBASE-T TX power register. */
215 #define MDIO_PMA_10GBT_TXPWR_SHORT	0x0001	/* Short-reach mode */
216 
217 /* PMA 10GBASE-T SNR registers. */
218 /* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */
219 #define MDIO_PMA_10GBT_SNR_BIAS		0x8000
220 #define MDIO_PMA_10GBT_SNR_MAX		127
221 
222 /* PMA 10GBASE-R FEC ability register. */
223 #define MDIO_PMA_10GBR_FECABLE_ABLE	0x0001	/* FEC ability */
224 #define MDIO_PMA_10GBR_FECABLE_ERRABLE	0x0002	/* FEC error indic. ability */
225 
226 /* PCS 10GBASE-R/-T status register 1. */
227 #define MDIO_PCS_10GBRT_STAT1_BLKLK	0x0001	/* Block lock attained */
228 
229 /* PCS 10GBASE-R/-T status register 2. */
230 #define MDIO_PCS_10GBRT_STAT2_ERR	0x00ff
231 #define MDIO_PCS_10GBRT_STAT2_BER	0x3f00
232 
233 /* AN 10GBASE-T control register. */
234 #define MDIO_AN_10GBT_CTRL_ADV10G	0x1000	/* Advertise 10GBASE-T */
235 
236 /* AN 10GBASE-T status register. */
237 #define MDIO_AN_10GBT_STAT_LPTRR	0x0200	/* LP training reset req. */
238 #define MDIO_AN_10GBT_STAT_LPLTABLE	0x0400	/* LP loop timing ability */
239 #define MDIO_AN_10GBT_STAT_LP10G	0x0800	/* LP is 10GBT capable */
240 #define MDIO_AN_10GBT_STAT_REMOK	0x1000	/* Remote OK */
241 #define MDIO_AN_10GBT_STAT_LOCOK	0x2000	/* Local OK */
242 #define MDIO_AN_10GBT_STAT_MS		0x4000	/* Master/slave config */
243 #define MDIO_AN_10GBT_STAT_MSFLT	0x8000	/* Master/slave config fault */
244 
245 /* EEE Supported/Advertisement/LP Advertisement registers.
246  *
247  * EEE capability Register (3.20), Advertisement (7.60) and
248  * Link partner ability (7.61) registers have and can use the same identical
249  * bit masks.
250  */
251 #define MDIO_AN_EEE_ADV_100TX	0x0002	/* Advertise 100TX EEE cap */
252 #define MDIO_AN_EEE_ADV_1000T	0x0004	/* Advertise 1000T EEE cap */
253 /* Note: the two defines above can be potentially used by the user-land
254  * and cannot remove them now.
255  * So, we define the new generic MDIO_EEE_100TX and MDIO_EEE_1000T macros
256  * using the previous ones (that can be considered obsolete).
257  */
258 #define MDIO_EEE_100TX		MDIO_AN_EEE_ADV_100TX	/* 100TX EEE cap */
259 #define MDIO_EEE_1000T		MDIO_AN_EEE_ADV_1000T	/* 1000T EEE cap */
260 #define MDIO_EEE_10GT		0x0008	/* 10GT EEE cap */
261 #define MDIO_EEE_1000KX		0x0010	/* 1000KX EEE cap */
262 #define MDIO_EEE_10GKX4		0x0020	/* 10G KX4 EEE cap */
263 #define MDIO_EEE_10GKR		0x0040	/* 10G KR EEE cap */
264 
265 /* LASI RX_ALARM control/status registers. */
266 #define MDIO_PMA_LASI_RX_PHYXSLFLT	0x0001	/* PHY XS RX local fault */
267 #define MDIO_PMA_LASI_RX_PCSLFLT	0x0008	/* PCS RX local fault */
268 #define MDIO_PMA_LASI_RX_PMALFLT	0x0010	/* PMA/PMD RX local fault */
269 #define MDIO_PMA_LASI_RX_OPTICPOWERFLT	0x0020	/* RX optical power fault */
270 #define MDIO_PMA_LASI_RX_WISLFLT	0x0200	/* WIS local fault */
271 
272 /* LASI TX_ALARM control/status registers. */
273 #define MDIO_PMA_LASI_TX_PHYXSLFLT	0x0001	/* PHY XS TX local fault */
274 #define MDIO_PMA_LASI_TX_PCSLFLT	0x0008	/* PCS TX local fault */
275 #define MDIO_PMA_LASI_TX_PMALFLT	0x0010	/* PMA/PMD TX local fault */
276 #define MDIO_PMA_LASI_TX_LASERPOWERFLT	0x0080	/* Laser output power fault */
277 #define MDIO_PMA_LASI_TX_LASERTEMPFLT	0x0100	/* Laser temperature fault */
278 #define MDIO_PMA_LASI_TX_LASERBICURRFLT	0x0200	/* Laser bias current fault */
279 
280 /* LASI control/status registers. */
281 #define MDIO_PMA_LASI_LSALARM		0x0001	/* LS_ALARM enable/status */
282 #define MDIO_PMA_LASI_TXALARM		0x0002	/* TX_ALARM enable/status */
283 #define MDIO_PMA_LASI_RXALARM		0x0004	/* RX_ALARM enable/status */
284 
285 /* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */
286 
287 #define MDIO_PHY_ID_C45			0x8000
288 #define MDIO_PHY_ID_PRTAD		0x03e0
289 #define MDIO_PHY_ID_DEVAD		0x001f
290 #define MDIO_PHY_ID_C45_MASK						\
291 	(MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD)
292 
293 static inline __u16 mdio_phy_id_c45(int prtad, int devad)
294 {
295 	return MDIO_PHY_ID_C45 | (prtad << 5) | devad;
296 }
297 
298 #endif /* _UAPI__LINUX_MDIO_H__ */
299