1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the SelectionDAGISel class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/Analysis/EHPersonalities.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAGISel.h"
36 #include "llvm/CodeGen/StackProtector.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DebugInfo.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/InlineAsm.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/IntrinsicInst.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/IR/LLVMContext.h"
46 #include "llvm/IR/Module.h"
47 #include "llvm/MC/MCAsmInfo.h"
48 #include "llvm/Support/Compiler.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/Timer.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetIntrinsicInfo.h"
55 #include "llvm/Target/TargetLowering.h"
56 #include "llvm/Target/TargetMachine.h"
57 #include "llvm/Target/TargetOptions.h"
58 #include "llvm/Target/TargetRegisterInfo.h"
59 #include "llvm/Target/TargetSubtargetInfo.h"
60 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
61 #include <algorithm>
62
63 using namespace llvm;
64
65 #define DEBUG_TYPE "isel"
66
67 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
68 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
69 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
70 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
71 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
72 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
73 STATISTIC(NumFastIselFailLowerArguments,
74 "Number of entry blocks where fast isel failed to lower arguments");
75
76 #ifndef NDEBUG
77 static cl::opt<bool>
78 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
79 cl::desc("Enable extra verbose messages in the \"fast\" "
80 "instruction selector"));
81
82 // Terminators
83 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
84 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
85 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
86 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
87 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
88 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
89 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
90
91 // Standard binary operators...
92 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
93 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
94 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
95 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
96 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
97 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
98 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
99 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
100 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
101 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
102 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
103 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
104
105 // Logical operators...
106 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
107 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
108 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
109
110 // Memory instructions...
111 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
112 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
113 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
114 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
115 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
116 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
117 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
118
119 // Convert instructions...
120 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
121 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
122 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
123 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
124 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
125 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
126 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
127 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
128 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
129 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
130 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
131 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
132
133 // Other instructions...
134 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
135 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
136 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
137 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
138 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
139 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
140 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
141 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
142 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
143 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
144 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
145 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
146 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
147 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
148 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
149
150 // Intrinsic instructions...
151 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
152 STATISTIC(NumFastIselFailSAddWithOverflow,
153 "Fast isel fails on sadd.with.overflow");
154 STATISTIC(NumFastIselFailUAddWithOverflow,
155 "Fast isel fails on uadd.with.overflow");
156 STATISTIC(NumFastIselFailSSubWithOverflow,
157 "Fast isel fails on ssub.with.overflow");
158 STATISTIC(NumFastIselFailUSubWithOverflow,
159 "Fast isel fails on usub.with.overflow");
160 STATISTIC(NumFastIselFailSMulWithOverflow,
161 "Fast isel fails on smul.with.overflow");
162 STATISTIC(NumFastIselFailUMulWithOverflow,
163 "Fast isel fails on umul.with.overflow");
164 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
165 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
166 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
167 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
168 #endif
169
170 static cl::opt<bool>
171 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
172 cl::desc("Enable verbose messages in the \"fast\" "
173 "instruction selector"));
174 static cl::opt<int> EnableFastISelAbort(
175 "fast-isel-abort", cl::Hidden,
176 cl::desc("Enable abort calls when \"fast\" instruction selection "
177 "fails to lower an instruction: 0 disable the abort, 1 will "
178 "abort but for args, calls and terminators, 2 will also "
179 "abort for argument lowering, and 3 will never fallback "
180 "to SelectionDAG."));
181
182 static cl::opt<bool>
183 UseMBPI("use-mbpi",
184 cl::desc("use Machine Branch Probability Info"),
185 cl::init(true), cl::Hidden);
186
187 #ifndef NDEBUG
188 static cl::opt<std::string>
189 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
190 cl::desc("Only display the basic block whose name "
191 "matches this for all view-*-dags options"));
192 static cl::opt<bool>
193 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
194 cl::desc("Pop up a window to show dags before the first "
195 "dag combine pass"));
196 static cl::opt<bool>
197 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
198 cl::desc("Pop up a window to show dags before legalize types"));
199 static cl::opt<bool>
200 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
201 cl::desc("Pop up a window to show dags before legalize"));
202 static cl::opt<bool>
203 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
204 cl::desc("Pop up a window to show dags before the second "
205 "dag combine pass"));
206 static cl::opt<bool>
207 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
208 cl::desc("Pop up a window to show dags before the post legalize types"
209 " dag combine pass"));
210 static cl::opt<bool>
211 ViewISelDAGs("view-isel-dags", cl::Hidden,
212 cl::desc("Pop up a window to show isel dags as they are selected"));
213 static cl::opt<bool>
214 ViewSchedDAGs("view-sched-dags", cl::Hidden,
215 cl::desc("Pop up a window to show sched dags as they are processed"));
216 static cl::opt<bool>
217 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
218 cl::desc("Pop up a window to show SUnit dags after they are processed"));
219 #else
220 static const bool ViewDAGCombine1 = false,
221 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
222 ViewDAGCombine2 = false,
223 ViewDAGCombineLT = false,
224 ViewISelDAGs = false, ViewSchedDAGs = false,
225 ViewSUnitDAGs = false;
226 #endif
227
228 //===---------------------------------------------------------------------===//
229 ///
230 /// RegisterScheduler class - Track the registration of instruction schedulers.
231 ///
232 //===---------------------------------------------------------------------===//
233 MachinePassRegistry RegisterScheduler::Registry;
234
235 //===---------------------------------------------------------------------===//
236 ///
237 /// ISHeuristic command line option for instruction schedulers.
238 ///
239 //===---------------------------------------------------------------------===//
240 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
241 RegisterPassParser<RegisterScheduler> >
242 ISHeuristic("pre-RA-sched",
243 cl::init(&createDefaultScheduler), cl::Hidden,
244 cl::desc("Instruction schedulers available (before register"
245 " allocation):"));
246
247 static RegisterScheduler
248 defaultListDAGScheduler("default", "Best scheduler for the target",
249 createDefaultScheduler);
250
251 namespace llvm {
252 //===--------------------------------------------------------------------===//
253 /// \brief This class is used by SelectionDAGISel to temporarily override
254 /// the optimization level on a per-function basis.
255 class OptLevelChanger {
256 SelectionDAGISel &IS;
257 CodeGenOpt::Level SavedOptLevel;
258 bool SavedFastISel;
259
260 public:
OptLevelChanger(SelectionDAGISel & ISel,CodeGenOpt::Level NewOptLevel)261 OptLevelChanger(SelectionDAGISel &ISel,
262 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
263 SavedOptLevel = IS.OptLevel;
264 if (NewOptLevel == SavedOptLevel)
265 return;
266 IS.OptLevel = NewOptLevel;
267 IS.TM.setOptLevel(NewOptLevel);
268 DEBUG(dbgs() << "\nChanging optimization level for Function "
269 << IS.MF->getFunction()->getName() << "\n");
270 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
271 << " ; After: -O" << NewOptLevel << "\n");
272 SavedFastISel = IS.TM.Options.EnableFastISel;
273 if (NewOptLevel == CodeGenOpt::None) {
274 IS.TM.setFastISel(IS.TM.getO0WantsFastISel());
275 DEBUG(dbgs() << "\tFastISel is "
276 << (IS.TM.Options.EnableFastISel ? "enabled" : "disabled")
277 << "\n");
278 }
279 }
280
~OptLevelChanger()281 ~OptLevelChanger() {
282 if (IS.OptLevel == SavedOptLevel)
283 return;
284 DEBUG(dbgs() << "\nRestoring optimization level for Function "
285 << IS.MF->getFunction()->getName() << "\n");
286 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
287 << " ; After: -O" << SavedOptLevel << "\n");
288 IS.OptLevel = SavedOptLevel;
289 IS.TM.setOptLevel(SavedOptLevel);
290 IS.TM.setFastISel(SavedFastISel);
291 }
292 };
293
294 //===--------------------------------------------------------------------===//
295 /// createDefaultScheduler - This creates an instruction scheduler appropriate
296 /// for the target.
createDefaultScheduler(SelectionDAGISel * IS,CodeGenOpt::Level OptLevel)297 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
298 CodeGenOpt::Level OptLevel) {
299 const TargetLowering *TLI = IS->TLI;
300 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
301
302 // Try first to see if the Target has its own way of selecting a scheduler
303 if (auto *SchedulerCtor = ST.getDAGScheduler(OptLevel)) {
304 return SchedulerCtor(IS, OptLevel);
305 }
306
307 if (OptLevel == CodeGenOpt::None ||
308 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
309 TLI->getSchedulingPreference() == Sched::Source)
310 return createSourceListDAGScheduler(IS, OptLevel);
311 if (TLI->getSchedulingPreference() == Sched::RegPressure)
312 return createBURRListDAGScheduler(IS, OptLevel);
313 if (TLI->getSchedulingPreference() == Sched::Hybrid)
314 return createHybridListDAGScheduler(IS, OptLevel);
315 if (TLI->getSchedulingPreference() == Sched::VLIW)
316 return createVLIWDAGScheduler(IS, OptLevel);
317 assert(TLI->getSchedulingPreference() == Sched::ILP &&
318 "Unknown sched type!");
319 return createILPListDAGScheduler(IS, OptLevel);
320 }
321 } // end namespace llvm
322
323 // EmitInstrWithCustomInserter - This method should be implemented by targets
324 // that mark instructions with the 'usesCustomInserter' flag. These
325 // instructions are special in various ways, which require special support to
326 // insert. The specified MachineInstr is created but not inserted into any
327 // basic blocks, and this method is called to expand it into a sequence of
328 // instructions, potentially also creating new basic blocks and control flow.
329 // When new basic blocks are inserted and the edges from MBB to its successors
330 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
331 // DenseMap.
332 MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr & MI,MachineBasicBlock * MBB) const333 TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
334 MachineBasicBlock *MBB) const {
335 #ifndef NDEBUG
336 dbgs() << "If a target marks an instruction with "
337 "'usesCustomInserter', it must implement "
338 "TargetLowering::EmitInstrWithCustomInserter!";
339 #endif
340 llvm_unreachable(nullptr);
341 }
342
AdjustInstrPostInstrSelection(MachineInstr & MI,SDNode * Node) const343 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
344 SDNode *Node) const {
345 assert(!MI.hasPostISelHook() &&
346 "If a target marks an instruction with 'hasPostISelHook', "
347 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
348 }
349
350 //===----------------------------------------------------------------------===//
351 // SelectionDAGISel code
352 //===----------------------------------------------------------------------===//
353
SelectionDAGISel(TargetMachine & tm,CodeGenOpt::Level OL)354 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
355 CodeGenOpt::Level OL) :
356 MachineFunctionPass(ID), TM(tm),
357 FuncInfo(new FunctionLoweringInfo()),
358 CurDAG(new SelectionDAG(tm, OL)),
359 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
360 GFI(),
361 OptLevel(OL),
362 DAGSize(0) {
363 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
364 initializeBranchProbabilityInfoWrapperPassPass(
365 *PassRegistry::getPassRegistry());
366 initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
367 initializeTargetLibraryInfoWrapperPassPass(
368 *PassRegistry::getPassRegistry());
369 }
370
~SelectionDAGISel()371 SelectionDAGISel::~SelectionDAGISel() {
372 delete SDB;
373 delete CurDAG;
374 delete FuncInfo;
375 }
376
getAnalysisUsage(AnalysisUsage & AU) const377 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
378 AU.addRequired<AAResultsWrapperPass>();
379 AU.addRequired<GCModuleInfo>();
380 AU.addRequired<StackProtector>();
381 AU.addPreserved<StackProtector>();
382 AU.addPreserved<GCModuleInfo>();
383 AU.addRequired<TargetLibraryInfoWrapperPass>();
384 if (UseMBPI && OptLevel != CodeGenOpt::None)
385 AU.addRequired<BranchProbabilityInfoWrapperPass>();
386 MachineFunctionPass::getAnalysisUsage(AU);
387 }
388
389 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
390 /// may trap on it. In this case we have to split the edge so that the path
391 /// through the predecessor block that doesn't go to the phi block doesn't
392 /// execute the possibly trapping instruction.
393 ///
394 /// This is required for correctness, so it must be done at -O0.
395 ///
SplitCriticalSideEffectEdges(Function & Fn)396 static void SplitCriticalSideEffectEdges(Function &Fn) {
397 // Loop for blocks with phi nodes.
398 for (BasicBlock &BB : Fn) {
399 PHINode *PN = dyn_cast<PHINode>(BB.begin());
400 if (!PN) continue;
401
402 ReprocessBlock:
403 // For each block with a PHI node, check to see if any of the input values
404 // are potentially trapping constant expressions. Constant expressions are
405 // the only potentially trapping value that can occur as the argument to a
406 // PHI.
407 for (BasicBlock::iterator I = BB.begin(); (PN = dyn_cast<PHINode>(I)); ++I)
408 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
409 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
410 if (!CE || !CE->canTrap()) continue;
411
412 // The only case we have to worry about is when the edge is critical.
413 // Since this block has a PHI Node, we assume it has multiple input
414 // edges: check to see if the pred has multiple successors.
415 BasicBlock *Pred = PN->getIncomingBlock(i);
416 if (Pred->getTerminator()->getNumSuccessors() == 1)
417 continue;
418
419 // Okay, we have to split this edge.
420 SplitCriticalEdge(
421 Pred->getTerminator(), GetSuccessorNumber(Pred, &BB),
422 CriticalEdgeSplittingOptions().setMergeIdenticalEdges());
423 goto ReprocessBlock;
424 }
425 }
426 }
427
runOnMachineFunction(MachineFunction & mf)428 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
429 // Do some sanity-checking on the command-line options.
430 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
431 "-fast-isel-verbose requires -fast-isel");
432 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
433 "-fast-isel-abort > 0 requires -fast-isel");
434
435 const Function &Fn = *mf.getFunction();
436 MF = &mf;
437
438 // Reset the target options before resetting the optimization
439 // level below.
440 // FIXME: This is a horrible hack and should be processed via
441 // codegen looking at the optimization level explicitly when
442 // it wants to look at it.
443 TM.resetTargetOptions(Fn);
444 // Reset OptLevel to None for optnone functions.
445 CodeGenOpt::Level NewOptLevel = OptLevel;
446 if (OptLevel != CodeGenOpt::None && skipFunction(Fn))
447 NewOptLevel = CodeGenOpt::None;
448 OptLevelChanger OLC(*this, NewOptLevel);
449
450 TII = MF->getSubtarget().getInstrInfo();
451 TLI = MF->getSubtarget().getTargetLowering();
452 RegInfo = &MF->getRegInfo();
453 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
454 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
455 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
456
457 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
458
459 SplitCriticalSideEffectEdges(const_cast<Function &>(Fn));
460
461 CurDAG->init(*MF);
462 FuncInfo->set(Fn, *MF, CurDAG);
463
464 if (UseMBPI && OptLevel != CodeGenOpt::None)
465 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();
466 else
467 FuncInfo->BPI = nullptr;
468
469 SDB->init(GFI, *AA, LibInfo);
470
471 MF->setHasInlineAsm(false);
472
473 FuncInfo->SplitCSR = false;
474
475 // We split CSR if the target supports it for the given function
476 // and the function has only return exits.
477 if (OptLevel != CodeGenOpt::None && TLI->supportSplitCSR(MF)) {
478 FuncInfo->SplitCSR = true;
479
480 // Collect all the return blocks.
481 for (const BasicBlock &BB : Fn) {
482 if (!succ_empty(&BB))
483 continue;
484
485 const TerminatorInst *Term = BB.getTerminator();
486 if (isa<UnreachableInst>(Term) || isa<ReturnInst>(Term))
487 continue;
488
489 // Bail out if the exit block is not Return nor Unreachable.
490 FuncInfo->SplitCSR = false;
491 break;
492 }
493 }
494
495 MachineBasicBlock *EntryMBB = &MF->front();
496 if (FuncInfo->SplitCSR)
497 // This performs initialization so lowering for SplitCSR will be correct.
498 TLI->initializeSplitCSR(EntryMBB);
499
500 SelectAllBasicBlocks(Fn);
501
502 // If the first basic block in the function has live ins that need to be
503 // copied into vregs, emit the copies into the top of the block before
504 // emitting the code for the block.
505 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
506 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
507
508 // Insert copies in the entry block and the return blocks.
509 if (FuncInfo->SplitCSR) {
510 SmallVector<MachineBasicBlock*, 4> Returns;
511 // Collect all the return blocks.
512 for (MachineBasicBlock &MBB : mf) {
513 if (!MBB.succ_empty())
514 continue;
515
516 MachineBasicBlock::iterator Term = MBB.getFirstTerminator();
517 if (Term != MBB.end() && Term->isReturn()) {
518 Returns.push_back(&MBB);
519 continue;
520 }
521 }
522 TLI->insertCopiesSplitCSR(EntryMBB, Returns);
523 }
524
525 DenseMap<unsigned, unsigned> LiveInMap;
526 if (!FuncInfo->ArgDbgValues.empty())
527 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
528 E = RegInfo->livein_end(); LI != E; ++LI)
529 if (LI->second)
530 LiveInMap.insert(std::make_pair(LI->first, LI->second));
531
532 // Insert DBG_VALUE instructions for function arguments to the entry block.
533 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
534 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
535 bool hasFI = MI->getOperand(0).isFI();
536 unsigned Reg =
537 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
538 if (TargetRegisterInfo::isPhysicalRegister(Reg))
539 EntryMBB->insert(EntryMBB->begin(), MI);
540 else {
541 MachineInstr *Def = RegInfo->getVRegDef(Reg);
542 if (Def) {
543 MachineBasicBlock::iterator InsertPos = Def;
544 // FIXME: VR def may not be in entry block.
545 Def->getParent()->insert(std::next(InsertPos), MI);
546 } else
547 DEBUG(dbgs() << "Dropping debug info for dead vreg"
548 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
549 }
550
551 // If Reg is live-in then update debug info to track its copy in a vreg.
552 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
553 if (LDI != LiveInMap.end()) {
554 assert(!hasFI && "There's no handling of frame pointer updating here yet "
555 "- add if needed");
556 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
557 MachineBasicBlock::iterator InsertPos = Def;
558 const MDNode *Variable = MI->getDebugVariable();
559 const MDNode *Expr = MI->getDebugExpression();
560 DebugLoc DL = MI->getDebugLoc();
561 bool IsIndirect = MI->isIndirectDebugValue();
562 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
563 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
564 "Expected inlined-at fields to agree");
565 // Def is never a terminator here, so it is ok to increment InsertPos.
566 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE),
567 IsIndirect, LDI->second, Offset, Variable, Expr);
568
569 // If this vreg is directly copied into an exported register then
570 // that COPY instructions also need DBG_VALUE, if it is the only
571 // user of LDI->second.
572 MachineInstr *CopyUseMI = nullptr;
573 for (MachineRegisterInfo::use_instr_iterator
574 UI = RegInfo->use_instr_begin(LDI->second),
575 E = RegInfo->use_instr_end(); UI != E; ) {
576 MachineInstr *UseMI = &*(UI++);
577 if (UseMI->isDebugValue()) continue;
578 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
579 CopyUseMI = UseMI; continue;
580 }
581 // Otherwise this is another use or second copy use.
582 CopyUseMI = nullptr; break;
583 }
584 if (CopyUseMI) {
585 // Use MI's debug location, which describes where Variable was
586 // declared, rather than whatever is attached to CopyUseMI.
587 MachineInstr *NewMI =
588 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
589 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
590 MachineBasicBlock::iterator Pos = CopyUseMI;
591 EntryMBB->insertAfter(Pos, NewMI);
592 }
593 }
594 }
595
596 // Determine if there are any calls in this machine function.
597 MachineFrameInfo *MFI = MF->getFrameInfo();
598 for (const auto &MBB : *MF) {
599 if (MFI->hasCalls() && MF->hasInlineAsm())
600 break;
601
602 for (const auto &MI : MBB) {
603 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
604 if ((MCID.isCall() && !MCID.isReturn()) ||
605 MI.isStackAligningInlineAsm()) {
606 MFI->setHasCalls(true);
607 }
608 if (MI.isInlineAsm()) {
609 MF->setHasInlineAsm(true);
610 }
611 }
612 }
613
614 // Determine if there is a call to setjmp in the machine function.
615 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
616
617 // Replace forward-declared registers with the registers containing
618 // the desired value.
619 MachineRegisterInfo &MRI = MF->getRegInfo();
620 for (DenseMap<unsigned, unsigned>::iterator
621 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
622 I != E; ++I) {
623 unsigned From = I->first;
624 unsigned To = I->second;
625 // If To is also scheduled to be replaced, find what its ultimate
626 // replacement is.
627 for (;;) {
628 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
629 if (J == E) break;
630 To = J->second;
631 }
632 // Make sure the new register has a sufficiently constrained register class.
633 if (TargetRegisterInfo::isVirtualRegister(From) &&
634 TargetRegisterInfo::isVirtualRegister(To))
635 MRI.constrainRegClass(To, MRI.getRegClass(From));
636 // Replace it.
637
638
639 // Replacing one register with another won't touch the kill flags.
640 // We need to conservatively clear the kill flags as a kill on the old
641 // register might dominate existing uses of the new register.
642 if (!MRI.use_empty(To))
643 MRI.clearKillFlags(From);
644 MRI.replaceRegWith(From, To);
645 }
646
647 if (TLI->hasCopyImplyingStackAdjustment(MF))
648 MFI->setHasCopyImplyingStackAdjustment(true);
649
650 // Freeze the set of reserved registers now that MachineFrameInfo has been
651 // set up. All the information required by getReservedRegs() should be
652 // available now.
653 MRI.freezeReservedRegs(*MF);
654
655 // Release function-specific state. SDB and CurDAG are already cleared
656 // at this point.
657 FuncInfo->clear();
658
659 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
660 DEBUG(MF->print(dbgs()));
661
662 return true;
663 }
664
SelectBasicBlock(BasicBlock::const_iterator Begin,BasicBlock::const_iterator End,bool & HadTailCall)665 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
666 BasicBlock::const_iterator End,
667 bool &HadTailCall) {
668 // Lower the instructions. If a call is emitted as a tail call, cease emitting
669 // nodes for this block.
670 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
671 SDB->visit(*I);
672
673 // Make sure the root of the DAG is up-to-date.
674 CurDAG->setRoot(SDB->getControlRoot());
675 HadTailCall = SDB->HasTailCall;
676 SDB->clear();
677
678 // Final step, emit the lowered DAG as machine code.
679 CodeGenAndEmitDAG();
680 }
681
ComputeLiveOutVRegInfo()682 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
683 SmallPtrSet<SDNode*, 16> VisitedNodes;
684 SmallVector<SDNode*, 128> Worklist;
685
686 Worklist.push_back(CurDAG->getRoot().getNode());
687
688 APInt KnownZero;
689 APInt KnownOne;
690
691 do {
692 SDNode *N = Worklist.pop_back_val();
693
694 // If we've already seen this node, ignore it.
695 if (!VisitedNodes.insert(N).second)
696 continue;
697
698 // Otherwise, add all chain operands to the worklist.
699 for (const SDValue &Op : N->op_values())
700 if (Op.getValueType() == MVT::Other)
701 Worklist.push_back(Op.getNode());
702
703 // If this is a CopyToReg with a vreg dest, process it.
704 if (N->getOpcode() != ISD::CopyToReg)
705 continue;
706
707 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
708 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
709 continue;
710
711 // Ignore non-scalar or non-integer values.
712 SDValue Src = N->getOperand(2);
713 EVT SrcVT = Src.getValueType();
714 if (!SrcVT.isInteger() || SrcVT.isVector())
715 continue;
716
717 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
718 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
719 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
720 } while (!Worklist.empty());
721 }
722
CodeGenAndEmitDAG()723 void SelectionDAGISel::CodeGenAndEmitDAG() {
724 std::string GroupName;
725 if (TimePassesIsEnabled)
726 GroupName = "Instruction Selection and Scheduling";
727 std::string BlockName;
728 int BlockNumber = -1;
729 (void)BlockNumber;
730 bool MatchFilterBB = false; (void)MatchFilterBB;
731 #ifndef NDEBUG
732 MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
733 FilterDAGBasicBlockName ==
734 FuncInfo->MBB->getBasicBlock()->getName().str());
735 #endif
736 #ifdef NDEBUG
737 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
738 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
739 ViewSUnitDAGs)
740 #endif
741 {
742 BlockNumber = FuncInfo->MBB->getNumber();
743 BlockName =
744 (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
745 }
746 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
747 << " '" << BlockName << "'\n"; CurDAG->dump());
748
749 if (ViewDAGCombine1 && MatchFilterBB)
750 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
751
752 // Run the DAG combiner in pre-legalize mode.
753 {
754 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
755 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
756 }
757
758 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
759 << " '" << BlockName << "'\n"; CurDAG->dump());
760
761 // Second step, hack on the DAG until it only uses operations and types that
762 // the target supports.
763 if (ViewLegalizeTypesDAGs && MatchFilterBB)
764 CurDAG->viewGraph("legalize-types input for " + BlockName);
765
766 bool Changed;
767 {
768 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
769 Changed = CurDAG->LegalizeTypes();
770 }
771
772 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
773 << " '" << BlockName << "'\n"; CurDAG->dump());
774
775 CurDAG->NewNodesMustHaveLegalTypes = true;
776
777 if (Changed) {
778 if (ViewDAGCombineLT && MatchFilterBB)
779 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
780
781 // Run the DAG combiner in post-type-legalize mode.
782 {
783 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
784 TimePassesIsEnabled);
785 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
786 }
787
788 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
789 << " '" << BlockName << "'\n"; CurDAG->dump());
790
791 }
792
793 {
794 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
795 Changed = CurDAG->LegalizeVectors();
796 }
797
798 if (Changed) {
799 {
800 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
801 CurDAG->LegalizeTypes();
802 }
803
804 if (ViewDAGCombineLT && MatchFilterBB)
805 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
806
807 // Run the DAG combiner in post-type-legalize mode.
808 {
809 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
810 TimePassesIsEnabled);
811 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
812 }
813
814 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
815 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
816 }
817
818 if (ViewLegalizeDAGs && MatchFilterBB)
819 CurDAG->viewGraph("legalize input for " + BlockName);
820
821 {
822 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
823 CurDAG->Legalize();
824 }
825
826 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
827 << " '" << BlockName << "'\n"; CurDAG->dump());
828
829 if (ViewDAGCombine2 && MatchFilterBB)
830 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
831
832 // Run the DAG combiner in post-legalize mode.
833 {
834 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
835 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
836 }
837
838 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
839 << " '" << BlockName << "'\n"; CurDAG->dump());
840
841 if (OptLevel != CodeGenOpt::None)
842 ComputeLiveOutVRegInfo();
843
844 if (ViewISelDAGs && MatchFilterBB)
845 CurDAG->viewGraph("isel input for " + BlockName);
846
847 // Third, instruction select all of the operations to machine code, adding the
848 // code to the MachineBasicBlock.
849 {
850 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
851 DoInstructionSelection();
852 }
853
854 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
855 << " '" << BlockName << "'\n"; CurDAG->dump());
856
857 if (ViewSchedDAGs && MatchFilterBB)
858 CurDAG->viewGraph("scheduler input for " + BlockName);
859
860 // Schedule machine code.
861 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
862 {
863 NamedRegionTimer T("Instruction Scheduling", GroupName,
864 TimePassesIsEnabled);
865 Scheduler->Run(CurDAG, FuncInfo->MBB);
866 }
867
868 if (ViewSUnitDAGs && MatchFilterBB)
869 Scheduler->viewGraph();
870
871 // Emit machine code to BB. This can change 'BB' to the last block being
872 // inserted into.
873 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
874 {
875 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
876
877 // FuncInfo->InsertPt is passed by reference and set to the end of the
878 // scheduled instructions.
879 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
880 }
881
882 // If the block was split, make sure we update any references that are used to
883 // update PHI nodes later on.
884 if (FirstMBB != LastMBB)
885 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
886
887 // Free the scheduler state.
888 {
889 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
890 TimePassesIsEnabled);
891 delete Scheduler;
892 }
893
894 // Free the SelectionDAG state, now that we're finished with it.
895 CurDAG->clear();
896 }
897
898 namespace {
899 /// ISelUpdater - helper class to handle updates of the instruction selection
900 /// graph.
901 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
902 SelectionDAG::allnodes_iterator &ISelPosition;
903 public:
ISelUpdater(SelectionDAG & DAG,SelectionDAG::allnodes_iterator & isp)904 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
905 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
906
907 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
908 /// deleted is the current ISelPosition node, update ISelPosition.
909 ///
NodeDeleted(SDNode * N,SDNode * E)910 void NodeDeleted(SDNode *N, SDNode *E) override {
911 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
912 ++ISelPosition;
913 }
914 };
915 } // end anonymous namespace
916
DoInstructionSelection()917 void SelectionDAGISel::DoInstructionSelection() {
918 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
919 << FuncInfo->MBB->getNumber()
920 << " '" << FuncInfo->MBB->getName() << "'\n");
921
922 PreprocessISelDAG();
923
924 // Select target instructions for the DAG.
925 {
926 // Number all nodes with a topological order and set DAGSize.
927 DAGSize = CurDAG->AssignTopologicalOrder();
928
929 // Create a dummy node (which is not added to allnodes), that adds
930 // a reference to the root node, preventing it from being deleted,
931 // and tracking any changes of the root.
932 HandleSDNode Dummy(CurDAG->getRoot());
933 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
934 ++ISelPosition;
935
936 // Make sure that ISelPosition gets properly updated when nodes are deleted
937 // in calls made from this function.
938 ISelUpdater ISU(*CurDAG, ISelPosition);
939
940 // The AllNodes list is now topological-sorted. Visit the
941 // nodes by starting at the end of the list (the root of the
942 // graph) and preceding back toward the beginning (the entry
943 // node).
944 while (ISelPosition != CurDAG->allnodes_begin()) {
945 SDNode *Node = &*--ISelPosition;
946 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
947 // but there are currently some corner cases that it misses. Also, this
948 // makes it theoretically possible to disable the DAGCombiner.
949 if (Node->use_empty())
950 continue;
951
952 Select(Node);
953 }
954
955 CurDAG->setRoot(Dummy.getValue());
956 }
957
958 DEBUG(dbgs() << "===== Instruction selection ends:\n");
959
960 PostprocessISelDAG();
961 }
962
hasExceptionPointerOrCodeUser(const CatchPadInst * CPI)963 static bool hasExceptionPointerOrCodeUser(const CatchPadInst *CPI) {
964 for (const User *U : CPI->users()) {
965 if (const IntrinsicInst *EHPtrCall = dyn_cast<IntrinsicInst>(U)) {
966 Intrinsic::ID IID = EHPtrCall->getIntrinsicID();
967 if (IID == Intrinsic::eh_exceptionpointer ||
968 IID == Intrinsic::eh_exceptioncode)
969 return true;
970 }
971 }
972 return false;
973 }
974
975 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
976 /// do other setup for EH landing-pad blocks.
PrepareEHLandingPad()977 bool SelectionDAGISel::PrepareEHLandingPad() {
978 MachineBasicBlock *MBB = FuncInfo->MBB;
979 const Constant *PersonalityFn = FuncInfo->Fn->getPersonalityFn();
980 const BasicBlock *LLVMBB = MBB->getBasicBlock();
981 const TargetRegisterClass *PtrRC =
982 TLI->getRegClassFor(TLI->getPointerTy(CurDAG->getDataLayout()));
983
984 // Catchpads have one live-in register, which typically holds the exception
985 // pointer or code.
986 if (const auto *CPI = dyn_cast<CatchPadInst>(LLVMBB->getFirstNonPHI())) {
987 if (hasExceptionPointerOrCodeUser(CPI)) {
988 // Get or create the virtual register to hold the pointer or code. Mark
989 // the live in physreg and copy into the vreg.
990 MCPhysReg EHPhysReg = TLI->getExceptionPointerRegister(PersonalityFn);
991 assert(EHPhysReg && "target lacks exception pointer register");
992 MBB->addLiveIn(EHPhysReg);
993 unsigned VReg = FuncInfo->getCatchPadExceptionPointerVReg(CPI, PtrRC);
994 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(),
995 TII->get(TargetOpcode::COPY), VReg)
996 .addReg(EHPhysReg, RegState::Kill);
997 }
998 return true;
999 }
1000
1001 if (!LLVMBB->isLandingPad())
1002 return true;
1003
1004 // Add a label to mark the beginning of the landing pad. Deletion of the
1005 // landing pad can thus be detected via the MachineModuleInfo.
1006 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
1007
1008 // Assign the call site to the landing pad's begin label.
1009 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
1010
1011 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
1012 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
1013 .addSym(Label);
1014
1015 // Mark exception register as live in.
1016 if (unsigned Reg = TLI->getExceptionPointerRegister(PersonalityFn))
1017 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
1018
1019 // Mark exception selector register as live in.
1020 if (unsigned Reg = TLI->getExceptionSelectorRegister(PersonalityFn))
1021 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
1022
1023 return true;
1024 }
1025
1026 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
1027 /// side-effect free and is either dead or folded into a generated instruction.
1028 /// Return false if it needs to be emitted.
isFoldedOrDeadInstruction(const Instruction * I,FunctionLoweringInfo * FuncInfo)1029 static bool isFoldedOrDeadInstruction(const Instruction *I,
1030 FunctionLoweringInfo *FuncInfo) {
1031 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
1032 !isa<TerminatorInst>(I) && // Terminators aren't folded.
1033 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
1034 !I->isEHPad() && // EH pad instructions aren't folded.
1035 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
1036 }
1037
1038 #ifndef NDEBUG
1039 // Collect per Instruction statistics for fast-isel misses. Only those
1040 // instructions that cause the bail are accounted for. It does not account for
1041 // instructions higher in the block. Thus, summing the per instructions stats
1042 // will not add up to what is reported by NumFastIselFailures.
collectFailStats(const Instruction * I)1043 static void collectFailStats(const Instruction *I) {
1044 switch (I->getOpcode()) {
1045 default: assert (0 && "<Invalid operator> ");
1046
1047 // Terminators
1048 case Instruction::Ret: NumFastIselFailRet++; return;
1049 case Instruction::Br: NumFastIselFailBr++; return;
1050 case Instruction::Switch: NumFastIselFailSwitch++; return;
1051 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1052 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1053 case Instruction::Resume: NumFastIselFailResume++; return;
1054 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1055
1056 // Standard binary operators...
1057 case Instruction::Add: NumFastIselFailAdd++; return;
1058 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1059 case Instruction::Sub: NumFastIselFailSub++; return;
1060 case Instruction::FSub: NumFastIselFailFSub++; return;
1061 case Instruction::Mul: NumFastIselFailMul++; return;
1062 case Instruction::FMul: NumFastIselFailFMul++; return;
1063 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1064 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1065 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1066 case Instruction::URem: NumFastIselFailURem++; return;
1067 case Instruction::SRem: NumFastIselFailSRem++; return;
1068 case Instruction::FRem: NumFastIselFailFRem++; return;
1069
1070 // Logical operators...
1071 case Instruction::And: NumFastIselFailAnd++; return;
1072 case Instruction::Or: NumFastIselFailOr++; return;
1073 case Instruction::Xor: NumFastIselFailXor++; return;
1074
1075 // Memory instructions...
1076 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1077 case Instruction::Load: NumFastIselFailLoad++; return;
1078 case Instruction::Store: NumFastIselFailStore++; return;
1079 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1080 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1081 case Instruction::Fence: NumFastIselFailFence++; return;
1082 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1083
1084 // Convert instructions...
1085 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1086 case Instruction::ZExt: NumFastIselFailZExt++; return;
1087 case Instruction::SExt: NumFastIselFailSExt++; return;
1088 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1089 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1090 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1091 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1092 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1093 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1094 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1095 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1096 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1097
1098 // Other instructions...
1099 case Instruction::ICmp: NumFastIselFailICmp++; return;
1100 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1101 case Instruction::PHI: NumFastIselFailPHI++; return;
1102 case Instruction::Select: NumFastIselFailSelect++; return;
1103 case Instruction::Call: {
1104 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1105 switch (Intrinsic->getIntrinsicID()) {
1106 default:
1107 NumFastIselFailIntrinsicCall++; return;
1108 case Intrinsic::sadd_with_overflow:
1109 NumFastIselFailSAddWithOverflow++; return;
1110 case Intrinsic::uadd_with_overflow:
1111 NumFastIselFailUAddWithOverflow++; return;
1112 case Intrinsic::ssub_with_overflow:
1113 NumFastIselFailSSubWithOverflow++; return;
1114 case Intrinsic::usub_with_overflow:
1115 NumFastIselFailUSubWithOverflow++; return;
1116 case Intrinsic::smul_with_overflow:
1117 NumFastIselFailSMulWithOverflow++; return;
1118 case Intrinsic::umul_with_overflow:
1119 NumFastIselFailUMulWithOverflow++; return;
1120 case Intrinsic::frameaddress:
1121 NumFastIselFailFrameaddress++; return;
1122 case Intrinsic::sqrt:
1123 NumFastIselFailSqrt++; return;
1124 case Intrinsic::experimental_stackmap:
1125 NumFastIselFailStackMap++; return;
1126 case Intrinsic::experimental_patchpoint_void: // fall-through
1127 case Intrinsic::experimental_patchpoint_i64:
1128 NumFastIselFailPatchPoint++; return;
1129 }
1130 }
1131 NumFastIselFailCall++;
1132 return;
1133 }
1134 case Instruction::Shl: NumFastIselFailShl++; return;
1135 case Instruction::LShr: NumFastIselFailLShr++; return;
1136 case Instruction::AShr: NumFastIselFailAShr++; return;
1137 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1138 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1139 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1140 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1141 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1142 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1143 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1144 }
1145 }
1146 #endif // NDEBUG
1147
1148 /// Set up SwiftErrorVals by going through the function. If the function has
1149 /// swifterror argument, it will be the first entry.
setupSwiftErrorVals(const Function & Fn,const TargetLowering * TLI,FunctionLoweringInfo * FuncInfo)1150 static void setupSwiftErrorVals(const Function &Fn, const TargetLowering *TLI,
1151 FunctionLoweringInfo *FuncInfo) {
1152 if (!TLI->supportSwiftError())
1153 return;
1154
1155 FuncInfo->SwiftErrorVals.clear();
1156 FuncInfo->SwiftErrorMap.clear();
1157 FuncInfo->SwiftErrorWorklist.clear();
1158
1159 // Check if function has a swifterror argument.
1160 for (Function::const_arg_iterator AI = Fn.arg_begin(), AE = Fn.arg_end();
1161 AI != AE; ++AI)
1162 if (AI->hasSwiftErrorAttr())
1163 FuncInfo->SwiftErrorVals.push_back(&*AI);
1164
1165 for (const auto &LLVMBB : Fn)
1166 for (const auto &Inst : LLVMBB) {
1167 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(&Inst))
1168 if (Alloca->isSwiftError())
1169 FuncInfo->SwiftErrorVals.push_back(Alloca);
1170 }
1171 }
1172
1173 /// For each basic block, merge incoming swifterror values or simply propagate
1174 /// them. The merged results will be saved in SwiftErrorMap. For predecessors
1175 /// that are not yet visited, we create virtual registers to hold the swifterror
1176 /// values and save them in SwiftErrorWorklist.
mergeIncomingSwiftErrors(FunctionLoweringInfo * FuncInfo,const TargetLowering * TLI,const TargetInstrInfo * TII,const BasicBlock * LLVMBB,SelectionDAGBuilder * SDB)1177 static void mergeIncomingSwiftErrors(FunctionLoweringInfo *FuncInfo,
1178 const TargetLowering *TLI,
1179 const TargetInstrInfo *TII,
1180 const BasicBlock *LLVMBB,
1181 SelectionDAGBuilder *SDB) {
1182 if (!TLI->supportSwiftError())
1183 return;
1184
1185 // We should only do this when we have swifterror parameter or swifterror
1186 // alloc.
1187 if (FuncInfo->SwiftErrorVals.empty())
1188 return;
1189
1190 // At beginning of a basic block, insert PHI nodes or get the virtual
1191 // register from the only predecessor, and update SwiftErrorMap; if one
1192 // of the predecessors is not visited, update SwiftErrorWorklist.
1193 // At end of a basic block, if a block is in SwiftErrorWorklist, insert copy
1194 // to sync up the virtual register assignment.
1195
1196 // Always create a virtual register for each swifterror value in entry block.
1197 auto &DL = SDB->DAG.getDataLayout();
1198 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
1199 if (pred_begin(LLVMBB) == pred_end(LLVMBB)) {
1200 for (unsigned I = 0, E = FuncInfo->SwiftErrorVals.size(); I < E; I++) {
1201 unsigned VReg = FuncInfo->MF->getRegInfo().createVirtualRegister(RC);
1202 // Assign Undef to Vreg. We construct MI directly to make sure it works
1203 // with FastISel.
1204 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(),
1205 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
1206 FuncInfo->SwiftErrorMap[FuncInfo->MBB].push_back(VReg);
1207 }
1208 return;
1209 }
1210
1211 if (auto *UniquePred = LLVMBB->getUniquePredecessor()) {
1212 auto *UniquePredMBB = FuncInfo->MBBMap[UniquePred];
1213 if (!FuncInfo->SwiftErrorMap.count(UniquePredMBB)) {
1214 // Update SwiftErrorWorklist with a new virtual register.
1215 for (unsigned I = 0, E = FuncInfo->SwiftErrorVals.size(); I < E; I++) {
1216 unsigned VReg = FuncInfo->MF->getRegInfo().createVirtualRegister(RC);
1217 FuncInfo->SwiftErrorWorklist[UniquePredMBB].push_back(VReg);
1218 // Propagate the information from the single predecessor.
1219 FuncInfo->SwiftErrorMap[FuncInfo->MBB].push_back(VReg);
1220 }
1221 return;
1222 }
1223 // Propagate the information from the single predecessor.
1224 FuncInfo->SwiftErrorMap[FuncInfo->MBB] =
1225 FuncInfo->SwiftErrorMap[UniquePredMBB];
1226 return;
1227 }
1228
1229 // For the case of multiple predecessors, update SwiftErrorWorklist.
1230 // Handle the case where we have two or more predecessors being the same.
1231 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1232 PI != PE; ++PI) {
1233 auto *PredMBB = FuncInfo->MBBMap[*PI];
1234 if (!FuncInfo->SwiftErrorMap.count(PredMBB) &&
1235 !FuncInfo->SwiftErrorWorklist.count(PredMBB)) {
1236 for (unsigned I = 0, E = FuncInfo->SwiftErrorVals.size(); I < E; I++) {
1237 unsigned VReg = FuncInfo->MF->getRegInfo().createVirtualRegister(RC);
1238 // When we actually visit the basic block PredMBB, we will materialize
1239 // the virtual register assignment in copySwiftErrorsToFinalVRegs.
1240 FuncInfo->SwiftErrorWorklist[PredMBB].push_back(VReg);
1241 }
1242 }
1243 }
1244
1245 // For the case of multiple predecessors, create a virtual register for
1246 // each swifterror value and generate Phi node.
1247 for (unsigned I = 0, E = FuncInfo->SwiftErrorVals.size(); I < E; I++) {
1248 unsigned VReg = FuncInfo->MF->getRegInfo().createVirtualRegister(RC);
1249 FuncInfo->SwiftErrorMap[FuncInfo->MBB].push_back(VReg);
1250
1251 MachineInstrBuilder SwiftErrorPHI = BuildMI(*FuncInfo->MBB,
1252 FuncInfo->MBB->begin(), SDB->getCurDebugLoc(),
1253 TII->get(TargetOpcode::PHI), VReg);
1254 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1255 PI != PE; ++PI) {
1256 auto *PredMBB = FuncInfo->MBBMap[*PI];
1257 unsigned SwiftErrorReg = FuncInfo->SwiftErrorMap.count(PredMBB) ?
1258 FuncInfo->SwiftErrorMap[PredMBB][I] :
1259 FuncInfo->SwiftErrorWorklist[PredMBB][I];
1260 SwiftErrorPHI.addReg(SwiftErrorReg)
1261 .addMBB(PredMBB);
1262 }
1263 }
1264 }
1265
SelectAllBasicBlocks(const Function & Fn)1266 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1267 // Initialize the Fast-ISel state, if needed.
1268 FastISel *FastIS = nullptr;
1269 if (TM.Options.EnableFastISel)
1270 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1271
1272 setupSwiftErrorVals(Fn, TLI, FuncInfo);
1273
1274 // Iterate over all basic blocks in the function.
1275 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1276 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1277 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1278 const BasicBlock *LLVMBB = *I;
1279
1280 if (OptLevel != CodeGenOpt::None) {
1281 bool AllPredsVisited = true;
1282 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1283 PI != PE; ++PI) {
1284 if (!FuncInfo->VisitedBBs.count(*PI)) {
1285 AllPredsVisited = false;
1286 break;
1287 }
1288 }
1289
1290 if (AllPredsVisited) {
1291 for (BasicBlock::const_iterator I = LLVMBB->begin();
1292 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1293 FuncInfo->ComputePHILiveOutRegInfo(PN);
1294 } else {
1295 for (BasicBlock::const_iterator I = LLVMBB->begin();
1296 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1297 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1298 }
1299
1300 FuncInfo->VisitedBBs.insert(LLVMBB);
1301 }
1302
1303 BasicBlock::const_iterator const Begin =
1304 LLVMBB->getFirstNonPHI()->getIterator();
1305 BasicBlock::const_iterator const End = LLVMBB->end();
1306 BasicBlock::const_iterator BI = End;
1307
1308 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1309 if (!FuncInfo->MBB)
1310 continue; // Some blocks like catchpads have no code or MBB.
1311 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1312 mergeIncomingSwiftErrors(FuncInfo, TLI, TII, LLVMBB, SDB);
1313
1314 // Setup an EH landing-pad block.
1315 FuncInfo->ExceptionPointerVirtReg = 0;
1316 FuncInfo->ExceptionSelectorVirtReg = 0;
1317 if (LLVMBB->isEHPad())
1318 if (!PrepareEHLandingPad())
1319 continue;
1320
1321 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1322 if (FastIS) {
1323 FastIS->startNewBlock();
1324
1325 // Emit code for any incoming arguments. This must happen before
1326 // beginning FastISel on the entry block.
1327 if (LLVMBB == &Fn.getEntryBlock()) {
1328 ++NumEntryBlocks;
1329
1330 // Lower any arguments needed in this block if this is the entry block.
1331 if (!FastIS->lowerArguments()) {
1332 // Fast isel failed to lower these arguments
1333 ++NumFastIselFailLowerArguments;
1334 if (EnableFastISelAbort > 1)
1335 report_fatal_error("FastISel didn't lower all arguments");
1336
1337 // Use SelectionDAG argument lowering
1338 LowerArguments(Fn);
1339 CurDAG->setRoot(SDB->getControlRoot());
1340 SDB->clear();
1341 CodeGenAndEmitDAG();
1342 }
1343
1344 // If we inserted any instructions at the beginning, make a note of
1345 // where they are, so we can be sure to emit subsequent instructions
1346 // after them.
1347 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1348 FastIS->setLastLocalValue(&*std::prev(FuncInfo->InsertPt));
1349 else
1350 FastIS->setLastLocalValue(nullptr);
1351 }
1352
1353 unsigned NumFastIselRemaining = std::distance(Begin, End);
1354 // Do FastISel on as many instructions as possible.
1355 for (; BI != Begin; --BI) {
1356 const Instruction *Inst = &*std::prev(BI);
1357
1358 // If we no longer require this instruction, skip it.
1359 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1360 --NumFastIselRemaining;
1361 continue;
1362 }
1363
1364 // Bottom-up: reset the insert pos at the top, after any local-value
1365 // instructions.
1366 FastIS->recomputeInsertPt();
1367
1368 // Try to select the instruction with FastISel.
1369 if (FastIS->selectInstruction(Inst)) {
1370 --NumFastIselRemaining;
1371 ++NumFastIselSuccess;
1372 // If fast isel succeeded, skip over all the folded instructions, and
1373 // then see if there is a load right before the selected instructions.
1374 // Try to fold the load if so.
1375 const Instruction *BeforeInst = Inst;
1376 while (BeforeInst != &*Begin) {
1377 BeforeInst = &*std::prev(BasicBlock::const_iterator(BeforeInst));
1378 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1379 break;
1380 }
1381 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1382 BeforeInst->hasOneUse() &&
1383 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1384 // If we succeeded, don't re-select the load.
1385 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1386 --NumFastIselRemaining;
1387 ++NumFastIselSuccess;
1388 }
1389 continue;
1390 }
1391
1392 #ifndef NDEBUG
1393 if (EnableFastISelVerbose2)
1394 collectFailStats(Inst);
1395 #endif
1396
1397 // Then handle certain instructions as single-LLVM-Instruction blocks.
1398 if (isa<CallInst>(Inst)) {
1399
1400 if (EnableFastISelVerbose || EnableFastISelAbort) {
1401 dbgs() << "FastISel missed call: ";
1402 Inst->dump();
1403 }
1404 if (EnableFastISelAbort > 2)
1405 // FastISel selector couldn't handle something and bailed.
1406 // For the purpose of debugging, just abort.
1407 report_fatal_error("FastISel didn't select the entire block");
1408
1409 if (!Inst->getType()->isVoidTy() && !Inst->getType()->isTokenTy() &&
1410 !Inst->use_empty()) {
1411 unsigned &R = FuncInfo->ValueMap[Inst];
1412 if (!R)
1413 R = FuncInfo->CreateRegs(Inst->getType());
1414 }
1415
1416 bool HadTailCall = false;
1417 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1418 SelectBasicBlock(Inst->getIterator(), BI, HadTailCall);
1419
1420 // If the call was emitted as a tail call, we're done with the block.
1421 // We also need to delete any previously emitted instructions.
1422 if (HadTailCall) {
1423 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1424 --BI;
1425 break;
1426 }
1427
1428 // Recompute NumFastIselRemaining as Selection DAG instruction
1429 // selection may have handled the call, input args, etc.
1430 unsigned RemainingNow = std::distance(Begin, BI);
1431 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1432 NumFastIselRemaining = RemainingNow;
1433 continue;
1434 }
1435
1436 bool ShouldAbort = EnableFastISelAbort;
1437 if (EnableFastISelVerbose || EnableFastISelAbort) {
1438 if (isa<TerminatorInst>(Inst)) {
1439 // Use a different message for terminator misses.
1440 dbgs() << "FastISel missed terminator: ";
1441 // Don't abort unless for terminator unless the level is really high
1442 ShouldAbort = (EnableFastISelAbort > 2);
1443 } else {
1444 dbgs() << "FastISel miss: ";
1445 }
1446 Inst->dump();
1447 }
1448 if (ShouldAbort)
1449 // FastISel selector couldn't handle something and bailed.
1450 // For the purpose of debugging, just abort.
1451 report_fatal_error("FastISel didn't select the entire block");
1452
1453 NumFastIselFailures += NumFastIselRemaining;
1454 break;
1455 }
1456
1457 FastIS->recomputeInsertPt();
1458 } else {
1459 // Lower any arguments needed in this block if this is the entry block.
1460 if (LLVMBB == &Fn.getEntryBlock()) {
1461 ++NumEntryBlocks;
1462 LowerArguments(Fn);
1463 }
1464 }
1465 if (getAnalysis<StackProtector>().shouldEmitSDCheck(*LLVMBB)) {
1466 bool FunctionBasedInstrumentation =
1467 TLI->getSSPStackGuardCheck(*Fn.getParent());
1468 SDB->SPDescriptor.initialize(LLVMBB, FuncInfo->MBBMap[LLVMBB],
1469 FunctionBasedInstrumentation);
1470 }
1471
1472 if (Begin != BI)
1473 ++NumDAGBlocks;
1474 else
1475 ++NumFastIselBlocks;
1476
1477 if (Begin != BI) {
1478 // Run SelectionDAG instruction selection on the remainder of the block
1479 // not handled by FastISel. If FastISel is not run, this is the entire
1480 // block.
1481 bool HadTailCall;
1482 SelectBasicBlock(Begin, BI, HadTailCall);
1483 }
1484
1485 FinishBasicBlock();
1486 FuncInfo->PHINodesToUpdate.clear();
1487 }
1488
1489 delete FastIS;
1490 SDB->clearDanglingDebugInfo();
1491 SDB->SPDescriptor.resetPerFunctionState();
1492 }
1493
1494 /// Given that the input MI is before a partial terminator sequence TSeq, return
1495 /// true if M + TSeq also a partial terminator sequence.
1496 ///
1497 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1498 /// lowering copy vregs into physical registers, which are then passed into
1499 /// terminator instructors so we can satisfy ABI constraints. A partial
1500 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1501 /// may be the whole terminator sequence).
MIIsInTerminatorSequence(const MachineInstr & MI)1502 static bool MIIsInTerminatorSequence(const MachineInstr &MI) {
1503 // If we do not have a copy or an implicit def, we return true if and only if
1504 // MI is a debug value.
1505 if (!MI.isCopy() && !MI.isImplicitDef())
1506 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1507 // physical registers if there is debug info associated with the terminator
1508 // of our mbb. We want to include said debug info in our terminator
1509 // sequence, so we return true in that case.
1510 return MI.isDebugValue();
1511
1512 // We have left the terminator sequence if we are not doing one of the
1513 // following:
1514 //
1515 // 1. Copying a vreg into a physical register.
1516 // 2. Copying a vreg into a vreg.
1517 // 3. Defining a register via an implicit def.
1518
1519 // OPI should always be a register definition...
1520 MachineInstr::const_mop_iterator OPI = MI.operands_begin();
1521 if (!OPI->isReg() || !OPI->isDef())
1522 return false;
1523
1524 // Defining any register via an implicit def is always ok.
1525 if (MI.isImplicitDef())
1526 return true;
1527
1528 // Grab the copy source...
1529 MachineInstr::const_mop_iterator OPI2 = OPI;
1530 ++OPI2;
1531 assert(OPI2 != MI.operands_end()
1532 && "Should have a copy implying we should have 2 arguments.");
1533
1534 // Make sure that the copy dest is not a vreg when the copy source is a
1535 // physical register.
1536 if (!OPI2->isReg() ||
1537 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1538 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1539 return false;
1540
1541 return true;
1542 }
1543
1544 /// Find the split point at which to splice the end of BB into its success stack
1545 /// protector check machine basic block.
1546 ///
1547 /// On many platforms, due to ABI constraints, terminators, even before register
1548 /// allocation, use physical registers. This creates an issue for us since
1549 /// physical registers at this point can not travel across basic
1550 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1551 /// when they enter functions and moves them through a sequence of copies back
1552 /// into the physical registers right before the terminator creating a
1553 /// ``Terminator Sequence''. This function is searching for the beginning of the
1554 /// terminator sequence so that we can ensure that we splice off not just the
1555 /// terminator, but additionally the copies that move the vregs into the
1556 /// physical registers.
1557 static MachineBasicBlock::iterator
FindSplitPointForStackProtector(MachineBasicBlock * BB)1558 FindSplitPointForStackProtector(MachineBasicBlock *BB) {
1559 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1560 //
1561 if (SplitPoint == BB->begin())
1562 return SplitPoint;
1563
1564 MachineBasicBlock::iterator Start = BB->begin();
1565 MachineBasicBlock::iterator Previous = SplitPoint;
1566 --Previous;
1567
1568 while (MIIsInTerminatorSequence(*Previous)) {
1569 SplitPoint = Previous;
1570 if (Previous == Start)
1571 break;
1572 --Previous;
1573 }
1574
1575 return SplitPoint;
1576 }
1577
1578 void
FinishBasicBlock()1579 SelectionDAGISel::FinishBasicBlock() {
1580 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1581 << FuncInfo->PHINodesToUpdate.size() << "\n";
1582 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1583 dbgs() << "Node " << i << " : ("
1584 << FuncInfo->PHINodesToUpdate[i].first
1585 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1586
1587 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1588 // PHI nodes in successors.
1589 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1590 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1591 assert(PHI->isPHI() &&
1592 "This is not a machine PHI node that we are updating!");
1593 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1594 continue;
1595 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1596 }
1597
1598 // Handle stack protector.
1599 if (SDB->SPDescriptor.shouldEmitFunctionBasedCheckStackProtector()) {
1600 // The target provides a guard check function. There is no need to
1601 // generate error handling code or to split current basic block.
1602 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1603
1604 // Add load and check to the basicblock.
1605 FuncInfo->MBB = ParentMBB;
1606 FuncInfo->InsertPt =
1607 FindSplitPointForStackProtector(ParentMBB);
1608 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1609 CurDAG->setRoot(SDB->getRoot());
1610 SDB->clear();
1611 CodeGenAndEmitDAG();
1612
1613 // Clear the Per-BB State.
1614 SDB->SPDescriptor.resetPerBBState();
1615 } else if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1616 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1617 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1618
1619 // Find the split point to split the parent mbb. At the same time copy all
1620 // physical registers used in the tail of parent mbb into virtual registers
1621 // before the split point and back into physical registers after the split
1622 // point. This prevents us needing to deal with Live-ins and many other
1623 // register allocation issues caused by us splitting the parent mbb. The
1624 // register allocator will clean up said virtual copies later on.
1625 MachineBasicBlock::iterator SplitPoint =
1626 FindSplitPointForStackProtector(ParentMBB);
1627
1628 // Splice the terminator of ParentMBB into SuccessMBB.
1629 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1630 SplitPoint,
1631 ParentMBB->end());
1632
1633 // Add compare/jump on neq/jump to the parent BB.
1634 FuncInfo->MBB = ParentMBB;
1635 FuncInfo->InsertPt = ParentMBB->end();
1636 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1637 CurDAG->setRoot(SDB->getRoot());
1638 SDB->clear();
1639 CodeGenAndEmitDAG();
1640
1641 // CodeGen Failure MBB if we have not codegened it yet.
1642 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1643 if (FailureMBB->empty()) {
1644 FuncInfo->MBB = FailureMBB;
1645 FuncInfo->InsertPt = FailureMBB->end();
1646 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1647 CurDAG->setRoot(SDB->getRoot());
1648 SDB->clear();
1649 CodeGenAndEmitDAG();
1650 }
1651
1652 // Clear the Per-BB State.
1653 SDB->SPDescriptor.resetPerBBState();
1654 }
1655
1656 // Lower each BitTestBlock.
1657 for (auto &BTB : SDB->BitTestCases) {
1658 // Lower header first, if it wasn't already lowered
1659 if (!BTB.Emitted) {
1660 // Set the current basic block to the mbb we wish to insert the code into
1661 FuncInfo->MBB = BTB.Parent;
1662 FuncInfo->InsertPt = FuncInfo->MBB->end();
1663 // Emit the code
1664 SDB->visitBitTestHeader(BTB, FuncInfo->MBB);
1665 CurDAG->setRoot(SDB->getRoot());
1666 SDB->clear();
1667 CodeGenAndEmitDAG();
1668 }
1669
1670 BranchProbability UnhandledProb = BTB.Prob;
1671 for (unsigned j = 0, ej = BTB.Cases.size(); j != ej; ++j) {
1672 UnhandledProb -= BTB.Cases[j].ExtraProb;
1673 // Set the current basic block to the mbb we wish to insert the code into
1674 FuncInfo->MBB = BTB.Cases[j].ThisBB;
1675 FuncInfo->InsertPt = FuncInfo->MBB->end();
1676 // Emit the code
1677
1678 // If all cases cover a contiguous range, it is not necessary to jump to
1679 // the default block after the last bit test fails. This is because the
1680 // range check during bit test header creation has guaranteed that every
1681 // case here doesn't go outside the range. In this case, there is no need
1682 // to perform the last bit test, as it will always be true. Instead, make
1683 // the second-to-last bit-test fall through to the target of the last bit
1684 // test, and delete the last bit test.
1685
1686 MachineBasicBlock *NextMBB;
1687 if (BTB.ContiguousRange && j + 2 == ej) {
1688 // Second-to-last bit-test with contiguous range: fall through to the
1689 // target of the final bit test.
1690 NextMBB = BTB.Cases[j + 1].TargetBB;
1691 } else if (j + 1 == ej) {
1692 // For the last bit test, fall through to Default.
1693 NextMBB = BTB.Default;
1694 } else {
1695 // Otherwise, fall through to the next bit test.
1696 NextMBB = BTB.Cases[j + 1].ThisBB;
1697 }
1698
1699 SDB->visitBitTestCase(BTB, NextMBB, UnhandledProb, BTB.Reg, BTB.Cases[j],
1700 FuncInfo->MBB);
1701
1702 CurDAG->setRoot(SDB->getRoot());
1703 SDB->clear();
1704 CodeGenAndEmitDAG();
1705
1706 if (BTB.ContiguousRange && j + 2 == ej) {
1707 // Since we're not going to use the final bit test, remove it.
1708 BTB.Cases.pop_back();
1709 break;
1710 }
1711 }
1712
1713 // Update PHI Nodes
1714 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1715 pi != pe; ++pi) {
1716 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1717 MachineBasicBlock *PHIBB = PHI->getParent();
1718 assert(PHI->isPHI() &&
1719 "This is not a machine PHI node that we are updating!");
1720 // This is "default" BB. We have two jumps to it. From "header" BB and
1721 // from last "case" BB, unless the latter was skipped.
1722 if (PHIBB == BTB.Default) {
1723 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(BTB.Parent);
1724 if (!BTB.ContiguousRange) {
1725 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1726 .addMBB(BTB.Cases.back().ThisBB);
1727 }
1728 }
1729 // One of "cases" BB.
1730 for (unsigned j = 0, ej = BTB.Cases.size();
1731 j != ej; ++j) {
1732 MachineBasicBlock* cBB = BTB.Cases[j].ThisBB;
1733 if (cBB->isSuccessor(PHIBB))
1734 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1735 }
1736 }
1737 }
1738 SDB->BitTestCases.clear();
1739
1740 // If the JumpTable record is filled in, then we need to emit a jump table.
1741 // Updating the PHI nodes is tricky in this case, since we need to determine
1742 // whether the PHI is a successor of the range check MBB or the jump table MBB
1743 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1744 // Lower header first, if it wasn't already lowered
1745 if (!SDB->JTCases[i].first.Emitted) {
1746 // Set the current basic block to the mbb we wish to insert the code into
1747 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1748 FuncInfo->InsertPt = FuncInfo->MBB->end();
1749 // Emit the code
1750 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1751 FuncInfo->MBB);
1752 CurDAG->setRoot(SDB->getRoot());
1753 SDB->clear();
1754 CodeGenAndEmitDAG();
1755 }
1756
1757 // Set the current basic block to the mbb we wish to insert the code into
1758 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1759 FuncInfo->InsertPt = FuncInfo->MBB->end();
1760 // Emit the code
1761 SDB->visitJumpTable(SDB->JTCases[i].second);
1762 CurDAG->setRoot(SDB->getRoot());
1763 SDB->clear();
1764 CodeGenAndEmitDAG();
1765
1766 // Update PHI Nodes
1767 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1768 pi != pe; ++pi) {
1769 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1770 MachineBasicBlock *PHIBB = PHI->getParent();
1771 assert(PHI->isPHI() &&
1772 "This is not a machine PHI node that we are updating!");
1773 // "default" BB. We can go there only from header BB.
1774 if (PHIBB == SDB->JTCases[i].second.Default)
1775 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1776 .addMBB(SDB->JTCases[i].first.HeaderBB);
1777 // JT BB. Just iterate over successors here
1778 if (FuncInfo->MBB->isSuccessor(PHIBB))
1779 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1780 }
1781 }
1782 SDB->JTCases.clear();
1783
1784 // If we generated any switch lowering information, build and codegen any
1785 // additional DAGs necessary.
1786 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1787 // Set the current basic block to the mbb we wish to insert the code into
1788 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1789 FuncInfo->InsertPt = FuncInfo->MBB->end();
1790
1791 // Determine the unique successors.
1792 SmallVector<MachineBasicBlock *, 2> Succs;
1793 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1794 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1795 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1796
1797 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1798 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1799 CurDAG->setRoot(SDB->getRoot());
1800 SDB->clear();
1801 CodeGenAndEmitDAG();
1802
1803 // Remember the last block, now that any splitting is done, for use in
1804 // populating PHI nodes in successors.
1805 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1806
1807 // Handle any PHI nodes in successors of this chunk, as if we were coming
1808 // from the original BB before switch expansion. Note that PHI nodes can
1809 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1810 // handle them the right number of times.
1811 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1812 FuncInfo->MBB = Succs[i];
1813 FuncInfo->InsertPt = FuncInfo->MBB->end();
1814 // FuncInfo->MBB may have been removed from the CFG if a branch was
1815 // constant folded.
1816 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1817 for (MachineBasicBlock::iterator
1818 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1819 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1820 MachineInstrBuilder PHI(*MF, MBBI);
1821 // This value for this PHI node is recorded in PHINodesToUpdate.
1822 for (unsigned pn = 0; ; ++pn) {
1823 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1824 "Didn't find PHI entry!");
1825 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1826 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1827 break;
1828 }
1829 }
1830 }
1831 }
1832 }
1833 }
1834 SDB->SwitchCases.clear();
1835 }
1836
1837 /// Create the scheduler. If a specific scheduler was specified
1838 /// via the SchedulerRegistry, use it, otherwise select the
1839 /// one preferred by the target.
1840 ///
CreateScheduler()1841 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1842 return ISHeuristic(this, OptLevel);
1843 }
1844
1845 //===----------------------------------------------------------------------===//
1846 // Helper functions used by the generated instruction selector.
1847 //===----------------------------------------------------------------------===//
1848 // Calls to these methods are generated by tblgen.
1849
1850 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1851 /// the dag combiner simplified the 255, we still want to match. RHS is the
1852 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1853 /// specified in the .td file (e.g. 255).
CheckAndMask(SDValue LHS,ConstantSDNode * RHS,int64_t DesiredMaskS) const1854 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1855 int64_t DesiredMaskS) const {
1856 const APInt &ActualMask = RHS->getAPIntValue();
1857 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1858
1859 // If the actual mask exactly matches, success!
1860 if (ActualMask == DesiredMask)
1861 return true;
1862
1863 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1864 if (ActualMask.intersects(~DesiredMask))
1865 return false;
1866
1867 // Otherwise, the DAG Combiner may have proven that the value coming in is
1868 // either already zero or is not demanded. Check for known zero input bits.
1869 APInt NeededMask = DesiredMask & ~ActualMask;
1870 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1871 return true;
1872
1873 // TODO: check to see if missing bits are just not demanded.
1874
1875 // Otherwise, this pattern doesn't match.
1876 return false;
1877 }
1878
1879 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1880 /// the dag combiner simplified the 255, we still want to match. RHS is the
1881 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1882 /// specified in the .td file (e.g. 255).
CheckOrMask(SDValue LHS,ConstantSDNode * RHS,int64_t DesiredMaskS) const1883 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1884 int64_t DesiredMaskS) const {
1885 const APInt &ActualMask = RHS->getAPIntValue();
1886 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1887
1888 // If the actual mask exactly matches, success!
1889 if (ActualMask == DesiredMask)
1890 return true;
1891
1892 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1893 if (ActualMask.intersects(~DesiredMask))
1894 return false;
1895
1896 // Otherwise, the DAG Combiner may have proven that the value coming in is
1897 // either already zero or is not demanded. Check for known zero input bits.
1898 APInt NeededMask = DesiredMask & ~ActualMask;
1899
1900 APInt KnownZero, KnownOne;
1901 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1902
1903 // If all the missing bits in the or are already known to be set, match!
1904 if ((NeededMask & KnownOne) == NeededMask)
1905 return true;
1906
1907 // TODO: check to see if missing bits are just not demanded.
1908
1909 // Otherwise, this pattern doesn't match.
1910 return false;
1911 }
1912
1913 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1914 /// by tblgen. Others should not call it.
SelectInlineAsmMemoryOperands(std::vector<SDValue> & Ops,const SDLoc & DL)1915 void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
1916 const SDLoc &DL) {
1917 std::vector<SDValue> InOps;
1918 std::swap(InOps, Ops);
1919
1920 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1921 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1922 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1923 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1924
1925 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1926 if (InOps[e-1].getValueType() == MVT::Glue)
1927 --e; // Don't process a glue operand if it is here.
1928
1929 while (i != e) {
1930 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1931 if (!InlineAsm::isMemKind(Flags)) {
1932 // Just skip over this operand, copying the operands verbatim.
1933 Ops.insert(Ops.end(), InOps.begin()+i,
1934 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1935 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1936 } else {
1937 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1938 "Memory operand with multiple values?");
1939
1940 unsigned TiedToOperand;
1941 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedToOperand)) {
1942 // We need the constraint ID from the operand this is tied to.
1943 unsigned CurOp = InlineAsm::Op_FirstOperand;
1944 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1945 for (; TiedToOperand; --TiedToOperand) {
1946 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1;
1947 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1948 }
1949 }
1950
1951 // Otherwise, this is a memory operand. Ask the target to select it.
1952 std::vector<SDValue> SelOps;
1953 if (SelectInlineAsmMemoryOperand(InOps[i+1],
1954 InlineAsm::getMemoryConstraintID(Flags),
1955 SelOps))
1956 report_fatal_error("Could not match memory address. Inline asm"
1957 " failure!");
1958
1959 // Add this to the output node.
1960 unsigned NewFlags =
1961 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1962 Ops.push_back(CurDAG->getTargetConstant(NewFlags, DL, MVT::i32));
1963 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1964 i += 2;
1965 }
1966 }
1967
1968 // Add the glue input back if present.
1969 if (e != InOps.size())
1970 Ops.push_back(InOps.back());
1971 }
1972
1973 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1974 /// SDNode.
1975 ///
findGlueUse(SDNode * N)1976 static SDNode *findGlueUse(SDNode *N) {
1977 unsigned FlagResNo = N->getNumValues()-1;
1978 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1979 SDUse &Use = I.getUse();
1980 if (Use.getResNo() == FlagResNo)
1981 return Use.getUser();
1982 }
1983 return nullptr;
1984 }
1985
1986 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1987 /// This function recursively traverses up the operand chain, ignoring
1988 /// certain nodes.
findNonImmUse(SDNode * Use,SDNode * Def,SDNode * ImmedUse,SDNode * Root,SmallPtrSetImpl<SDNode * > & Visited,bool IgnoreChains)1989 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1990 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1991 bool IgnoreChains) {
1992 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1993 // greater than all of its (recursive) operands. If we scan to a point where
1994 // 'use' is smaller than the node we're scanning for, then we know we will
1995 // never find it.
1996 //
1997 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1998 // happen because we scan down to newly selected nodes in the case of glue
1999 // uses.
2000 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
2001 return false;
2002
2003 // Don't revisit nodes if we already scanned it and didn't fail, we know we
2004 // won't fail if we scan it again.
2005 if (!Visited.insert(Use).second)
2006 return false;
2007
2008 for (const SDValue &Op : Use->op_values()) {
2009 // Ignore chain uses, they are validated by HandleMergeInputChains.
2010 if (Op.getValueType() == MVT::Other && IgnoreChains)
2011 continue;
2012
2013 SDNode *N = Op.getNode();
2014 if (N == Def) {
2015 if (Use == ImmedUse || Use == Root)
2016 continue; // We are not looking for immediate use.
2017 assert(N != Root);
2018 return true;
2019 }
2020
2021 // Traverse up the operand chain.
2022 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
2023 return true;
2024 }
2025 return false;
2026 }
2027
2028 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
2029 /// operand node N of U during instruction selection that starts at Root.
IsProfitableToFold(SDValue N,SDNode * U,SDNode * Root) const2030 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
2031 SDNode *Root) const {
2032 if (OptLevel == CodeGenOpt::None) return false;
2033 return N.hasOneUse();
2034 }
2035
2036 /// IsLegalToFold - Returns true if the specific operand node N of
2037 /// U can be folded during instruction selection that starts at Root.
IsLegalToFold(SDValue N,SDNode * U,SDNode * Root,CodeGenOpt::Level OptLevel,bool IgnoreChains)2038 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
2039 CodeGenOpt::Level OptLevel,
2040 bool IgnoreChains) {
2041 if (OptLevel == CodeGenOpt::None) return false;
2042
2043 // If Root use can somehow reach N through a path that that doesn't contain
2044 // U then folding N would create a cycle. e.g. In the following
2045 // diagram, Root can reach N through X. If N is folded into into Root, then
2046 // X is both a predecessor and a successor of U.
2047 //
2048 // [N*] //
2049 // ^ ^ //
2050 // / \ //
2051 // [U*] [X]? //
2052 // ^ ^ //
2053 // \ / //
2054 // \ / //
2055 // [Root*] //
2056 //
2057 // * indicates nodes to be folded together.
2058 //
2059 // If Root produces glue, then it gets (even more) interesting. Since it
2060 // will be "glued" together with its glue use in the scheduler, we need to
2061 // check if it might reach N.
2062 //
2063 // [N*] //
2064 // ^ ^ //
2065 // / \ //
2066 // [U*] [X]? //
2067 // ^ ^ //
2068 // \ \ //
2069 // \ | //
2070 // [Root*] | //
2071 // ^ | //
2072 // f | //
2073 // | / //
2074 // [Y] / //
2075 // ^ / //
2076 // f / //
2077 // | / //
2078 // [GU] //
2079 //
2080 // If GU (glue use) indirectly reaches N (the load), and Root folds N
2081 // (call it Fold), then X is a predecessor of GU and a successor of
2082 // Fold. But since Fold and GU are glued together, this will create
2083 // a cycle in the scheduling graph.
2084
2085 // If the node has glue, walk down the graph to the "lowest" node in the
2086 // glueged set.
2087 EVT VT = Root->getValueType(Root->getNumValues()-1);
2088 while (VT == MVT::Glue) {
2089 SDNode *GU = findGlueUse(Root);
2090 if (!GU)
2091 break;
2092 Root = GU;
2093 VT = Root->getValueType(Root->getNumValues()-1);
2094
2095 // If our query node has a glue result with a use, we've walked up it. If
2096 // the user (which has already been selected) has a chain or indirectly uses
2097 // the chain, our WalkChainUsers predicate will not consider it. Because of
2098 // this, we cannot ignore chains in this predicate.
2099 IgnoreChains = false;
2100 }
2101
2102
2103 SmallPtrSet<SDNode*, 16> Visited;
2104 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
2105 }
2106
Select_INLINEASM(SDNode * N)2107 void SelectionDAGISel::Select_INLINEASM(SDNode *N) {
2108 SDLoc DL(N);
2109
2110 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
2111 SelectInlineAsmMemoryOperands(Ops, DL);
2112
2113 const EVT VTs[] = {MVT::Other, MVT::Glue};
2114 SDValue New = CurDAG->getNode(ISD::INLINEASM, DL, VTs, Ops);
2115 New->setNodeId(-1);
2116 ReplaceUses(N, New.getNode());
2117 CurDAG->RemoveDeadNode(N);
2118 }
2119
Select_READ_REGISTER(SDNode * Op)2120 void SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
2121 SDLoc dl(Op);
2122 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
2123 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
2124 unsigned Reg =
2125 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0),
2126 *CurDAG);
2127 SDValue New = CurDAG->getCopyFromReg(
2128 Op->getOperand(0), dl, Reg, Op->getValueType(0));
2129 New->setNodeId(-1);
2130 ReplaceUses(Op, New.getNode());
2131 CurDAG->RemoveDeadNode(Op);
2132 }
2133
Select_WRITE_REGISTER(SDNode * Op)2134 void SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
2135 SDLoc dl(Op);
2136 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
2137 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
2138 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
2139 Op->getOperand(2).getValueType(),
2140 *CurDAG);
2141 SDValue New = CurDAG->getCopyToReg(
2142 Op->getOperand(0), dl, Reg, Op->getOperand(2));
2143 New->setNodeId(-1);
2144 ReplaceUses(Op, New.getNode());
2145 CurDAG->RemoveDeadNode(Op);
2146 }
2147
Select_UNDEF(SDNode * N)2148 void SelectionDAGISel::Select_UNDEF(SDNode *N) {
2149 CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF, N->getValueType(0));
2150 }
2151
2152 /// GetVBR - decode a vbr encoding whose top bit is set.
2153 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline uint64_t
GetVBR(uint64_t Val,const unsigned char * MatcherTable,unsigned & Idx)2154 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
2155 assert(Val >= 128 && "Not a VBR");
2156 Val &= 127; // Remove first vbr bit.
2157
2158 unsigned Shift = 7;
2159 uint64_t NextBits;
2160 do {
2161 NextBits = MatcherTable[Idx++];
2162 Val |= (NextBits&127) << Shift;
2163 Shift += 7;
2164 } while (NextBits & 128);
2165
2166 return Val;
2167 }
2168
2169 /// When a match is complete, this method updates uses of interior chain results
2170 /// to use the new results.
UpdateChains(SDNode * NodeToMatch,SDValue InputChain,const SmallVectorImpl<SDNode * > & ChainNodesMatched,bool isMorphNodeTo)2171 void SelectionDAGISel::UpdateChains(
2172 SDNode *NodeToMatch, SDValue InputChain,
2173 const SmallVectorImpl<SDNode *> &ChainNodesMatched, bool isMorphNodeTo) {
2174 SmallVector<SDNode*, 4> NowDeadNodes;
2175
2176 // Now that all the normal results are replaced, we replace the chain and
2177 // glue results if present.
2178 if (!ChainNodesMatched.empty()) {
2179 assert(InputChain.getNode() &&
2180 "Matched input chains but didn't produce a chain");
2181 // Loop over all of the nodes we matched that produced a chain result.
2182 // Replace all the chain results with the final chain we ended up with.
2183 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2184 SDNode *ChainNode = ChainNodesMatched[i];
2185 assert(ChainNode->getOpcode() != ISD::DELETED_NODE &&
2186 "Deleted node left in chain");
2187
2188 // Don't replace the results of the root node if we're doing a
2189 // MorphNodeTo.
2190 if (ChainNode == NodeToMatch && isMorphNodeTo)
2191 continue;
2192
2193 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2194 if (ChainVal.getValueType() == MVT::Glue)
2195 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2196 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2197 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2198
2199 // If the node became dead and we haven't already seen it, delete it.
2200 if (ChainNode != NodeToMatch && ChainNode->use_empty() &&
2201 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2202 NowDeadNodes.push_back(ChainNode);
2203 }
2204 }
2205
2206 if (!NowDeadNodes.empty())
2207 CurDAG->RemoveDeadNodes(NowDeadNodes);
2208
2209 DEBUG(dbgs() << "ISEL: Match complete!\n");
2210 }
2211
2212 enum ChainResult {
2213 CR_Simple,
2214 CR_InducesCycle,
2215 CR_LeadsToInteriorNode
2216 };
2217
2218 /// WalkChainUsers - Walk down the users of the specified chained node that is
2219 /// part of the pattern we're matching, looking at all of the users we find.
2220 /// This determines whether something is an interior node, whether we have a
2221 /// non-pattern node in between two pattern nodes (which prevent folding because
2222 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2223 /// between pattern nodes (in which case the TF becomes part of the pattern).
2224 ///
2225 /// The walk we do here is guaranteed to be small because we quickly get down to
2226 /// already selected nodes "below" us.
2227 static ChainResult
WalkChainUsers(const SDNode * ChainedNode,SmallVectorImpl<SDNode * > & ChainedNodesInPattern,DenseMap<const SDNode *,ChainResult> & TokenFactorResult,SmallVectorImpl<SDNode * > & InteriorChainedNodes)2228 WalkChainUsers(const SDNode *ChainedNode,
2229 SmallVectorImpl<SDNode *> &ChainedNodesInPattern,
2230 DenseMap<const SDNode *, ChainResult> &TokenFactorResult,
2231 SmallVectorImpl<SDNode *> &InteriorChainedNodes) {
2232 ChainResult Result = CR_Simple;
2233
2234 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2235 E = ChainedNode->use_end(); UI != E; ++UI) {
2236 // Make sure the use is of the chain, not some other value we produce.
2237 if (UI.getUse().getValueType() != MVT::Other) continue;
2238
2239 SDNode *User = *UI;
2240
2241 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2242 continue;
2243
2244 // If we see an already-selected machine node, then we've gone beyond the
2245 // pattern that we're selecting down into the already selected chunk of the
2246 // DAG.
2247 unsigned UserOpcode = User->getOpcode();
2248 if (User->isMachineOpcode() ||
2249 UserOpcode == ISD::CopyToReg ||
2250 UserOpcode == ISD::CopyFromReg ||
2251 UserOpcode == ISD::INLINEASM ||
2252 UserOpcode == ISD::EH_LABEL ||
2253 UserOpcode == ISD::LIFETIME_START ||
2254 UserOpcode == ISD::LIFETIME_END) {
2255 // If their node ID got reset to -1 then they've already been selected.
2256 // Treat them like a MachineOpcode.
2257 if (User->getNodeId() == -1)
2258 continue;
2259 }
2260
2261 // If we have a TokenFactor, we handle it specially.
2262 if (User->getOpcode() != ISD::TokenFactor) {
2263 // If the node isn't a token factor and isn't part of our pattern, then it
2264 // must be a random chained node in between two nodes we're selecting.
2265 // This happens when we have something like:
2266 // x = load ptr
2267 // call
2268 // y = x+4
2269 // store y -> ptr
2270 // Because we structurally match the load/store as a read/modify/write,
2271 // but the call is chained between them. We cannot fold in this case
2272 // because it would induce a cycle in the graph.
2273 if (!std::count(ChainedNodesInPattern.begin(),
2274 ChainedNodesInPattern.end(), User))
2275 return CR_InducesCycle;
2276
2277 // Otherwise we found a node that is part of our pattern. For example in:
2278 // x = load ptr
2279 // y = x+4
2280 // store y -> ptr
2281 // This would happen when we're scanning down from the load and see the
2282 // store as a user. Record that there is a use of ChainedNode that is
2283 // part of the pattern and keep scanning uses.
2284 Result = CR_LeadsToInteriorNode;
2285 InteriorChainedNodes.push_back(User);
2286 continue;
2287 }
2288
2289 // If we found a TokenFactor, there are two cases to consider: first if the
2290 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2291 // uses of the TF are in our pattern) we just want to ignore it. Second,
2292 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2293 // [Load chain]
2294 // ^
2295 // |
2296 // [Load]
2297 // ^ ^
2298 // | \ DAG's like cheese
2299 // / \ do you?
2300 // / |
2301 // [TokenFactor] [Op]
2302 // ^ ^
2303 // | |
2304 // \ /
2305 // \ /
2306 // [Store]
2307 //
2308 // In this case, the TokenFactor becomes part of our match and we rewrite it
2309 // as a new TokenFactor.
2310 //
2311 // To distinguish these two cases, do a recursive walk down the uses.
2312 auto MemoizeResult = TokenFactorResult.find(User);
2313 bool Visited = MemoizeResult != TokenFactorResult.end();
2314 // Recursively walk chain users only if the result is not memoized.
2315 if (!Visited) {
2316 auto Res = WalkChainUsers(User, ChainedNodesInPattern, TokenFactorResult,
2317 InteriorChainedNodes);
2318 MemoizeResult = TokenFactorResult.insert(std::make_pair(User, Res)).first;
2319 }
2320 switch (MemoizeResult->second) {
2321 case CR_Simple:
2322 // If the uses of the TokenFactor are just already-selected nodes, ignore
2323 // it, it is "below" our pattern.
2324 continue;
2325 case CR_InducesCycle:
2326 // If the uses of the TokenFactor lead to nodes that are not part of our
2327 // pattern that are not selected, folding would turn this into a cycle,
2328 // bail out now.
2329 return CR_InducesCycle;
2330 case CR_LeadsToInteriorNode:
2331 break; // Otherwise, keep processing.
2332 }
2333
2334 // Okay, we know we're in the interesting interior case. The TokenFactor
2335 // is now going to be considered part of the pattern so that we rewrite its
2336 // uses (it may have uses that are not part of the pattern) with the
2337 // ultimate chain result of the generated code. We will also add its chain
2338 // inputs as inputs to the ultimate TokenFactor we create.
2339 Result = CR_LeadsToInteriorNode;
2340 if (!Visited) {
2341 ChainedNodesInPattern.push_back(User);
2342 InteriorChainedNodes.push_back(User);
2343 }
2344 }
2345
2346 return Result;
2347 }
2348
2349 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2350 /// operation for when the pattern matched at least one node with a chains. The
2351 /// input vector contains a list of all of the chained nodes that we match. We
2352 /// must determine if this is a valid thing to cover (i.e. matching it won't
2353 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2354 /// be used as the input node chain for the generated nodes.
2355 static SDValue
HandleMergeInputChains(SmallVectorImpl<SDNode * > & ChainNodesMatched,SelectionDAG * CurDAG)2356 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2357 SelectionDAG *CurDAG) {
2358 // Used for memoization. Without it WalkChainUsers could take exponential
2359 // time to run.
2360 DenseMap<const SDNode *, ChainResult> TokenFactorResult;
2361 // Walk all of the chained nodes we've matched, recursively scanning down the
2362 // users of the chain result. This adds any TokenFactor nodes that are caught
2363 // in between chained nodes to the chained and interior nodes list.
2364 SmallVector<SDNode*, 3> InteriorChainedNodes;
2365 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2366 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2367 TokenFactorResult,
2368 InteriorChainedNodes) == CR_InducesCycle)
2369 return SDValue(); // Would induce a cycle.
2370 }
2371
2372 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2373 // that we are interested in. Form our input TokenFactor node.
2374 SmallVector<SDValue, 3> InputChains;
2375 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2376 // Add the input chain of this node to the InputChains list (which will be
2377 // the operands of the generated TokenFactor) if it's not an interior node.
2378 SDNode *N = ChainNodesMatched[i];
2379 if (N->getOpcode() != ISD::TokenFactor) {
2380 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2381 continue;
2382
2383 // Otherwise, add the input chain.
2384 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2385 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2386 InputChains.push_back(InChain);
2387 continue;
2388 }
2389
2390 // If we have a token factor, we want to add all inputs of the token factor
2391 // that are not part of the pattern we're matching.
2392 for (const SDValue &Op : N->op_values()) {
2393 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2394 Op.getNode()))
2395 InputChains.push_back(Op);
2396 }
2397 }
2398
2399 if (InputChains.size() == 1)
2400 return InputChains[0];
2401 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2402 MVT::Other, InputChains);
2403 }
2404
2405 /// MorphNode - Handle morphing a node in place for the selector.
2406 SDNode *SelectionDAGISel::
MorphNode(SDNode * Node,unsigned TargetOpc,SDVTList VTList,ArrayRef<SDValue> Ops,unsigned EmitNodeInfo)2407 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2408 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2409 // It is possible we're using MorphNodeTo to replace a node with no
2410 // normal results with one that has a normal result (or we could be
2411 // adding a chain) and the input could have glue and chains as well.
2412 // In this case we need to shift the operands down.
2413 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2414 // than the old isel though.
2415 int OldGlueResultNo = -1, OldChainResultNo = -1;
2416
2417 unsigned NTMNumResults = Node->getNumValues();
2418 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2419 OldGlueResultNo = NTMNumResults-1;
2420 if (NTMNumResults != 1 &&
2421 Node->getValueType(NTMNumResults-2) == MVT::Other)
2422 OldChainResultNo = NTMNumResults-2;
2423 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2424 OldChainResultNo = NTMNumResults-1;
2425
2426 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2427 // that this deletes operands of the old node that become dead.
2428 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2429
2430 // MorphNodeTo can operate in two ways: if an existing node with the
2431 // specified operands exists, it can just return it. Otherwise, it
2432 // updates the node in place to have the requested operands.
2433 if (Res == Node) {
2434 // If we updated the node in place, reset the node ID. To the isel,
2435 // this should be just like a newly allocated machine node.
2436 Res->setNodeId(-1);
2437 }
2438
2439 unsigned ResNumResults = Res->getNumValues();
2440 // Move the glue if needed.
2441 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2442 (unsigned)OldGlueResultNo != ResNumResults-1)
2443 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2444 SDValue(Res, ResNumResults-1));
2445
2446 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2447 --ResNumResults;
2448
2449 // Move the chain reference if needed.
2450 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2451 (unsigned)OldChainResultNo != ResNumResults-1)
2452 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2453 SDValue(Res, ResNumResults-1));
2454
2455 // Otherwise, no replacement happened because the node already exists. Replace
2456 // Uses of the old node with the new one.
2457 if (Res != Node) {
2458 CurDAG->ReplaceAllUsesWith(Node, Res);
2459 CurDAG->RemoveDeadNode(Node);
2460 }
2461
2462 return Res;
2463 }
2464
2465 /// CheckSame - Implements OP_CheckSame.
2466 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
CheckSame(const unsigned char * MatcherTable,unsigned & MatcherIndex,SDValue N,const SmallVectorImpl<std::pair<SDValue,SDNode * >> & RecordedNodes)2467 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2468 SDValue N,
2469 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2470 // Accept if it is exactly the same as a previously recorded node.
2471 unsigned RecNo = MatcherTable[MatcherIndex++];
2472 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2473 return N == RecordedNodes[RecNo].first;
2474 }
2475
2476 /// CheckChildSame - Implements OP_CheckChildXSame.
2477 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
CheckChildSame(const unsigned char * MatcherTable,unsigned & MatcherIndex,SDValue N,const SmallVectorImpl<std::pair<SDValue,SDNode * >> & RecordedNodes,unsigned ChildNo)2478 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2479 SDValue N,
2480 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2481 unsigned ChildNo) {
2482 if (ChildNo >= N.getNumOperands())
2483 return false; // Match fails if out of range child #.
2484 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2485 RecordedNodes);
2486 }
2487
2488 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2489 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
CheckPatternPredicate(const unsigned char * MatcherTable,unsigned & MatcherIndex,const SelectionDAGISel & SDISel)2490 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2491 const SelectionDAGISel &SDISel) {
2492 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2493 }
2494
2495 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2496 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
CheckNodePredicate(const unsigned char * MatcherTable,unsigned & MatcherIndex,const SelectionDAGISel & SDISel,SDNode * N)2497 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2498 const SelectionDAGISel &SDISel, SDNode *N) {
2499 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2500 }
2501
2502 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
CheckOpcode(const unsigned char * MatcherTable,unsigned & MatcherIndex,SDNode * N)2503 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2504 SDNode *N) {
2505 uint16_t Opc = MatcherTable[MatcherIndex++];
2506 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2507 return N->getOpcode() == Opc;
2508 }
2509
2510 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
CheckType(const unsigned char * MatcherTable,unsigned & MatcherIndex,SDValue N,const TargetLowering * TLI,const DataLayout & DL)2511 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N,
2512 const TargetLowering *TLI, const DataLayout &DL) {
2513 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2514 if (N.getValueType() == VT) return true;
2515
2516 // Handle the case when VT is iPTR.
2517 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(DL);
2518 }
2519
2520 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
CheckChildType(const unsigned char * MatcherTable,unsigned & MatcherIndex,SDValue N,const TargetLowering * TLI,const DataLayout & DL,unsigned ChildNo)2521 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2522 SDValue N, const TargetLowering *TLI, const DataLayout &DL,
2523 unsigned ChildNo) {
2524 if (ChildNo >= N.getNumOperands())
2525 return false; // Match fails if out of range child #.
2526 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI,
2527 DL);
2528 }
2529
2530 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
CheckCondCode(const unsigned char * MatcherTable,unsigned & MatcherIndex,SDValue N)2531 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2532 SDValue N) {
2533 return cast<CondCodeSDNode>(N)->get() ==
2534 (ISD::CondCode)MatcherTable[MatcherIndex++];
2535 }
2536
2537 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
CheckValueType(const unsigned char * MatcherTable,unsigned & MatcherIndex,SDValue N,const TargetLowering * TLI,const DataLayout & DL)2538 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2539 SDValue N, const TargetLowering *TLI, const DataLayout &DL) {
2540 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2541 if (cast<VTSDNode>(N)->getVT() == VT)
2542 return true;
2543
2544 // Handle the case when VT is iPTR.
2545 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(DL);
2546 }
2547
2548 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
CheckInteger(const unsigned char * MatcherTable,unsigned & MatcherIndex,SDValue N)2549 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2550 SDValue N) {
2551 int64_t Val = MatcherTable[MatcherIndex++];
2552 if (Val & 128)
2553 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2554
2555 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2556 return C && C->getSExtValue() == Val;
2557 }
2558
2559 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
CheckChildInteger(const unsigned char * MatcherTable,unsigned & MatcherIndex,SDValue N,unsigned ChildNo)2560 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2561 SDValue N, unsigned ChildNo) {
2562 if (ChildNo >= N.getNumOperands())
2563 return false; // Match fails if out of range child #.
2564 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2565 }
2566
2567 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
CheckAndImm(const unsigned char * MatcherTable,unsigned & MatcherIndex,SDValue N,const SelectionDAGISel & SDISel)2568 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2569 SDValue N, const SelectionDAGISel &SDISel) {
2570 int64_t Val = MatcherTable[MatcherIndex++];
2571 if (Val & 128)
2572 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2573
2574 if (N->getOpcode() != ISD::AND) return false;
2575
2576 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2577 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2578 }
2579
2580 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
CheckOrImm(const unsigned char * MatcherTable,unsigned & MatcherIndex,SDValue N,const SelectionDAGISel & SDISel)2581 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2582 SDValue N, const SelectionDAGISel &SDISel) {
2583 int64_t Val = MatcherTable[MatcherIndex++];
2584 if (Val & 128)
2585 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2586
2587 if (N->getOpcode() != ISD::OR) return false;
2588
2589 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2590 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2591 }
2592
2593 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2594 /// scope, evaluate the current node. If the current predicate is known to
2595 /// fail, set Result=true and return anything. If the current predicate is
2596 /// known to pass, set Result=false and return the MatcherIndex to continue
2597 /// with. If the current predicate is unknown, set Result=false and return the
2598 /// MatcherIndex to continue with.
IsPredicateKnownToFail(const unsigned char * Table,unsigned Index,SDValue N,bool & Result,const SelectionDAGISel & SDISel,SmallVectorImpl<std::pair<SDValue,SDNode * >> & RecordedNodes)2599 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2600 unsigned Index, SDValue N,
2601 bool &Result,
2602 const SelectionDAGISel &SDISel,
2603 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2604 switch (Table[Index++]) {
2605 default:
2606 Result = false;
2607 return Index-1; // Could not evaluate this predicate.
2608 case SelectionDAGISel::OPC_CheckSame:
2609 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2610 return Index;
2611 case SelectionDAGISel::OPC_CheckChild0Same:
2612 case SelectionDAGISel::OPC_CheckChild1Same:
2613 case SelectionDAGISel::OPC_CheckChild2Same:
2614 case SelectionDAGISel::OPC_CheckChild3Same:
2615 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2616 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2617 return Index;
2618 case SelectionDAGISel::OPC_CheckPatternPredicate:
2619 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2620 return Index;
2621 case SelectionDAGISel::OPC_CheckPredicate:
2622 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2623 return Index;
2624 case SelectionDAGISel::OPC_CheckOpcode:
2625 Result = !::CheckOpcode(Table, Index, N.getNode());
2626 return Index;
2627 case SelectionDAGISel::OPC_CheckType:
2628 Result = !::CheckType(Table, Index, N, SDISel.TLI,
2629 SDISel.CurDAG->getDataLayout());
2630 return Index;
2631 case SelectionDAGISel::OPC_CheckChild0Type:
2632 case SelectionDAGISel::OPC_CheckChild1Type:
2633 case SelectionDAGISel::OPC_CheckChild2Type:
2634 case SelectionDAGISel::OPC_CheckChild3Type:
2635 case SelectionDAGISel::OPC_CheckChild4Type:
2636 case SelectionDAGISel::OPC_CheckChild5Type:
2637 case SelectionDAGISel::OPC_CheckChild6Type:
2638 case SelectionDAGISel::OPC_CheckChild7Type:
2639 Result = !::CheckChildType(
2640 Table, Index, N, SDISel.TLI, SDISel.CurDAG->getDataLayout(),
2641 Table[Index - 1] - SelectionDAGISel::OPC_CheckChild0Type);
2642 return Index;
2643 case SelectionDAGISel::OPC_CheckCondCode:
2644 Result = !::CheckCondCode(Table, Index, N);
2645 return Index;
2646 case SelectionDAGISel::OPC_CheckValueType:
2647 Result = !::CheckValueType(Table, Index, N, SDISel.TLI,
2648 SDISel.CurDAG->getDataLayout());
2649 return Index;
2650 case SelectionDAGISel::OPC_CheckInteger:
2651 Result = !::CheckInteger(Table, Index, N);
2652 return Index;
2653 case SelectionDAGISel::OPC_CheckChild0Integer:
2654 case SelectionDAGISel::OPC_CheckChild1Integer:
2655 case SelectionDAGISel::OPC_CheckChild2Integer:
2656 case SelectionDAGISel::OPC_CheckChild3Integer:
2657 case SelectionDAGISel::OPC_CheckChild4Integer:
2658 Result = !::CheckChildInteger(Table, Index, N,
2659 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2660 return Index;
2661 case SelectionDAGISel::OPC_CheckAndImm:
2662 Result = !::CheckAndImm(Table, Index, N, SDISel);
2663 return Index;
2664 case SelectionDAGISel::OPC_CheckOrImm:
2665 Result = !::CheckOrImm(Table, Index, N, SDISel);
2666 return Index;
2667 }
2668 }
2669
2670 namespace {
2671 struct MatchScope {
2672 /// FailIndex - If this match fails, this is the index to continue with.
2673 unsigned FailIndex;
2674
2675 /// NodeStack - The node stack when the scope was formed.
2676 SmallVector<SDValue, 4> NodeStack;
2677
2678 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2679 unsigned NumRecordedNodes;
2680
2681 /// NumMatchedMemRefs - The number of matched memref entries.
2682 unsigned NumMatchedMemRefs;
2683
2684 /// InputChain/InputGlue - The current chain/glue
2685 SDValue InputChain, InputGlue;
2686
2687 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2688 bool HasChainNodesMatched;
2689 };
2690
2691 /// \\brief A DAG update listener to keep the matching state
2692 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2693 /// change the DAG while matching. X86 addressing mode matcher is an example
2694 /// for this.
2695 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2696 {
2697 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2698 SmallVectorImpl<MatchScope> &MatchScopes;
2699 public:
MatchStateUpdater(SelectionDAG & DAG,SmallVectorImpl<std::pair<SDValue,SDNode * >> & RN,SmallVectorImpl<MatchScope> & MS)2700 MatchStateUpdater(SelectionDAG &DAG,
2701 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2702 SmallVectorImpl<MatchScope> &MS) :
2703 SelectionDAG::DAGUpdateListener(DAG),
2704 RecordedNodes(RN), MatchScopes(MS) { }
2705
NodeDeleted(SDNode * N,SDNode * E)2706 void NodeDeleted(SDNode *N, SDNode *E) override {
2707 // Some early-returns here to avoid the search if we deleted the node or
2708 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2709 // do, so it's unnecessary to update matching state at that point).
2710 // Neither of these can occur currently because we only install this
2711 // update listener during matching a complex patterns.
2712 if (!E || E->isMachineOpcode())
2713 return;
2714 // Performing linear search here does not matter because we almost never
2715 // run this code. You'd have to have a CSE during complex pattern
2716 // matching.
2717 for (auto &I : RecordedNodes)
2718 if (I.first.getNode() == N)
2719 I.first.setNode(E);
2720
2721 for (auto &I : MatchScopes)
2722 for (auto &J : I.NodeStack)
2723 if (J.getNode() == N)
2724 J.setNode(E);
2725 }
2726 };
2727 } // end anonymous namespace
2728
SelectCodeCommon(SDNode * NodeToMatch,const unsigned char * MatcherTable,unsigned TableSize)2729 void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
2730 const unsigned char *MatcherTable,
2731 unsigned TableSize) {
2732 // FIXME: Should these even be selected? Handle these cases in the caller?
2733 switch (NodeToMatch->getOpcode()) {
2734 default:
2735 break;
2736 case ISD::EntryToken: // These nodes remain the same.
2737 case ISD::BasicBlock:
2738 case ISD::Register:
2739 case ISD::RegisterMask:
2740 case ISD::HANDLENODE:
2741 case ISD::MDNODE_SDNODE:
2742 case ISD::TargetConstant:
2743 case ISD::TargetConstantFP:
2744 case ISD::TargetConstantPool:
2745 case ISD::TargetFrameIndex:
2746 case ISD::TargetExternalSymbol:
2747 case ISD::MCSymbol:
2748 case ISD::TargetBlockAddress:
2749 case ISD::TargetJumpTable:
2750 case ISD::TargetGlobalTLSAddress:
2751 case ISD::TargetGlobalAddress:
2752 case ISD::TokenFactor:
2753 case ISD::CopyFromReg:
2754 case ISD::CopyToReg:
2755 case ISD::EH_LABEL:
2756 case ISD::LIFETIME_START:
2757 case ISD::LIFETIME_END:
2758 NodeToMatch->setNodeId(-1); // Mark selected.
2759 return;
2760 case ISD::AssertSext:
2761 case ISD::AssertZext:
2762 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2763 NodeToMatch->getOperand(0));
2764 CurDAG->RemoveDeadNode(NodeToMatch);
2765 return;
2766 case ISD::INLINEASM:
2767 Select_INLINEASM(NodeToMatch);
2768 return;
2769 case ISD::READ_REGISTER:
2770 Select_READ_REGISTER(NodeToMatch);
2771 return;
2772 case ISD::WRITE_REGISTER:
2773 Select_WRITE_REGISTER(NodeToMatch);
2774 return;
2775 case ISD::UNDEF:
2776 Select_UNDEF(NodeToMatch);
2777 return;
2778 }
2779
2780 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2781
2782 // Set up the node stack with NodeToMatch as the only node on the stack.
2783 SmallVector<SDValue, 8> NodeStack;
2784 SDValue N = SDValue(NodeToMatch, 0);
2785 NodeStack.push_back(N);
2786
2787 // MatchScopes - Scopes used when matching, if a match failure happens, this
2788 // indicates where to continue checking.
2789 SmallVector<MatchScope, 8> MatchScopes;
2790
2791 // RecordedNodes - This is the set of nodes that have been recorded by the
2792 // state machine. The second value is the parent of the node, or null if the
2793 // root is recorded.
2794 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2795
2796 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2797 // pattern.
2798 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2799
2800 // These are the current input chain and glue for use when generating nodes.
2801 // Various Emit operations change these. For example, emitting a copytoreg
2802 // uses and updates these.
2803 SDValue InputChain, InputGlue;
2804
2805 // ChainNodesMatched - If a pattern matches nodes that have input/output
2806 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2807 // which ones they are. The result is captured into this list so that we can
2808 // update the chain results when the pattern is complete.
2809 SmallVector<SDNode*, 3> ChainNodesMatched;
2810
2811 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2812 NodeToMatch->dump(CurDAG);
2813 dbgs() << '\n');
2814
2815 // Determine where to start the interpreter. Normally we start at opcode #0,
2816 // but if the state machine starts with an OPC_SwitchOpcode, then we
2817 // accelerate the first lookup (which is guaranteed to be hot) with the
2818 // OpcodeOffset table.
2819 unsigned MatcherIndex = 0;
2820
2821 if (!OpcodeOffset.empty()) {
2822 // Already computed the OpcodeOffset table, just index into it.
2823 if (N.getOpcode() < OpcodeOffset.size())
2824 MatcherIndex = OpcodeOffset[N.getOpcode()];
2825 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2826
2827 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2828 // Otherwise, the table isn't computed, but the state machine does start
2829 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2830 // is the first time we're selecting an instruction.
2831 unsigned Idx = 1;
2832 while (1) {
2833 // Get the size of this case.
2834 unsigned CaseSize = MatcherTable[Idx++];
2835 if (CaseSize & 128)
2836 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2837 if (CaseSize == 0) break;
2838
2839 // Get the opcode, add the index to the table.
2840 uint16_t Opc = MatcherTable[Idx++];
2841 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2842 if (Opc >= OpcodeOffset.size())
2843 OpcodeOffset.resize((Opc+1)*2);
2844 OpcodeOffset[Opc] = Idx;
2845 Idx += CaseSize;
2846 }
2847
2848 // Okay, do the lookup for the first opcode.
2849 if (N.getOpcode() < OpcodeOffset.size())
2850 MatcherIndex = OpcodeOffset[N.getOpcode()];
2851 }
2852
2853 while (1) {
2854 assert(MatcherIndex < TableSize && "Invalid index");
2855 #ifndef NDEBUG
2856 unsigned CurrentOpcodeIndex = MatcherIndex;
2857 #endif
2858 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2859 switch (Opcode) {
2860 case OPC_Scope: {
2861 // Okay, the semantics of this operation are that we should push a scope
2862 // then evaluate the first child. However, pushing a scope only to have
2863 // the first check fail (which then pops it) is inefficient. If we can
2864 // determine immediately that the first check (or first several) will
2865 // immediately fail, don't even bother pushing a scope for them.
2866 unsigned FailIndex;
2867
2868 while (1) {
2869 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2870 if (NumToSkip & 128)
2871 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2872 // Found the end of the scope with no match.
2873 if (NumToSkip == 0) {
2874 FailIndex = 0;
2875 break;
2876 }
2877
2878 FailIndex = MatcherIndex+NumToSkip;
2879
2880 unsigned MatcherIndexOfPredicate = MatcherIndex;
2881 (void)MatcherIndexOfPredicate; // silence warning.
2882
2883 // If we can't evaluate this predicate without pushing a scope (e.g. if
2884 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2885 // push the scope and evaluate the full predicate chain.
2886 bool Result;
2887 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2888 Result, *this, RecordedNodes);
2889 if (!Result)
2890 break;
2891
2892 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2893 << "index " << MatcherIndexOfPredicate
2894 << ", continuing at " << FailIndex << "\n");
2895 ++NumDAGIselRetries;
2896
2897 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2898 // move to the next case.
2899 MatcherIndex = FailIndex;
2900 }
2901
2902 // If the whole scope failed to match, bail.
2903 if (FailIndex == 0) break;
2904
2905 // Push a MatchScope which indicates where to go if the first child fails
2906 // to match.
2907 MatchScope NewEntry;
2908 NewEntry.FailIndex = FailIndex;
2909 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2910 NewEntry.NumRecordedNodes = RecordedNodes.size();
2911 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2912 NewEntry.InputChain = InputChain;
2913 NewEntry.InputGlue = InputGlue;
2914 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2915 MatchScopes.push_back(NewEntry);
2916 continue;
2917 }
2918 case OPC_RecordNode: {
2919 // Remember this node, it may end up being an operand in the pattern.
2920 SDNode *Parent = nullptr;
2921 if (NodeStack.size() > 1)
2922 Parent = NodeStack[NodeStack.size()-2].getNode();
2923 RecordedNodes.push_back(std::make_pair(N, Parent));
2924 continue;
2925 }
2926
2927 case OPC_RecordChild0: case OPC_RecordChild1:
2928 case OPC_RecordChild2: case OPC_RecordChild3:
2929 case OPC_RecordChild4: case OPC_RecordChild5:
2930 case OPC_RecordChild6: case OPC_RecordChild7: {
2931 unsigned ChildNo = Opcode-OPC_RecordChild0;
2932 if (ChildNo >= N.getNumOperands())
2933 break; // Match fails if out of range child #.
2934
2935 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2936 N.getNode()));
2937 continue;
2938 }
2939 case OPC_RecordMemRef:
2940 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2941 continue;
2942
2943 case OPC_CaptureGlueInput:
2944 // If the current node has an input glue, capture it in InputGlue.
2945 if (N->getNumOperands() != 0 &&
2946 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2947 InputGlue = N->getOperand(N->getNumOperands()-1);
2948 continue;
2949
2950 case OPC_MoveChild: {
2951 unsigned ChildNo = MatcherTable[MatcherIndex++];
2952 if (ChildNo >= N.getNumOperands())
2953 break; // Match fails if out of range child #.
2954 N = N.getOperand(ChildNo);
2955 NodeStack.push_back(N);
2956 continue;
2957 }
2958
2959 case OPC_MoveChild0: case OPC_MoveChild1:
2960 case OPC_MoveChild2: case OPC_MoveChild3:
2961 case OPC_MoveChild4: case OPC_MoveChild5:
2962 case OPC_MoveChild6: case OPC_MoveChild7: {
2963 unsigned ChildNo = Opcode-OPC_MoveChild0;
2964 if (ChildNo >= N.getNumOperands())
2965 break; // Match fails if out of range child #.
2966 N = N.getOperand(ChildNo);
2967 NodeStack.push_back(N);
2968 continue;
2969 }
2970
2971 case OPC_MoveParent:
2972 // Pop the current node off the NodeStack.
2973 NodeStack.pop_back();
2974 assert(!NodeStack.empty() && "Node stack imbalance!");
2975 N = NodeStack.back();
2976 continue;
2977
2978 case OPC_CheckSame:
2979 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2980 continue;
2981
2982 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2983 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2984 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2985 Opcode-OPC_CheckChild0Same))
2986 break;
2987 continue;
2988
2989 case OPC_CheckPatternPredicate:
2990 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2991 continue;
2992 case OPC_CheckPredicate:
2993 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2994 N.getNode()))
2995 break;
2996 continue;
2997 case OPC_CheckComplexPat: {
2998 unsigned CPNum = MatcherTable[MatcherIndex++];
2999 unsigned RecNo = MatcherTable[MatcherIndex++];
3000 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
3001
3002 // If target can modify DAG during matching, keep the matching state
3003 // consistent.
3004 std::unique_ptr<MatchStateUpdater> MSU;
3005 if (ComplexPatternFuncMutatesDAG())
3006 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
3007 MatchScopes));
3008
3009 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
3010 RecordedNodes[RecNo].first, CPNum,
3011 RecordedNodes))
3012 break;
3013 continue;
3014 }
3015 case OPC_CheckOpcode:
3016 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
3017 continue;
3018
3019 case OPC_CheckType:
3020 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI,
3021 CurDAG->getDataLayout()))
3022 break;
3023 continue;
3024
3025 case OPC_SwitchOpcode: {
3026 unsigned CurNodeOpcode = N.getOpcode();
3027 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
3028 unsigned CaseSize;
3029 while (1) {
3030 // Get the size of this case.
3031 CaseSize = MatcherTable[MatcherIndex++];
3032 if (CaseSize & 128)
3033 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
3034 if (CaseSize == 0) break;
3035
3036 uint16_t Opc = MatcherTable[MatcherIndex++];
3037 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3038
3039 // If the opcode matches, then we will execute this case.
3040 if (CurNodeOpcode == Opc)
3041 break;
3042
3043 // Otherwise, skip over this case.
3044 MatcherIndex += CaseSize;
3045 }
3046
3047 // If no cases matched, bail out.
3048 if (CaseSize == 0) break;
3049
3050 // Otherwise, execute the case we found.
3051 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
3052 << " to " << MatcherIndex << "\n");
3053 continue;
3054 }
3055
3056 case OPC_SwitchType: {
3057 MVT CurNodeVT = N.getSimpleValueType();
3058 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
3059 unsigned CaseSize;
3060 while (1) {
3061 // Get the size of this case.
3062 CaseSize = MatcherTable[MatcherIndex++];
3063 if (CaseSize & 128)
3064 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
3065 if (CaseSize == 0) break;
3066
3067 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3068 if (CaseVT == MVT::iPTR)
3069 CaseVT = TLI->getPointerTy(CurDAG->getDataLayout());
3070
3071 // If the VT matches, then we will execute this case.
3072 if (CurNodeVT == CaseVT)
3073 break;
3074
3075 // Otherwise, skip over this case.
3076 MatcherIndex += CaseSize;
3077 }
3078
3079 // If no cases matched, bail out.
3080 if (CaseSize == 0) break;
3081
3082 // Otherwise, execute the case we found.
3083 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
3084 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
3085 continue;
3086 }
3087 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
3088 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
3089 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
3090 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
3091 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
3092 CurDAG->getDataLayout(),
3093 Opcode - OPC_CheckChild0Type))
3094 break;
3095 continue;
3096 case OPC_CheckCondCode:
3097 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
3098 continue;
3099 case OPC_CheckValueType:
3100 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI,
3101 CurDAG->getDataLayout()))
3102 break;
3103 continue;
3104 case OPC_CheckInteger:
3105 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
3106 continue;
3107 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
3108 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
3109 case OPC_CheckChild4Integer:
3110 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
3111 Opcode-OPC_CheckChild0Integer)) break;
3112 continue;
3113 case OPC_CheckAndImm:
3114 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
3115 continue;
3116 case OPC_CheckOrImm:
3117 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
3118 continue;
3119
3120 case OPC_CheckFoldableChainNode: {
3121 assert(NodeStack.size() != 1 && "No parent node");
3122 // Verify that all intermediate nodes between the root and this one have
3123 // a single use.
3124 bool HasMultipleUses = false;
3125 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
3126 if (!NodeStack[i].hasOneUse()) {
3127 HasMultipleUses = true;
3128 break;
3129 }
3130 if (HasMultipleUses) break;
3131
3132 // Check to see that the target thinks this is profitable to fold and that
3133 // we can fold it without inducing cycles in the graph.
3134 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
3135 NodeToMatch) ||
3136 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
3137 NodeToMatch, OptLevel,
3138 true/*We validate our own chains*/))
3139 break;
3140
3141 continue;
3142 }
3143 case OPC_EmitInteger: {
3144 MVT::SimpleValueType VT =
3145 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3146 int64_t Val = MatcherTable[MatcherIndex++];
3147 if (Val & 128)
3148 Val = GetVBR(Val, MatcherTable, MatcherIndex);
3149 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3150 CurDAG->getTargetConstant(Val, SDLoc(NodeToMatch),
3151 VT), nullptr));
3152 continue;
3153 }
3154 case OPC_EmitRegister: {
3155 MVT::SimpleValueType VT =
3156 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3157 unsigned RegNo = MatcherTable[MatcherIndex++];
3158 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3159 CurDAG->getRegister(RegNo, VT), nullptr));
3160 continue;
3161 }
3162 case OPC_EmitRegister2: {
3163 // For targets w/ more than 256 register names, the register enum
3164 // values are stored in two bytes in the matcher table (just like
3165 // opcodes).
3166 MVT::SimpleValueType VT =
3167 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3168 unsigned RegNo = MatcherTable[MatcherIndex++];
3169 RegNo |= MatcherTable[MatcherIndex++] << 8;
3170 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3171 CurDAG->getRegister(RegNo, VT), nullptr));
3172 continue;
3173 }
3174
3175 case OPC_EmitConvertToTarget: {
3176 // Convert from IMM/FPIMM to target version.
3177 unsigned RecNo = MatcherTable[MatcherIndex++];
3178 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
3179 SDValue Imm = RecordedNodes[RecNo].first;
3180
3181 if (Imm->getOpcode() == ISD::Constant) {
3182 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
3183 Imm = CurDAG->getTargetConstant(*Val, SDLoc(NodeToMatch),
3184 Imm.getValueType());
3185 } else if (Imm->getOpcode() == ISD::ConstantFP) {
3186 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
3187 Imm = CurDAG->getTargetConstantFP(*Val, SDLoc(NodeToMatch),
3188 Imm.getValueType());
3189 }
3190
3191 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
3192 continue;
3193 }
3194
3195 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
3196 case OPC_EmitMergeInputChains1_1: // OPC_EmitMergeInputChains, 1, 1
3197 case OPC_EmitMergeInputChains1_2: { // OPC_EmitMergeInputChains, 1, 2
3198 // These are space-optimized forms of OPC_EmitMergeInputChains.
3199 assert(!InputChain.getNode() &&
3200 "EmitMergeInputChains should be the first chain producing node");
3201 assert(ChainNodesMatched.empty() &&
3202 "Should only have one EmitMergeInputChains per match");
3203
3204 // Read all of the chained nodes.
3205 unsigned RecNo = Opcode - OPC_EmitMergeInputChains1_0;
3206 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3207 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3208
3209 // FIXME: What if other value results of the node have uses not matched
3210 // by this pattern?
3211 if (ChainNodesMatched.back() != NodeToMatch &&
3212 !RecordedNodes[RecNo].first.hasOneUse()) {
3213 ChainNodesMatched.clear();
3214 break;
3215 }
3216
3217 // Merge the input chains if they are not intra-pattern references.
3218 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3219
3220 if (!InputChain.getNode())
3221 break; // Failed to merge.
3222 continue;
3223 }
3224
3225 case OPC_EmitMergeInputChains: {
3226 assert(!InputChain.getNode() &&
3227 "EmitMergeInputChains should be the first chain producing node");
3228 // This node gets a list of nodes we matched in the input that have
3229 // chains. We want to token factor all of the input chains to these nodes
3230 // together. However, if any of the input chains is actually one of the
3231 // nodes matched in this pattern, then we have an intra-match reference.
3232 // Ignore these because the newly token factored chain should not refer to
3233 // the old nodes.
3234 unsigned NumChains = MatcherTable[MatcherIndex++];
3235 assert(NumChains != 0 && "Can't TF zero chains");
3236
3237 assert(ChainNodesMatched.empty() &&
3238 "Should only have one EmitMergeInputChains per match");
3239
3240 // Read all of the chained nodes.
3241 for (unsigned i = 0; i != NumChains; ++i) {
3242 unsigned RecNo = MatcherTable[MatcherIndex++];
3243 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3244 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3245
3246 // FIXME: What if other value results of the node have uses not matched
3247 // by this pattern?
3248 if (ChainNodesMatched.back() != NodeToMatch &&
3249 !RecordedNodes[RecNo].first.hasOneUse()) {
3250 ChainNodesMatched.clear();
3251 break;
3252 }
3253 }
3254
3255 // If the inner loop broke out, the match fails.
3256 if (ChainNodesMatched.empty())
3257 break;
3258
3259 // Merge the input chains if they are not intra-pattern references.
3260 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3261
3262 if (!InputChain.getNode())
3263 break; // Failed to merge.
3264
3265 continue;
3266 }
3267
3268 case OPC_EmitCopyToReg: {
3269 unsigned RecNo = MatcherTable[MatcherIndex++];
3270 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3271 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3272
3273 if (!InputChain.getNode())
3274 InputChain = CurDAG->getEntryNode();
3275
3276 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3277 DestPhysReg, RecordedNodes[RecNo].first,
3278 InputGlue);
3279
3280 InputGlue = InputChain.getValue(1);
3281 continue;
3282 }
3283
3284 case OPC_EmitNodeXForm: {
3285 unsigned XFormNo = MatcherTable[MatcherIndex++];
3286 unsigned RecNo = MatcherTable[MatcherIndex++];
3287 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3288 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3289 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3290 continue;
3291 }
3292
3293 case OPC_EmitNode: case OPC_MorphNodeTo:
3294 case OPC_EmitNode0: case OPC_EmitNode1: case OPC_EmitNode2:
3295 case OPC_MorphNodeTo0: case OPC_MorphNodeTo1: case OPC_MorphNodeTo2: {
3296 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3297 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3298 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3299 // Get the result VT list.
3300 unsigned NumVTs;
3301 // If this is one of the compressed forms, get the number of VTs based
3302 // on the Opcode. Otherwise read the next byte from the table.
3303 if (Opcode >= OPC_MorphNodeTo0 && Opcode <= OPC_MorphNodeTo2)
3304 NumVTs = Opcode - OPC_MorphNodeTo0;
3305 else if (Opcode >= OPC_EmitNode0 && Opcode <= OPC_EmitNode2)
3306 NumVTs = Opcode - OPC_EmitNode0;
3307 else
3308 NumVTs = MatcherTable[MatcherIndex++];
3309 SmallVector<EVT, 4> VTs;
3310 for (unsigned i = 0; i != NumVTs; ++i) {
3311 MVT::SimpleValueType VT =
3312 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3313 if (VT == MVT::iPTR)
3314 VT = TLI->getPointerTy(CurDAG->getDataLayout()).SimpleTy;
3315 VTs.push_back(VT);
3316 }
3317
3318 if (EmitNodeInfo & OPFL_Chain)
3319 VTs.push_back(MVT::Other);
3320 if (EmitNodeInfo & OPFL_GlueOutput)
3321 VTs.push_back(MVT::Glue);
3322
3323 // This is hot code, so optimize the two most common cases of 1 and 2
3324 // results.
3325 SDVTList VTList;
3326 if (VTs.size() == 1)
3327 VTList = CurDAG->getVTList(VTs[0]);
3328 else if (VTs.size() == 2)
3329 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3330 else
3331 VTList = CurDAG->getVTList(VTs);
3332
3333 // Get the operand list.
3334 unsigned NumOps = MatcherTable[MatcherIndex++];
3335 SmallVector<SDValue, 8> Ops;
3336 for (unsigned i = 0; i != NumOps; ++i) {
3337 unsigned RecNo = MatcherTable[MatcherIndex++];
3338 if (RecNo & 128)
3339 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3340
3341 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3342 Ops.push_back(RecordedNodes[RecNo].first);
3343 }
3344
3345 // If there are variadic operands to add, handle them now.
3346 if (EmitNodeInfo & OPFL_VariadicInfo) {
3347 // Determine the start index to copy from.
3348 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3349 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3350 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3351 "Invalid variadic node");
3352 // Copy all of the variadic operands, not including a potential glue
3353 // input.
3354 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3355 i != e; ++i) {
3356 SDValue V = NodeToMatch->getOperand(i);
3357 if (V.getValueType() == MVT::Glue) break;
3358 Ops.push_back(V);
3359 }
3360 }
3361
3362 // If this has chain/glue inputs, add them.
3363 if (EmitNodeInfo & OPFL_Chain)
3364 Ops.push_back(InputChain);
3365 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3366 Ops.push_back(InputGlue);
3367
3368 // Create the node.
3369 SDNode *Res = nullptr;
3370 bool IsMorphNodeTo = Opcode == OPC_MorphNodeTo ||
3371 (Opcode >= OPC_MorphNodeTo0 && Opcode <= OPC_MorphNodeTo2);
3372 if (!IsMorphNodeTo) {
3373 // If this is a normal EmitNode command, just create the new node and
3374 // add the results to the RecordedNodes list.
3375 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3376 VTList, Ops);
3377
3378 // Add all the non-glue/non-chain results to the RecordedNodes list.
3379 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3380 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3381 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3382 nullptr));
3383 }
3384
3385 } else {
3386 assert(NodeToMatch->getOpcode() != ISD::DELETED_NODE &&
3387 "NodeToMatch was removed partway through selection");
3388 SelectionDAG::DAGNodeDeletedListener NDL(*CurDAG, [&](SDNode *N,
3389 SDNode *E) {
3390 auto &Chain = ChainNodesMatched;
3391 assert((!E || llvm::find(Chain, N) == Chain.end()) &&
3392 "Chain node replaced during MorphNode");
3393 Chain.erase(std::remove(Chain.begin(), Chain.end(), N), Chain.end());
3394 });
3395 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3396 }
3397
3398 // If the node had chain/glue results, update our notion of the current
3399 // chain and glue.
3400 if (EmitNodeInfo & OPFL_GlueOutput) {
3401 InputGlue = SDValue(Res, VTs.size()-1);
3402 if (EmitNodeInfo & OPFL_Chain)
3403 InputChain = SDValue(Res, VTs.size()-2);
3404 } else if (EmitNodeInfo & OPFL_Chain)
3405 InputChain = SDValue(Res, VTs.size()-1);
3406
3407 // If the OPFL_MemRefs glue is set on this node, slap all of the
3408 // accumulated memrefs onto it.
3409 //
3410 // FIXME: This is vastly incorrect for patterns with multiple outputs
3411 // instructions that access memory and for ComplexPatterns that match
3412 // loads.
3413 if (EmitNodeInfo & OPFL_MemRefs) {
3414 // Only attach load or store memory operands if the generated
3415 // instruction may load or store.
3416 const MCInstrDesc &MCID = TII->get(TargetOpc);
3417 bool mayLoad = MCID.mayLoad();
3418 bool mayStore = MCID.mayStore();
3419
3420 unsigned NumMemRefs = 0;
3421 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3422 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3423 if ((*I)->isLoad()) {
3424 if (mayLoad)
3425 ++NumMemRefs;
3426 } else if ((*I)->isStore()) {
3427 if (mayStore)
3428 ++NumMemRefs;
3429 } else {
3430 ++NumMemRefs;
3431 }
3432 }
3433
3434 MachineSDNode::mmo_iterator MemRefs =
3435 MF->allocateMemRefsArray(NumMemRefs);
3436
3437 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3438 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3439 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3440 if ((*I)->isLoad()) {
3441 if (mayLoad)
3442 *MemRefsPos++ = *I;
3443 } else if ((*I)->isStore()) {
3444 if (mayStore)
3445 *MemRefsPos++ = *I;
3446 } else {
3447 *MemRefsPos++ = *I;
3448 }
3449 }
3450
3451 cast<MachineSDNode>(Res)
3452 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3453 }
3454
3455 DEBUG(dbgs() << " "
3456 << (IsMorphNodeTo ? "Morphed" : "Created")
3457 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3458
3459 // If this was a MorphNodeTo then we're completely done!
3460 if (IsMorphNodeTo) {
3461 // Update chain uses.
3462 UpdateChains(Res, InputChain, ChainNodesMatched, true);
3463 return;
3464 }
3465 continue;
3466 }
3467
3468 case OPC_CompleteMatch: {
3469 // The match has been completed, and any new nodes (if any) have been
3470 // created. Patch up references to the matched dag to use the newly
3471 // created nodes.
3472 unsigned NumResults = MatcherTable[MatcherIndex++];
3473
3474 for (unsigned i = 0; i != NumResults; ++i) {
3475 unsigned ResSlot = MatcherTable[MatcherIndex++];
3476 if (ResSlot & 128)
3477 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3478
3479 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3480 SDValue Res = RecordedNodes[ResSlot].first;
3481
3482 assert(i < NodeToMatch->getNumValues() &&
3483 NodeToMatch->getValueType(i) != MVT::Other &&
3484 NodeToMatch->getValueType(i) != MVT::Glue &&
3485 "Invalid number of results to complete!");
3486 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3487 NodeToMatch->getValueType(i) == MVT::iPTR ||
3488 Res.getValueType() == MVT::iPTR ||
3489 NodeToMatch->getValueType(i).getSizeInBits() ==
3490 Res.getValueType().getSizeInBits()) &&
3491 "invalid replacement");
3492 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3493 }
3494
3495 // Update chain uses.
3496 UpdateChains(NodeToMatch, InputChain, ChainNodesMatched, false);
3497
3498 // If the root node defines glue, we need to update it to the glue result.
3499 // TODO: This never happens in our tests and I think it can be removed /
3500 // replaced with an assert, but if we do it this the way the change is
3501 // NFC.
3502 if (NodeToMatch->getValueType(NodeToMatch->getNumValues() - 1) ==
3503 MVT::Glue &&
3504 InputGlue.getNode())
3505 CurDAG->ReplaceAllUsesOfValueWith(
3506 SDValue(NodeToMatch, NodeToMatch->getNumValues() - 1), InputGlue);
3507
3508 assert(NodeToMatch->use_empty() &&
3509 "Didn't replace all uses of the node?");
3510 CurDAG->RemoveDeadNode(NodeToMatch);
3511
3512 return;
3513 }
3514 }
3515
3516 // If the code reached this point, then the match failed. See if there is
3517 // another child to try in the current 'Scope', otherwise pop it until we
3518 // find a case to check.
3519 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3520 ++NumDAGIselRetries;
3521 while (1) {
3522 if (MatchScopes.empty()) {
3523 CannotYetSelect(NodeToMatch);
3524 return;
3525 }
3526
3527 // Restore the interpreter state back to the point where the scope was
3528 // formed.
3529 MatchScope &LastScope = MatchScopes.back();
3530 RecordedNodes.resize(LastScope.NumRecordedNodes);
3531 NodeStack.clear();
3532 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3533 N = NodeStack.back();
3534
3535 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3536 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3537 MatcherIndex = LastScope.FailIndex;
3538
3539 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3540
3541 InputChain = LastScope.InputChain;
3542 InputGlue = LastScope.InputGlue;
3543 if (!LastScope.HasChainNodesMatched)
3544 ChainNodesMatched.clear();
3545
3546 // Check to see what the offset is at the new MatcherIndex. If it is zero
3547 // we have reached the end of this scope, otherwise we have another child
3548 // in the current scope to try.
3549 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3550 if (NumToSkip & 128)
3551 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3552
3553 // If we have another child in this scope to match, update FailIndex and
3554 // try it.
3555 if (NumToSkip != 0) {
3556 LastScope.FailIndex = MatcherIndex+NumToSkip;
3557 break;
3558 }
3559
3560 // End of this scope, pop it and try the next child in the containing
3561 // scope.
3562 MatchScopes.pop_back();
3563 }
3564 }
3565 }
3566
CannotYetSelect(SDNode * N)3567 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3568 std::string msg;
3569 raw_string_ostream Msg(msg);
3570 Msg << "Cannot select: ";
3571
3572 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3573 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3574 N->getOpcode() != ISD::INTRINSIC_VOID) {
3575 N->printrFull(Msg, CurDAG);
3576 Msg << "\nIn function: " << MF->getName();
3577 } else {
3578 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3579 unsigned iid =
3580 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3581 if (iid < Intrinsic::num_intrinsics)
3582 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3583 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3584 Msg << "target intrinsic %" << TII->getName(iid);
3585 else
3586 Msg << "unknown intrinsic #" << iid;
3587 }
3588 report_fatal_error(Msg.str());
3589 }
3590
3591 char SelectionDAGISel::ID = 0;
3592