1 //===-- R600MachineScheduler.h - R600 Scheduler Interface -*- C++ -*-------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief R600 Machine Scheduler interface
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
16 #define LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
17 
18 #include "llvm/CodeGen/MachineScheduler.h"
19 
20 using namespace llvm;
21 
22 namespace llvm {
23 
24 class R600InstrInfo;
25 struct R600RegisterInfo;
26 
27 class R600SchedStrategy final : public MachineSchedStrategy {
28   const ScheduleDAGMILive *DAG;
29   const R600InstrInfo *TII;
30   const R600RegisterInfo *TRI;
31   MachineRegisterInfo *MRI;
32 
33   enum InstKind {
34     IDAlu,
35     IDFetch,
36     IDOther,
37     IDLast
38   };
39 
40   enum AluKind {
41     AluAny,
42     AluT_X,
43     AluT_Y,
44     AluT_Z,
45     AluT_W,
46     AluT_XYZW,
47     AluPredX,
48     AluTrans,
49     AluDiscarded, // LLVM Instructions that are going to be eliminated
50     AluLast
51   };
52 
53   std::vector<SUnit *> Available[IDLast], Pending[IDLast];
54   std::vector<SUnit *> AvailableAlus[AluLast];
55   std::vector<SUnit *> PhysicalRegCopy;
56 
57   InstKind CurInstKind;
58   int CurEmitted;
59   InstKind NextInstKind;
60 
61   unsigned AluInstCount;
62   unsigned FetchInstCount;
63 
64   int InstKindLimit[IDLast];
65 
66   int OccupedSlotsMask;
67 
68 public:
R600SchedStrategy()69   R600SchedStrategy() :
70     DAG(nullptr), TII(nullptr), TRI(nullptr), MRI(nullptr) {
71   }
72 
~R600SchedStrategy()73   virtual ~R600SchedStrategy() {}
74 
75   void initialize(ScheduleDAGMI *dag) override;
76   SUnit *pickNode(bool &IsTopNode) override;
77   void schedNode(SUnit *SU, bool IsTopNode) override;
78   void releaseTopNode(SUnit *SU) override;
79   void releaseBottomNode(SUnit *SU) override;
80 
81 private:
82   std::vector<MachineInstr *> InstructionsGroupCandidate;
83   bool VLIW5;
84 
85   int getInstKind(SUnit *SU);
86   bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const;
87   AluKind getAluKind(SUnit *SU) const;
88   void LoadAlu();
89   unsigned AvailablesAluCount() const;
90   SUnit *AttemptFillSlot (unsigned Slot, bool AnyAlu);
91   void PrepareNextSlot();
92   SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);
93 
94   void AssignSlot(MachineInstr *MI, unsigned Slot);
95   SUnit* pickAlu();
96   SUnit* pickOther(int QID);
97   void MoveUnits(std::vector<SUnit *> &QSrc, std::vector<SUnit *> &QDst);
98 };
99 
100 } // namespace llvm
101 
102 #endif /* R600MACHINESCHEDULER_H_ */
103