1//===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10class DspMMRel;
11
12def Dsp2MicroMips : InstrMapping {
13  let FilterClass = "DspMMRel";
14  // Instructions with the same BaseOpcode and isNVStore values form a row.
15  let RowFields = ["BaseOpcode"];
16  // Instructions with the same predicate sense form a column.
17  let ColFields = ["Arch"];
18  // The key column is the unpredicated instructions.
19  let KeyCol = ["dsp"];
20  // Value columns are PredSense=true and PredSense=false
21  let ValueCols = [["dsp"], ["mmdsp"]];
22}
23
24def HasDSP : Predicate<"Subtarget->hasDSP()">,
25             AssemblerPredicate<"FeatureDSP">;
26def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
27               AssemblerPredicate<"FeatureDSPR2">;
28def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">,
29               AssemblerPredicate<"FeatureDSPR3">;
30
31class ISA_DSPR2 {
32  list<Predicate> InsnPredicates = [HasDSPR2];
33}
34
35class ISA_DSPR3 {
36  list<Predicate> InsnPredicates = [HasDSPR3];
37}
38
39// Fields.
40class Field6<bits<6> val> {
41  bits<6> V = val;
42}
43
44def SPECIAL3_OPCODE : Field6<0b011111>;
45def REGIMM_OPCODE : Field6<0b000001>;
46
47class DSPInst<string opstr = "">
48    : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
49  let InsnPredicates = [HasDSP];
50  string BaseOpcode = opstr;
51  string Arch = "dsp";
52}
53
54class PseudoDSP<dag outs, dag ins, list<dag> pattern,
55                InstrItinClass itin = IIPseudo>
56    : MipsPseudo<outs, ins, pattern, itin>, PredicateControl {
57  let InsnPredicates = [HasDSP];
58}
59
60class DSPInstAlias<string Asm, dag Result, bit Emit = 0b1>
61    : InstAlias<Asm, Result, Emit>, PredicateControl {
62  let InsnPredicates = [HasDSP];
63}
64
65// ADDU.QB sub-class format.
66class ADDU_QB_FMT<bits<5> op> : DSPInst {
67  bits<5> rd;
68  bits<5> rs;
69  bits<5> rt;
70
71  let Opcode = SPECIAL3_OPCODE.V;
72
73  let Inst{25-21} = rs;
74  let Inst{20-16} = rt;
75  let Inst{15-11} = rd;
76  let Inst{10-6}  = op;
77  let Inst{5-0}   = 0b010000;
78}
79
80class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
81  bits<5> rd;
82  bits<5> rs;
83
84  let Opcode = SPECIAL3_OPCODE.V;
85
86  let Inst{25-21} = rs;
87  let Inst{20-16} = 0;
88  let Inst{15-11} = rd;
89  let Inst{10-6}  = op;
90  let Inst{5-0}   = 0b010000;
91}
92
93// CMPU.EQ.QB sub-class format.
94class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
95  bits<5> rs;
96  bits<5> rt;
97
98  let Opcode = SPECIAL3_OPCODE.V;
99
100  let Inst{25-21} = rs;
101  let Inst{20-16} = rt;
102  let Inst{15-11} = 0;
103  let Inst{10-6}  = op;
104  let Inst{5-0}   = 0b010001;
105}
106
107class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst {
108  bits<5> rs;
109  bits<5> rt;
110  bits<5> rd;
111
112  let Opcode = SPECIAL3_OPCODE.V;
113
114  let Inst{25-21} = rs;
115  let Inst{20-16} = rt;
116  let Inst{15-11} = rd;
117  let Inst{10-6}  = op;
118  let Inst{5-0}   = 0b010001;
119}
120
121class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
122  bits<5> rs;
123  bits<5> rt;
124  bits<5> sa;
125
126  let Opcode = SPECIAL3_OPCODE.V;
127
128  let Inst{25-21} = rs;
129  let Inst{20-16} = rt;
130  let Inst{15-11} = sa;
131  let Inst{10-6}  = op;
132  let Inst{5-0}   = 0b010001;
133}
134
135// ABSQ_S.PH sub-class format.
136class ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst {
137  bits<5> rd;
138  bits<5> rt;
139
140  let Opcode = SPECIAL3_OPCODE.V;
141
142  let Inst{25-21} = 0;
143  let Inst{20-16} = rt;
144  let Inst{15-11} = rd;
145  let Inst{10-6}  = op;
146  let Inst{5-0}   = 0b010010;
147}
148
149
150class REPL_FMT<bits<5> op> : DSPInst {
151  bits<5> rd;
152  bits<10> imm;
153
154  let Opcode = SPECIAL3_OPCODE.V;
155
156  let Inst{25-16} = imm;
157  let Inst{15-11} = rd;
158  let Inst{10-6}  = op;
159  let Inst{5-0}   = 0b010010;
160}
161
162// SHLL.QB sub-class format.
163class SHLL_QB_FMT<bits<5> op> : DSPInst {
164  bits<5> rd;
165  bits<5> rt;
166  bits<5> rs_sa;
167
168  let Opcode = SPECIAL3_OPCODE.V;
169
170  let Inst{25-21} = rs_sa;
171  let Inst{20-16} = rt;
172  let Inst{15-11} = rd;
173  let Inst{10-6}  = op;
174  let Inst{5-0}   = 0b010011;
175}
176
177// LX sub-class format.
178class LX_FMT<bits<5> op> : DSPInst {
179  bits<5> rd;
180  bits<5> base;
181  bits<5> index;
182
183  let Opcode = SPECIAL3_OPCODE.V;
184
185  let Inst{25-21} = base;
186  let Inst{20-16} = index;
187  let Inst{15-11} = rd;
188  let Inst{10-6}  = op;
189  let Inst{5-0} = 0b001010;
190}
191
192// ADDUH.QB sub-class format.
193class ADDUH_QB_FMT<bits<5> op> : DSPInst {
194  bits<5> rd;
195  bits<5> rs;
196  bits<5> rt;
197
198  let Opcode = SPECIAL3_OPCODE.V;
199
200  let Inst{25-21} = rs;
201  let Inst{20-16} = rt;
202  let Inst{15-11} = rd;
203  let Inst{10-6} = op;
204  let Inst{5-0} = 0b011000;
205}
206
207// APPEND sub-class format.
208class APPEND_FMT<bits<5> op> : DSPInst {
209  bits<5> rt;
210  bits<5> rs;
211  bits<5> sa;
212
213  let Opcode = SPECIAL3_OPCODE.V;
214
215  let Inst{25-21} = rs;
216  let Inst{20-16} = rt;
217  let Inst{15-11} = sa;
218  let Inst{10-6} = op;
219  let Inst{5-0} = 0b110001;
220}
221
222// DPA.W.PH sub-class format.
223class DPA_W_PH_FMT<bits<5> op> : DSPInst {
224  bits<2> ac;
225  bits<5> rs;
226  bits<5> rt;
227
228  let Opcode = SPECIAL3_OPCODE.V;
229
230  let Inst{25-21} = rs;
231  let Inst{20-16} = rt;
232  let Inst{15-13} = 0;
233  let Inst{12-11} = ac;
234  let Inst{10-6}  = op;
235  let Inst{5-0} = 0b110000;
236}
237
238// MULT sub-class format.
239class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst {
240  bits<2> ac;
241  bits<5> rs;
242  bits<5> rt;
243
244  let Opcode = opcode;
245
246  let Inst{25-21} = rs;
247  let Inst{20-16} = rt;
248  let Inst{15-13} = 0;
249  let Inst{12-11} = ac;
250  let Inst{10-6}  = 0;
251  let Inst{5-0} = funct;
252}
253
254// MFHI sub-class format.
255class MFHI_FMT<bits<6> funct> : DSPInst {
256  bits<5> rd;
257  bits<2> ac;
258
259  let Inst{31-26} = 0;
260  let Inst{25-23} = 0;
261  let Inst{22-21} = ac;
262  let Inst{20-16} = 0;
263  let Inst{15-11} = rd;
264  let Inst{10-6} = 0;
265  let Inst{5-0} = funct;
266}
267
268// MTHI sub-class format.
269class MTHI_FMT<bits<6> funct> : DSPInst {
270  bits<5> rs;
271  bits<2> ac;
272
273  let Inst{31-26} = 0;
274  let Inst{25-21} = rs;
275  let Inst{20-13} = 0;
276  let Inst{12-11} = ac;
277  let Inst{10-6} = 0;
278  let Inst{5-0} = funct;
279}
280
281// EXTR.W sub-class format (type 1).
282class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
283  bits<5> rt;
284  bits<2> ac;
285  bits<5> shift_rs;
286
287  let Opcode = SPECIAL3_OPCODE.V;
288
289  let Inst{25-21} = shift_rs;
290  let Inst{20-16} = rt;
291  let Inst{15-13} = 0;
292  let Inst{12-11} = ac;
293  let Inst{10-6} = op;
294  let Inst{5-0} = 0b111000;
295}
296
297// SHILO sub-class format.
298class SHILO_R1_FMT<bits<5> op> : DSPInst {
299  bits<2> ac;
300  bits<6> shift;
301
302  let Opcode = SPECIAL3_OPCODE.V;
303
304  let Inst{25-20} = shift;
305  let Inst{19-13} = 0;
306  let Inst{12-11} = ac;
307  let Inst{10-6} = op;
308  let Inst{5-0} = 0b111000;
309}
310
311class SHILO_R2_FMT<bits<5> op> : DSPInst {
312  bits<2> ac;
313  bits<5> rs;
314
315  let Opcode = SPECIAL3_OPCODE.V;
316
317  let Inst{25-21} = rs;
318  let Inst{20-13} = 0;
319  let Inst{12-11} = ac;
320  let Inst{10-6} = op;
321  let Inst{5-0} = 0b111000;
322}
323
324class RDDSP_FMT<bits<5> op> : DSPInst {
325  bits<5> rd;
326  bits<10> mask;
327
328  let Opcode = SPECIAL3_OPCODE.V;
329
330  let Inst{25-16} = mask;
331  let Inst{15-11} = rd;
332  let Inst{10-6} = op;
333  let Inst{5-0} = 0b111000;
334}
335
336class WRDSP_FMT<bits<5> op> : DSPInst {
337  bits<5> rs;
338  bits<10> mask;
339
340  let Opcode = SPECIAL3_OPCODE.V;
341
342  let Inst{25-21} = rs;
343  let Inst{20-11} = mask;
344  let Inst{10-6} = op;
345  let Inst{5-0} = 0b111000;
346}
347
348class BPOSGE32_FMT<bits<5> op> : DSPInst {
349  bits<16> offset;
350
351  let Opcode = REGIMM_OPCODE.V;
352
353  let Inst{25-21} = 0;
354  let Inst{20-16} = op;
355  let Inst{15-0} = offset;
356}
357
358// INSV sub-class format.
359class INSV_FMT<bits<6> op> : DSPInst {
360  bits<5> rt;
361  bits<5> rs;
362
363  let Opcode = SPECIAL3_OPCODE.V;
364
365  let Inst{25-21} = rs;
366  let Inst{20-16} = rt;
367  let Inst{15-6} = 0;
368  let Inst{5-0} = op;
369}
370