1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Stack allocation 12//===----------------------------------------------------------------------===// 13 14def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt), 15 [(callseq_start timm:$amt)]>; 16def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 17 [(callseq_end timm:$amt1, timm:$amt2)]>; 18 19let hasSideEffects = 0 in { 20 // Takes as input the value of the stack pointer after a dynamic allocation 21 // has been made. Sets the output to the address of the dynamically- 22 // allocated area itself, skipping the outgoing arguments. 23 // 24 // This expands to an LA or LAY instruction. We restrict the offset 25 // to the range of LA and keep the LAY range in reserve for when 26 // the size of the outgoing arguments is added. 27 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 28 [(set GR64:$dst, dynalloc12only:$src)]>; 29} 30 31//===----------------------------------------------------------------------===// 32// Control flow instructions 33//===----------------------------------------------------------------------===// 34 35// A return instruction (br %r14). 36let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 37 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 38 39// A conditional return instruction (bcr <cond>, %r14). 40let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 41 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 42 43// Fused compare and conditional returns. 44let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 45 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 46 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 47 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 48 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 49 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 50 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 51 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 52 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 53} 54 55// Unconditional branches. R1 is the condition-code mask (all 1s). 56let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in { 57 let isIndirectBranch = 1 in 58 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), 59 "br\t$R2", [(brind ADDR64:$R2)]>; 60 61 // An assembler extended mnemonic for BRC. 62 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2", 63 [(br bb:$I2)]>; 64 65 // An assembler extended mnemonic for BRCL. (The extension is "G" 66 // rather than "L" because "JL" is "Jump if Less".) 67 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>; 68} 69 70// FIXME: This trap instruction should be marked as isTerminator, but there is 71// currently a general bug that allows non-terminators to be placed between 72// terminators. Temporarily leave this unmarked until the bug is fixed. 73let isBarrier = 1, hasCtrlDep = 1 in { 74 def Trap : Alias<4, (outs), (ins), [(trap)]>; 75} 76 77let isTerminator = 1, hasCtrlDep = 1, Uses = [CC] in { 78 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 79} 80 81// Conditional branches. It's easier for LLVM to handle these branches 82// in their raw BRC/BRCL form, with the 4-bit condition-code mask being 83// the first operand. It seems friendlier to use mnemonic forms like 84// JE and JLH when writing out the assembly though. 85let isBranch = 1, isTerminator = 1, Uses = [CC] in { 86 let isCodeGenOnly = 1, CCMaskFirst = 1 in { 87 def BRC : InstRI<0xA74, (outs), (ins cond4:$valid, cond4:$R1, 88 brtarget16:$I2), "j$R1\t$I2", 89 [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>; 90 def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1, 91 brtarget32:$I2), "jg$R1\t$I2", []>; 92 let isIndirectBranch = 1 in 93 def BCR : InstRR<0x07, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2), 94 "b${R1}r\t$R2", []>; 95 } 96 def AsmBRC : InstRI<0xA74, (outs), (ins imm32zx4:$R1, brtarget16:$I2), 97 "brc\t$R1, $I2", []>; 98 def AsmBRCL : InstRIL<0xC04, (outs), (ins imm32zx4:$R1, brtarget32:$I2), 99 "brcl\t$R1, $I2", []>; 100 let isIndirectBranch = 1 in { 101 def AsmBC : InstRX<0x47, (outs), (ins imm32zx4:$R1, bdxaddr12only:$XBD2), 102 "bc\t$R1, $XBD2", []>; 103 def AsmBCR : InstRR<0x07, (outs), (ins imm32zx4:$R1, GR64:$R2), 104 "bcr\t$R1, $R2", []>; 105 } 106} 107 108def AsmNop : InstAlias<"nop\t$XBD", (AsmBC 0, bdxaddr12only:$XBD), 0>; 109def AsmNopR : InstAlias<"nopr\t$R", (AsmBCR 0, GR64:$R), 0>; 110 111// Fused compare-and-branch instructions. As for normal branches, 112// we handle these instructions internally in their raw CRJ-like form, 113// but use assembly macros like CRJE when writing them out. 114// 115// These instructions do not use or clobber the condition codes. 116// We nevertheless pretend that they clobber CC, so that we can lower 117// them to separate comparisons and BRCLs if the branch ends up being 118// out of range. 119multiclass CompareBranches<Operand ccmask, string pos1, string pos2> { 120 let isBranch = 1, isTerminator = 1, Defs = [CC] in { 121 def RJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3, 122 brtarget16:$RI4), 123 "crj"##pos1##"\t$R1, $R2"##pos2##", $RI4", []>; 124 def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3, 125 brtarget16:$RI4), 126 "cgrj"##pos1##"\t$R1, $R2"##pos2##", $RI4", []>; 127 def IJ : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3, 128 brtarget16:$RI4), 129 "cij"##pos1##"\t$R1, $I2"##pos2##", $RI4", []>; 130 def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3, 131 brtarget16:$RI4), 132 "cgij"##pos1##"\t$R1, $I2"##pos2##", $RI4", []>; 133 def LRJ : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3, 134 brtarget16:$RI4), 135 "clrj"##pos1##"\t$R1, $R2"##pos2##", $RI4", []>; 136 def LGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3, 137 brtarget16:$RI4), 138 "clgrj"##pos1##"\t$R1, $R2"##pos2##", $RI4", []>; 139 def LIJ : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3, 140 brtarget16:$RI4), 141 "clij"##pos1##"\t$R1, $I2"##pos2##", $RI4", []>; 142 def LGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3, 143 brtarget16:$RI4), 144 "clgij"##pos1##"\t$R1, $I2"##pos2##", $RI4", []>; 145 let isIndirectBranch = 1 in { 146 def RB : InstRRS<0xECF6, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3, 147 bdaddr12only:$BD4), 148 "crb"##pos1##"\t$R1, $R2"##pos2##", $BD4", []>; 149 def GRB : InstRRS<0xECE4, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3, 150 bdaddr12only:$BD4), 151 "cgrb"##pos1##"\t$R1, $R2"##pos2##", $BD4", []>; 152 def IB : InstRIS<0xECFE, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3, 153 bdaddr12only:$BD4), 154 "cib"##pos1##"\t$R1, $I2"##pos2##", $BD4", []>; 155 def GIB : InstRIS<0xECFC, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3, 156 bdaddr12only:$BD4), 157 "cgib"##pos1##"\t$R1, $I2"##pos2##", $BD4", []>; 158 def LRB : InstRRS<0xECF7, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3, 159 bdaddr12only:$BD4), 160 "clrb"##pos1##"\t$R1, $R2"##pos2##", $BD4", []>; 161 def LGRB : InstRRS<0xECE5, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3, 162 bdaddr12only:$BD4), 163 "clgrb"##pos1##"\t$R1, $R2"##pos2##", $BD4", []>; 164 def LIB : InstRIS<0xECFF, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3, 165 bdaddr12only:$BD4), 166 "clib"##pos1##"\t$R1, $I2"##pos2##", $BD4", []>; 167 def LGIB : InstRIS<0xECFD, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3, 168 bdaddr12only:$BD4), 169 "clgib"##pos1##"\t$R1, $I2"##pos2##", $BD4", []>; 170 } 171 } 172 173 let isTerminator = 1, hasCtrlDep = 1 in { 174 def RT : InstRRFc<0xB972, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3), 175 "crt"##pos1##"\t$R1, $R2"##pos2, []>; 176 def GRT : InstRRFc<0xB960, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3), 177 "cgrt"##pos1##"\t$R1, $R2"##pos2, []>; 178 def LRT : InstRRFc<0xB973, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3), 179 "clrt"##pos1##"\t$R1, $R2"##pos2, []>; 180 def LGRT : InstRRFc<0xB961, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3), 181 "clgrt"##pos1##"\t$R1, $R2"##pos2, []>; 182 def IT : InstRIEa<0xEC72, (outs), (ins GR32:$R1, imm32sx16:$I2, ccmask:$M3), 183 "cit"##pos1##"\t$R1, $I2"##pos2, []>; 184 def GIT : InstRIEa<0xEC70, (outs), (ins GR64:$R1, imm32sx16:$I2, ccmask:$M3), 185 "cgit"##pos1##"\t$R1, $I2"##pos2, []>; 186 def LFIT : InstRIEa<0xEC73, (outs), (ins GR32:$R1, imm32zx16:$I2, ccmask:$M3), 187 "clfit"##pos1##"\t$R1, $I2"##pos2, []>; 188 def LGIT : InstRIEa<0xEC71, (outs), (ins GR64:$R1, imm32zx16:$I2, ccmask:$M3), 189 "clgit"##pos1##"\t$R1, $I2"##pos2, []>; 190 } 191} 192let isCodeGenOnly = 1 in 193 defm C : CompareBranches<cond4, "$M3", "">; 194defm AsmC : CompareBranches<imm32zx4, "", ", $M3">; 195 196// Define AsmParser mnemonics for each general condition-code mask 197// (integer or floating-point) 198multiclass CondExtendedMnemonicA<bits<4> ccmask, string name> { 199 let isBranch = 1, isTerminator = 1, R1 = ccmask in { 200 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), 201 "j"##name##"\t$I2", []>; 202 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), 203 "jg"##name##"\t$I2", []>; 204 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), "b"##name##"r\t$R2", []>; 205 } 206 def LOCR : FixedCondUnaryRRF<"locr"##name, 0xB9F2, GR32, GR32, ccmask>; 207 def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>; 208 def LOCHI : FixedCondUnaryRIE<"lochi"##name, 0xEC42, GR64, imm32sx16, 209 ccmask>; 210 def LOCGHI: FixedCondUnaryRIE<"locghi"##name, 0xEC46, GR64, imm64sx16, 211 ccmask>; 212 def LOC : FixedCondUnaryRSY<"loc"##name, 0xEBF2, GR32, ccmask, 4>; 213 def LOCG : FixedCondUnaryRSY<"locg"##name, 0xEBE2, GR64, ccmask, 8>; 214 def STOC : FixedCondStoreRSY<"stoc"##name, 0xEBF3, GR32, ccmask, 4>; 215 def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>; 216} 217 218multiclass CondExtendedMnemonic<bits<4> ccmask, string name1, string name2> 219 : CondExtendedMnemonicA<ccmask, name1> { 220 let isAsmParserOnly = 1 in 221 defm Alt : CondExtendedMnemonicA<ccmask, name2>; 222} 223 224defm AsmO : CondExtendedMnemonicA<1, "o">; 225defm AsmH : CondExtendedMnemonic<2, "h", "p">; 226defm AsmNLE : CondExtendedMnemonicA<3, "nle">; 227defm AsmL : CondExtendedMnemonic<4, "l", "m">; 228defm AsmNHE : CondExtendedMnemonicA<5, "nhe">; 229defm AsmLH : CondExtendedMnemonicA<6, "lh">; 230defm AsmNE : CondExtendedMnemonic<7, "ne", "nz">; 231defm AsmE : CondExtendedMnemonic<8, "e", "z">; 232defm AsmNLH : CondExtendedMnemonicA<9, "nlh">; 233defm AsmHE : CondExtendedMnemonicA<10, "he">; 234defm AsmNL : CondExtendedMnemonic<11, "nl", "nm">; 235defm AsmLE : CondExtendedMnemonicA<12, "le">; 236defm AsmNH : CondExtendedMnemonic<13, "nh", "np">; 237defm AsmNO : CondExtendedMnemonicA<14, "no">; 238 239// Define AsmParser mnemonics for each integer condition-code mask. 240// This is like the list above, except that condition 3 is not possible 241// and that the low bit of the mask is therefore always 0. This means 242// that each condition has two names. Conditions "o" and "no" are not used. 243// 244// We don't make one of the two names an alias of the other because 245// we need the custom parsing routines to select the correct register class. 246multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> { 247 let isBranch = 1, isTerminator = 1, M3 = ccmask in { 248 def CRJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, 249 brtarget16:$RI4), 250 "crj"##name##"\t$R1, $R2, $RI4", []>; 251 def CGRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, 252 brtarget16:$RI4), 253 "cgrj"##name##"\t$R1, $R2, $RI4", []>; 254 def CIJ : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, 255 brtarget16:$RI4), 256 "cij"##name##"\t$R1, $I2, $RI4", []>; 257 def CGIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, 258 brtarget16:$RI4), 259 "cgij"##name##"\t$R1, $I2, $RI4", []>; 260 def CLRJ : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2, 261 brtarget16:$RI4), 262 "clrj"##name##"\t$R1, $R2, $RI4", []>; 263 def CLGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2, 264 brtarget16:$RI4), 265 "clgrj"##name##"\t$R1, $R2, $RI4", []>; 266 def CLIJ : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2, 267 brtarget16:$RI4), 268 "clij"##name##"\t$R1, $I2, $RI4", []>; 269 def CLGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, 270 brtarget16:$RI4), 271 "clgij"##name##"\t$R1, $I2, $RI4", []>; 272 let isIndirectBranch = 1 in { 273 def CRB : InstRRS<0xECF6, (outs), (ins GR32:$R1, GR32:$R2, 274 bdaddr12only:$BD4), 275 "crb"##name##"\t$R1, $R2, $BD4", []>; 276 def CGRB : InstRRS<0xECE4, (outs), (ins GR64:$R1, GR64:$R2, 277 bdaddr12only:$BD4), 278 "cgrb"##name##"\t$R1, $R2, $BD4", []>; 279 def CIB : InstRIS<0xECFE, (outs), (ins GR32:$R1, imm32sx8:$I2, 280 bdaddr12only:$BD4), 281 "cib"##name##"\t$R1, $I2, $BD4", []>; 282 def CGIB : InstRIS<0xECFC, (outs), (ins GR64:$R1, imm64sx8:$I2, 283 bdaddr12only:$BD4), 284 "cgib"##name##"\t$R1, $I2, $BD4", []>; 285 def CLRB : InstRRS<0xECF7, (outs), (ins GR32:$R1, GR32:$R2, 286 bdaddr12only:$BD4), 287 "clrb"##name##"\t$R1, $R2, $BD4", []>; 288 def CLGRB : InstRRS<0xECE5, (outs), (ins GR64:$R1, GR64:$R2, 289 bdaddr12only:$BD4), 290 "clgrb"##name##"\t$R1, $R2, $BD4", []>; 291 def CLIB : InstRIS<0xECFF, (outs), (ins GR32:$R1, imm32zx8:$I2, 292 bdaddr12only:$BD4), 293 "clib"##name##"\t$R1, $I2, $BD4", []>; 294 def CLGIB : InstRIS<0xECFD, (outs), (ins GR64:$R1, imm64zx8:$I2, 295 bdaddr12only:$BD4), 296 "clgib"##name##"\t$R1, $I2, $BD4", []>; 297 } 298 } 299 300 let hasCtrlDep = 1, isTerminator = 1, M3 = ccmask in { 301 def CRT : InstRRFc<0xB972, (outs), (ins GR32:$R1, GR32:$R2), 302 "crt"##name##"\t$R1, $R2", []>; 303 def CGRT : InstRRFc<0xB960, (outs), (ins GR64:$R1, GR64:$R2), 304 "cgrt"##name##"\t$R1, $R2", []>; 305 def CLRT : InstRRFc<0xB973, (outs), (ins GR32:$R1, GR32:$R2), 306 "clrt"##name##"\t$R1, $R2", []>; 307 def CLGRT : InstRRFc<0xB961, (outs), (ins GR64:$R1, GR64:$R2), 308 "clgrt"##name##"\t$R1, $R2", []>; 309 def CIT : InstRIEa<0xEC72, (outs), (ins GR32:$R1, imm32sx16:$I2), 310 "cit"##name##"\t$R1, $I2", []>; 311 def CGIT : InstRIEa<0xEC70, (outs), (ins GR64:$R1, imm32sx16:$I2), 312 "cgit"##name##"\t$R1, $I2", []>; 313 def CLFIT : InstRIEa<0xEC73, (outs), (ins GR32:$R1, imm32zx16:$I2), 314 "clfit"##name##"\t$R1, $I2", []>; 315 def CLGIT : InstRIEa<0xEC71, (outs), (ins GR64:$R1, imm32zx16:$I2), 316 "clgit"##name##"\t$R1, $I2", []>; 317 } 318} 319multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2> 320 : IntCondExtendedMnemonicA<ccmask, name1> { 321 let isAsmParserOnly = 1 in 322 defm Alt : IntCondExtendedMnemonicA<ccmask, name2>; 323} 324defm AsmJH : IntCondExtendedMnemonic<2, "h", "nle">; 325defm AsmJL : IntCondExtendedMnemonic<4, "l", "nhe">; 326defm AsmJLH : IntCondExtendedMnemonic<6, "lh", "ne">; 327defm AsmJE : IntCondExtendedMnemonic<8, "e", "nlh">; 328defm AsmJHE : IntCondExtendedMnemonic<10, "he", "nl">; 329defm AsmJLE : IntCondExtendedMnemonic<12, "le", "nh">; 330 331// Decrement a register and branch if it is nonzero. These don't clobber CC, 332// but we might need to split long branches into sequences that do. 333let Defs = [CC] in { 334 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 335 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 336} 337 338//===----------------------------------------------------------------------===// 339// Select instructions 340//===----------------------------------------------------------------------===// 341 342def Select32Mux : SelectWrapper<GRX32>, Requires<[FeatureHighWord]>; 343def Select32 : SelectWrapper<GR32>; 344def Select64 : SelectWrapper<GR64>; 345 346// We don't define 32-bit Mux stores because the low-only STOC should 347// always be used if possible. 348defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 349 nonvolatile_anyextloadi8, bdxaddr20only>, 350 Requires<[FeatureHighWord]>; 351defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 352 nonvolatile_anyextloadi16, bdxaddr20only>, 353 Requires<[FeatureHighWord]>; 354defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 355 nonvolatile_anyextloadi8, bdxaddr20only>; 356defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 357 nonvolatile_anyextloadi16, bdxaddr20only>; 358defm CondStore32 : CondStores<GR32, nonvolatile_store, 359 nonvolatile_load, bdxaddr20only>; 360 361defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 362 nonvolatile_anyextloadi8, bdxaddr20only>; 363defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 364 nonvolatile_anyextloadi16, bdxaddr20only>; 365defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 366 nonvolatile_anyextloadi32, bdxaddr20only>; 367defm CondStore64 : CondStores<GR64, nonvolatile_store, 368 nonvolatile_load, bdxaddr20only>; 369 370//===----------------------------------------------------------------------===// 371// Call instructions 372//===----------------------------------------------------------------------===// 373 374let isCall = 1, Defs = [R14D, CC] in { 375 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 376 [(z_call pcrel32:$I2)]>; 377 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 378 [(z_call ADDR64:$R2)]>; 379} 380 381// Sibling calls. Indirect sibling calls must be via R1, since R2 upwards 382// are argument registers and since branching to R0 is a no-op. 383let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 384 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 385 [(z_sibcall pcrel32:$I2)]>; 386 let Uses = [R1D] in 387 def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>; 388} 389 390let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 391 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 392 pcrel32:$I2), []>; 393 394 let Uses = [R1D] in 395 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 396} 397 398// Fused compare and conditional sibling calls. 399let isCall = 1, isTerminator = 1, isReturn = 1, Uses = [R1D] in { 400 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 401 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 402 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 403 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 404 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 405 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 406 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 407 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 408} 409 410// TLS calls. These will be lowered into a call to __tls_get_offset, 411// with an extra relocation specifying the TLS symbol. 412let isCall = 1, Defs = [R14D, CC] in { 413 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 414 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 415 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 416 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 417} 418 419// Define the general form of the call instructions for the asm parser. 420// These instructions don't hard-code %r14 as the return address register. 421// Allow an optional TLS marker symbol to generate TLS call relocations. 422let isCall = 1, Defs = [CC] in { 423 def BRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16tls:$I2), 424 "bras\t$R1, $I2", []>; 425 def BRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32tls:$I2), 426 "brasl\t$R1, $I2", []>; 427 def BASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2), 428 "basr\t$R1, $R2", []>; 429} 430 431//===----------------------------------------------------------------------===// 432// Move instructions 433//===----------------------------------------------------------------------===// 434 435// Register moves. 436let hasSideEffects = 0 in { 437 // Expands to LR, RISBHG or RISBLG, depending on the choice of registers. 438 def LRMux : UnaryRRPseudo<"l", null_frag, GRX32, GRX32>, 439 Requires<[FeatureHighWord]>; 440 def LR : UnaryRR <"l", 0x18, null_frag, GR32, GR32>; 441 def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>; 442} 443let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 444 def LTR : UnaryRR <"lt", 0x12, null_frag, GR32, GR32>; 445 def LTGR : UnaryRRE<"ltg", 0xB902, null_frag, GR64, GR64>; 446} 447 448// Move on condition. 449let isCodeGenOnly = 1, Uses = [CC] in { 450 def LOCR : CondUnaryRRF<"loc", 0xB9F2, GR32, GR32>; 451 def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>; 452} 453let Uses = [CC] in { 454 def AsmLOCR : AsmCondUnaryRRF<"loc", 0xB9F2, GR32, GR32>; 455 def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>; 456} 457let isCodeGenOnly = 1, Uses = [CC] in { 458 def LOCHI : CondUnaryRIE<"lochi", 0xEC42, GR32, imm32sx16>; 459 def LOCGHI : CondUnaryRIE<"locghi", 0xEC46, GR64, imm64sx16>; 460} 461let Uses = [CC] in { 462 def AsmLOCHI : AsmCondUnaryRIE<"lochi", 0xEC42, GR32, imm32sx16>; 463 def AsmLOCGHI : AsmCondUnaryRIE<"locghi", 0xEC46, GR64, imm64sx16>; 464} 465 466// Immediate moves. 467let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1, 468 isReMaterializable = 1 in { 469 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 470 // deopending on the choice of register. 471 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 472 Requires<[FeatureHighWord]>; 473 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 474 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 475 476 // Other 16-bit immediates. 477 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 478 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 479 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 480 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 481 482 // 32-bit immediates. 483 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 484 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 485 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 486} 487 488// Register loads. 489let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 490 // Expands to L, LY or LFH, depending on the choice of register. 491 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 492 Requires<[FeatureHighWord]>; 493 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 494 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 495 Requires<[FeatureHighWord]>; 496 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 497 498 // These instructions are split after register allocation, so we don't 499 // want a custom inserter. 500 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 501 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 502 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 503 } 504} 505let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 506 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 507 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 508} 509 510let canFoldAsLoad = 1 in { 511 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 512 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 513} 514 515// Load on condition. 516let isCodeGenOnly = 1, Uses = [CC] in { 517 def LOC : CondUnaryRSY<"loc", 0xEBF2, nonvolatile_load, GR32, 4>; 518 def LOCG : CondUnaryRSY<"locg", 0xEBE2, nonvolatile_load, GR64, 8>; 519} 520let Uses = [CC] in { 521 def AsmLOC : AsmCondUnaryRSY<"loc", 0xEBF2, GR32, 4>; 522 def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>; 523} 524 525// Register stores. 526let SimpleBDXStore = 1 in { 527 // Expands to ST, STY or STFH, depending on the choice of register. 528 def STMux : StoreRXYPseudo<store, GRX32, 4>, 529 Requires<[FeatureHighWord]>; 530 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 531 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 532 Requires<[FeatureHighWord]>; 533 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 534 535 // These instructions are split after register allocation, so we don't 536 // want a custom inserter. 537 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 538 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 539 [(store GR128:$src, bdxaddr20only128:$dst)]>; 540 } 541} 542def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 543def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 544 545// Store on condition. 546let isCodeGenOnly = 1, Uses = [CC] in { 547 def STOC : CondStoreRSY<"stoc", 0xEBF3, GR32, 4>; 548 def STOCG : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>; 549} 550let Uses = [CC] in { 551 def AsmSTOC : AsmCondStoreRSY<"stoc", 0xEBF3, GR32, 4>; 552 def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>; 553} 554 555// 8-bit immediate stores to 8-bit fields. 556defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 557 558// 16-bit immediate stores to 16-, 32- or 64-bit fields. 559def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 560def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 561def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 562 563// Memory-to-memory moves. 564let mayLoad = 1, mayStore = 1 in 565 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; 566 567// String moves. 568let mayLoad = 1, mayStore = 1, Defs = [CC] in 569 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 570 571//===----------------------------------------------------------------------===// 572// Sign extensions 573//===----------------------------------------------------------------------===// 574// 575// Note that putting these before zero extensions mean that we will prefer 576// them for anyextload*. There's not really much to choose between the two 577// either way, but signed-extending loads have a short LH and a long LHY, 578// while zero-extending loads have only the long LLH. 579// 580//===----------------------------------------------------------------------===// 581 582// 32-bit extensions from registers. 583let hasSideEffects = 0 in { 584 def LBR : UnaryRRE<"lb", 0xB926, sext8, GR32, GR32>; 585 def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>; 586} 587 588// 64-bit extensions from registers. 589let hasSideEffects = 0 in { 590 def LGBR : UnaryRRE<"lgb", 0xB906, sext8, GR64, GR64>; 591 def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>; 592 def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>; 593} 594let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 595 def LTGFR : UnaryRRE<"ltgf", 0xB912, null_frag, GR64, GR32>; 596 597// Match 32-to-64-bit sign extensions in which the source is already 598// in a 64-bit register. 599def : Pat<(sext_inreg GR64:$src, i32), 600 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 601 602// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 603// depending on the choice of register. 604def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 605 Requires<[FeatureHighWord]>; 606def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 607def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 608 Requires<[FeatureHighWord]>; 609 610// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 611// depending on the choice of register. 612def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 613 Requires<[FeatureHighWord]>; 614defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 615def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 616 Requires<[FeatureHighWord]>; 617def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 618 619// 64-bit extensions from memory. 620def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 621def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 622def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 623def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 624def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 625let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 626 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 627 628//===----------------------------------------------------------------------===// 629// Zero extensions 630//===----------------------------------------------------------------------===// 631 632// 32-bit extensions from registers. 633let hasSideEffects = 0 in { 634 // Expands to LLCR or RISB[LH]G, depending on the choice of registers. 635 def LLCRMux : UnaryRRPseudo<"llc", zext8, GRX32, GRX32>, 636 Requires<[FeatureHighWord]>; 637 def LLCR : UnaryRRE<"llc", 0xB994, zext8, GR32, GR32>; 638 // Expands to LLHR or RISB[LH]G, depending on the choice of registers. 639 def LLHRMux : UnaryRRPseudo<"llh", zext16, GRX32, GRX32>, 640 Requires<[FeatureHighWord]>; 641 def LLHR : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>; 642} 643 644// 64-bit extensions from registers. 645let hasSideEffects = 0 in { 646 def LLGCR : UnaryRRE<"llgc", 0xB984, zext8, GR64, GR64>; 647 def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>; 648 def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>; 649} 650 651// Match 32-to-64-bit zero extensions in which the source is already 652// in a 64-bit register. 653def : Pat<(and GR64:$src, 0xffffffff), 654 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 655 656// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 657// depending on the choice of register. 658def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 659 Requires<[FeatureHighWord]>; 660def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 661def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 662 Requires<[FeatureHighWord]>; 663 664// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 665// depending on the choice of register. 666def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 667 Requires<[FeatureHighWord]>; 668def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 669def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 670 Requires<[FeatureHighWord]>; 671def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 672 673// 64-bit extensions from memory. 674def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 675def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 676def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 677def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 678def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 679 680//===----------------------------------------------------------------------===// 681// Truncations 682//===----------------------------------------------------------------------===// 683 684// Truncations of 64-bit registers to 32-bit registers. 685def : Pat<(i32 (trunc GR64:$src)), 686 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 687 688// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 689// STC, STCY or STCH, depending on the choice of register. 690def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 691 Requires<[FeatureHighWord]>; 692defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 693def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 694 Requires<[FeatureHighWord]>; 695 696// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 697// STH, STHY or STHH, depending on the choice of register. 698def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 699 Requires<[FeatureHighWord]>; 700defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 701def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 702 Requires<[FeatureHighWord]>; 703def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 704 705// Truncations of 64-bit registers to memory. 706defm : StoreGR64Pair<STC, STCY, truncstorei8>; 707defm : StoreGR64Pair<STH, STHY, truncstorei16>; 708def : StoreGR64PC<STHRL, aligned_truncstorei16>; 709defm : StoreGR64Pair<ST, STY, truncstorei32>; 710def : StoreGR64PC<STRL, aligned_truncstorei32>; 711 712//===----------------------------------------------------------------------===// 713// Multi-register moves 714//===----------------------------------------------------------------------===// 715 716// Multi-register loads. 717defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 718def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 719def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 720 721// Multi-register stores. 722defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 723def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 724def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 725 726//===----------------------------------------------------------------------===// 727// Byte swaps 728//===----------------------------------------------------------------------===// 729 730// Byte-swapping register moves. 731let hasSideEffects = 0 in { 732 def LRVR : UnaryRRE<"lrv", 0xB91F, bswap, GR32, GR32>; 733 def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>; 734} 735 736// Byte-swapping loads. Unlike normal loads, these instructions are 737// allowed to access storage more than once. 738def LRVH : UnaryRXY<"lrvh", 0xE31F, z_lrvh, GR32, 2>; 739def LRV : UnaryRXY<"lrv", 0xE31E, z_lrv, GR32, 4>; 740def LRVG : UnaryRXY<"lrvg", 0xE30F, z_lrvg, GR64, 8>; 741 742// Likewise byte-swapping stores. 743def STRVH : StoreRXY<"strvh", 0xE33F, z_strvh, GR32, 2>; 744def STRV : StoreRXY<"strv", 0xE33E, z_strv, GR32, 4>; 745def STRVG : StoreRXY<"strvg", 0xE32F, z_strvg, GR64, 8>; 746 747//===----------------------------------------------------------------------===// 748// Load address instructions 749//===----------------------------------------------------------------------===// 750 751// Load BDX-style addresses. 752let hasSideEffects = 0, isAsCheapAsAMove = 1, isReMaterializable = 1, 753 DispKey = "la" in { 754 let DispSize = "12" in 755 def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2), 756 "la\t$R1, $XBD2", 757 [(set GR64:$R1, laaddr12pair:$XBD2)]>; 758 let DispSize = "20" in 759 def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2), 760 "lay\t$R1, $XBD2", 761 [(set GR64:$R1, laaddr20pair:$XBD2)]>; 762} 763 764// Load a PC-relative address. There's no version of this instruction 765// with a 16-bit offset, so there's no relaxation. 766let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1, 767 isReMaterializable = 1 in { 768 def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2), 769 "larl\t$R1, $I2", 770 [(set GR64:$R1, pcrel32:$I2)]>; 771} 772 773// Load the Global Offset Table address. This will be lowered into a 774// larl $R1, _GLOBAL_OFFSET_TABLE_ 775// instruction. 776def GOT : Alias<6, (outs GR64:$R1), (ins), 777 [(set GR64:$R1, (global_offset_table))]>; 778 779//===----------------------------------------------------------------------===// 780// Absolute and Negation 781//===----------------------------------------------------------------------===// 782 783let Defs = [CC] in { 784 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 785 def LPR : UnaryRR <"lp", 0x10, z_iabs, GR32, GR32>; 786 def LPGR : UnaryRRE<"lpg", 0xB900, z_iabs, GR64, GR64>; 787 } 788 let CCValues = 0xE, CompareZeroCCMask = 0xE in 789 def LPGFR : UnaryRRE<"lpgf", 0xB910, null_frag, GR64, GR32>; 790} 791def : Pat<(z_iabs32 GR32:$src), (LPR GR32:$src)>; 792def : Pat<(z_iabs64 GR64:$src), (LPGR GR64:$src)>; 793defm : SXU<z_iabs, LPGFR>; 794defm : SXU<z_iabs64, LPGFR>; 795 796let Defs = [CC] in { 797 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 798 def LNR : UnaryRR <"ln", 0x11, z_inegabs, GR32, GR32>; 799 def LNGR : UnaryRRE<"lng", 0xB901, z_inegabs, GR64, GR64>; 800 } 801 let CCValues = 0xE, CompareZeroCCMask = 0xE in 802 def LNGFR : UnaryRRE<"lngf", 0xB911, null_frag, GR64, GR32>; 803} 804def : Pat<(z_inegabs32 GR32:$src), (LNR GR32:$src)>; 805def : Pat<(z_inegabs64 GR64:$src), (LNGR GR64:$src)>; 806defm : SXU<z_inegabs, LNGFR>; 807defm : SXU<z_inegabs64, LNGFR>; 808 809let Defs = [CC] in { 810 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 811 def LCR : UnaryRR <"lc", 0x13, ineg, GR32, GR32>; 812 def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>; 813 } 814 let CCValues = 0xE, CompareZeroCCMask = 0xE in 815 def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>; 816} 817defm : SXU<ineg, LCGFR>; 818 819//===----------------------------------------------------------------------===// 820// Insertion 821//===----------------------------------------------------------------------===// 822 823let isCodeGenOnly = 1 in 824 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 825defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 826 827defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 828defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 829 830defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 831defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 832 833let Defs = [CC] in { 834 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 835 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 836} 837 838// Insertions of a 16-bit immediate, leaving other bits unaffected. 839// We don't have or_as_insert equivalents of these operations because 840// OI is available instead. 841// 842// IIxMux expands to II[LH]x, depending on the choice of register. 843def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 844 Requires<[FeatureHighWord]>; 845def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 846 Requires<[FeatureHighWord]>; 847def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 848def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 849def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 850def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 851def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 852def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 853def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 854def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 855 856// ...likewise for 32-bit immediates. For GR32s this is a general 857// full-width move. (We use IILF rather than something like LLILF 858// for 32-bit moves because IILF leaves the upper 32 bits of the 859// GR64 unchanged.) 860let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 861 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 862 Requires<[FeatureHighWord]>; 863 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 864 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 865} 866def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 867def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 868 869// An alternative model of inserthf, with the first operand being 870// a zero-extended value. 871def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 872 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 873 imm64hf32:$imm)>; 874 875//===----------------------------------------------------------------------===// 876// Addition 877//===----------------------------------------------------------------------===// 878 879// Plain addition. 880let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 881 // Addition of a register. 882 let isCommutable = 1 in { 883 defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>; 884 defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>; 885 } 886 def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>; 887 888 // Addition of signed 16-bit immediates. 889 defm AHIMux : BinaryRIAndKPseudo<"ahimux", add, GRX32, imm32sx16>; 890 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, add, GR32, imm32sx16>; 891 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>; 892 893 // Addition of signed 32-bit immediates. 894 def AFIMux : BinaryRIPseudo<add, GRX32, simm32>, 895 Requires<[FeatureHighWord]>; 896 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>; 897 def AIH : BinaryRIL<"aih", 0xCC8, add, GRH32, simm32>, 898 Requires<[FeatureHighWord]>; 899 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>; 900 901 // Addition of memory. 902 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>; 903 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load, 4>; 904 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>; 905 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load, 8>; 906 907 // Addition to memory. 908 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 909 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 910} 911defm : SXB<add, GR64, AGFR>; 912 913// Addition producing a carry. 914let Defs = [CC] in { 915 // Addition of a register. 916 let isCommutable = 1 in { 917 defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>; 918 defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>; 919 } 920 def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>; 921 922 // Addition of signed 16-bit immediates. 923 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, addc, GR32, imm32sx16>, 924 Requires<[FeatureDistinctOps]>; 925 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>, 926 Requires<[FeatureDistinctOps]>; 927 928 // Addition of unsigned 32-bit immediates. 929 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>; 930 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>; 931 932 // Addition of memory. 933 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>; 934 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, azextloadi32, 4>; 935 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load, 8>; 936} 937defm : ZXB<addc, GR64, ALGFR>; 938 939// Addition producing and using a carry. 940let Defs = [CC], Uses = [CC] in { 941 // Addition of a register. 942 def ALCR : BinaryRRE<"alc", 0xB998, adde, GR32, GR32>; 943 def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>; 944 945 // Addition of memory. 946 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load, 4>; 947 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>; 948} 949 950//===----------------------------------------------------------------------===// 951// Subtraction 952//===----------------------------------------------------------------------===// 953 954// Plain subtraction. Although immediate forms exist, we use the 955// add-immediate instruction instead. 956let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 957 // Subtraction of a register. 958 defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>; 959 def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>; 960 defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>; 961 962 // Subtraction of memory. 963 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>; 964 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>; 965 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>; 966 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load, 8>; 967} 968defm : SXB<sub, GR64, SGFR>; 969 970// Subtraction producing a carry. 971let Defs = [CC] in { 972 // Subtraction of a register. 973 defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>; 974 def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>; 975 defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>; 976 977 // Subtraction of unsigned 32-bit immediates. These don't match 978 // subc because we prefer addc for constants. 979 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>; 980 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>; 981 982 // Subtraction of memory. 983 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>; 984 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>; 985 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>; 986} 987defm : ZXB<subc, GR64, SLGFR>; 988 989// Subtraction producing and using a carry. 990let Defs = [CC], Uses = [CC] in { 991 // Subtraction of a register. 992 def SLBR : BinaryRRE<"slb", 0xB999, sube, GR32, GR32>; 993 def SLBGR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>; 994 995 // Subtraction of memory. 996 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>; 997 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>; 998} 999 1000//===----------------------------------------------------------------------===// 1001// AND 1002//===----------------------------------------------------------------------===// 1003 1004let Defs = [CC] in { 1005 // ANDs of a register. 1006 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1007 defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>; 1008 defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>; 1009 } 1010 1011 let isConvertibleToThreeAddress = 1 in { 1012 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1013 // The CC result only reflects the 16-bit field, not the full register. 1014 // 1015 // NIxMux expands to NI[LH]x, depending on the choice of register. 1016 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1017 Requires<[FeatureHighWord]>; 1018 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1019 Requires<[FeatureHighWord]>; 1020 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1021 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1022 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1023 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1024 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1025 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1026 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1027 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1028 1029 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1030 // The CC result only reflects the 32-bit field, which means we can 1031 // use it as a zero indicator for i32 operations but not otherwise. 1032 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1033 // Expands to NILF or NIHF, depending on the choice of register. 1034 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1035 Requires<[FeatureHighWord]>; 1036 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1037 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1038 } 1039 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1040 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1041 } 1042 1043 // ANDs of memory. 1044 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1045 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>; 1046 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>; 1047 } 1048 1049 // AND to memory 1050 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1051 1052 // Block AND. 1053 let mayLoad = 1, mayStore = 1 in 1054 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>; 1055} 1056defm : RMWIByte<and, bdaddr12pair, NI>; 1057defm : RMWIByte<and, bdaddr20pair, NIY>; 1058 1059//===----------------------------------------------------------------------===// 1060// OR 1061//===----------------------------------------------------------------------===// 1062 1063let Defs = [CC] in { 1064 // ORs of a register. 1065 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1066 defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>; 1067 defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>; 1068 } 1069 1070 // ORs of a 16-bit immediate, leaving other bits unaffected. 1071 // The CC result only reflects the 16-bit field, not the full register. 1072 // 1073 // OIxMux expands to OI[LH]x, depending on the choice of register. 1074 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1075 Requires<[FeatureHighWord]>; 1076 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1077 Requires<[FeatureHighWord]>; 1078 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1079 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1080 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1081 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1082 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1083 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1084 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1085 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1086 1087 // ORs of a 32-bit immediate, leaving other bits unaffected. 1088 // The CC result only reflects the 32-bit field, which means we can 1089 // use it as a zero indicator for i32 operations but not otherwise. 1090 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1091 // Expands to OILF or OIHF, depending on the choice of register. 1092 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1093 Requires<[FeatureHighWord]>; 1094 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1095 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1096 } 1097 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1098 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1099 1100 // ORs of memory. 1101 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1102 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>; 1103 def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>; 1104 } 1105 1106 // OR to memory 1107 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1108 1109 // Block OR. 1110 let mayLoad = 1, mayStore = 1 in 1111 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>; 1112} 1113defm : RMWIByte<or, bdaddr12pair, OI>; 1114defm : RMWIByte<or, bdaddr20pair, OIY>; 1115 1116//===----------------------------------------------------------------------===// 1117// XOR 1118//===----------------------------------------------------------------------===// 1119 1120let Defs = [CC] in { 1121 // XORs of a register. 1122 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1123 defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>; 1124 defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>; 1125 } 1126 1127 // XORs of a 32-bit immediate, leaving other bits unaffected. 1128 // The CC result only reflects the 32-bit field, which means we can 1129 // use it as a zero indicator for i32 operations but not otherwise. 1130 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1131 // Expands to XILF or XIHF, depending on the choice of register. 1132 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1133 Requires<[FeatureHighWord]>; 1134 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1135 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1136 } 1137 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1138 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1139 1140 // XORs of memory. 1141 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1142 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>; 1143 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>; 1144 } 1145 1146 // XOR to memory 1147 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1148 1149 // Block XOR. 1150 let mayLoad = 1, mayStore = 1 in 1151 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>; 1152} 1153defm : RMWIByte<xor, bdaddr12pair, XI>; 1154defm : RMWIByte<xor, bdaddr20pair, XIY>; 1155 1156//===----------------------------------------------------------------------===// 1157// Multiplication 1158//===----------------------------------------------------------------------===// 1159 1160// Multiplication of a register. 1161let isCommutable = 1 in { 1162 def MSR : BinaryRRE<"ms", 0xB252, mul, GR32, GR32>; 1163 def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>; 1164} 1165def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>; 1166defm : SXB<mul, GR64, MSGFR>; 1167 1168// Multiplication of a signed 16-bit immediate. 1169def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1170def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1171 1172// Multiplication of a signed 32-bit immediate. 1173def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1174def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1175 1176// Multiplication of memory. 1177defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1178defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1179def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1180def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1181 1182// Multiplication of a register, producing two results. 1183def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>; 1184 1185// Multiplication of memory, producing two results. 1186def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>; 1187 1188//===----------------------------------------------------------------------===// 1189// Division and remainder 1190//===----------------------------------------------------------------------===// 1191 1192// Division and remainder, from registers. 1193def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>; 1194def DSGR : BinaryRRE<"dsg", 0xB90D, z_sdivrem64, GR128, GR64>; 1195def DLR : BinaryRRE<"dl", 0xB997, z_udivrem32, GR128, GR32>; 1196def DLGR : BinaryRRE<"dlg", 0xB987, z_udivrem64, GR128, GR64>; 1197 1198// Division and remainder, from memory. 1199def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>; 1200def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load, 8>; 1201def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load, 4>; 1202def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load, 8>; 1203 1204//===----------------------------------------------------------------------===// 1205// Shifts 1206//===----------------------------------------------------------------------===// 1207 1208// Shift left. 1209let hasSideEffects = 0 in { 1210 defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>; 1211 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1212 def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>; 1213} 1214 1215// Logical shift right. 1216let hasSideEffects = 0 in { 1217 defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>; 1218 def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>; 1219} 1220 1221// Arithmetic shift right. 1222let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1223 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>; 1224 def SRAG : BinaryRSY<"srag", 0xEB0A, sra, GR64>; 1225} 1226 1227// Rotate left. 1228let hasSideEffects = 0 in { 1229 def RLL : BinaryRSY<"rll", 0xEB1D, rotl, GR32>; 1230 def RLLG : BinaryRSY<"rllg", 0xEB1C, rotl, GR64>; 1231} 1232 1233// Rotate second operand left and inserted selected bits into first operand. 1234// These can act like 32-bit operands provided that the constant start and 1235// end bits (operands 2 and 3) are in the range [32, 64). 1236let Defs = [CC] in { 1237 let isCodeGenOnly = 1 in 1238 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1239 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1240 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1241} 1242 1243// On zEC12 we have a variant of RISBG that does not set CC. 1244let Predicates = [FeatureMiscellaneousExtensions] in 1245 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1246 1247// Forms of RISBG that only affect one word of the destination register. 1248// They do not set CC. 1249let Predicates = [FeatureHighWord] in { 1250 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1251 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1252 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1253 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1254 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1255 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1256 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1257} 1258 1259// Rotate second operand left and perform a logical operation with selected 1260// bits of the first operand. The CC result only describes the selected bits, 1261// so isn't useful for a full comparison against zero. 1262let Defs = [CC] in { 1263 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1264 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1265 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1266} 1267 1268//===----------------------------------------------------------------------===// 1269// Comparison 1270//===----------------------------------------------------------------------===// 1271 1272// Signed comparisons. We put these before the unsigned comparisons because 1273// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1274// of the unsigned forms do. 1275let Defs = [CC], CCValues = 0xE in { 1276 // Comparison with a register. 1277 def CR : CompareRR <"c", 0x19, z_scmp, GR32, GR32>; 1278 def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>; 1279 def CGR : CompareRRE<"cg", 0xB920, z_scmp, GR64, GR64>; 1280 1281 // Comparison with a signed 16-bit immediate. 1282 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1283 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1284 1285 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1286 // depending on the choice of register. 1287 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1288 Requires<[FeatureHighWord]>; 1289 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1290 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1291 Requires<[FeatureHighWord]>; 1292 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1293 1294 // Comparison with memory. 1295 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1296 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1297 Requires<[FeatureHighWord]>; 1298 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1299 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1300 Requires<[FeatureHighWord]>; 1301 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1302 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1303 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1304 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1305 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1306 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1307 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1308 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1309 1310 // Comparison between memory and a signed 16-bit immediate. 1311 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1312 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1313 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1314} 1315defm : SXB<z_scmp, GR64, CGFR>; 1316 1317// Unsigned comparisons. 1318let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1319 // Comparison with a register. 1320 def CLR : CompareRR <"cl", 0x15, z_ucmp, GR32, GR32>; 1321 def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>; 1322 def CLGR : CompareRRE<"clg", 0xB921, z_ucmp, GR64, GR64>; 1323 1324 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1325 // or CLIH, depending on the choice of register. 1326 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1327 Requires<[FeatureHighWord]>; 1328 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1329 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1330 Requires<[FeatureHighWord]>; 1331 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1332 1333 // Comparison with memory. 1334 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1335 Requires<[FeatureHighWord]>; 1336 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1337 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1338 Requires<[FeatureHighWord]>; 1339 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1340 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1341 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1342 aligned_azextloadi16>; 1343 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1344 aligned_load>; 1345 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1346 aligned_azextloadi16>; 1347 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1348 aligned_azextloadi32>; 1349 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1350 aligned_load>; 1351 1352 // Comparison between memory and an unsigned 8-bit immediate. 1353 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1354 1355 // Comparison between memory and an unsigned 16-bit immediate. 1356 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1357 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1358 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1359} 1360defm : ZXB<z_ucmp, GR64, CLGFR>; 1361 1362// Memory-to-memory comparison. 1363let mayLoad = 1, Defs = [CC] in 1364 defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>; 1365 1366// String comparison. 1367let mayLoad = 1, Defs = [CC] in 1368 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1369 1370// Test under mask. 1371let Defs = [CC] in { 1372 // TMxMux expands to TM[LH]x, depending on the choice of register. 1373 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1374 Requires<[FeatureHighWord]>; 1375 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1376 Requires<[FeatureHighWord]>; 1377 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1378 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1379 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1380 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1381 1382 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1383 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1384 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1385 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1386 1387 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1388} 1389 1390def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1391def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1392 1393//===----------------------------------------------------------------------===// 1394// Prefetch 1395//===----------------------------------------------------------------------===// 1396 1397def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1398def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1399 1400//===----------------------------------------------------------------------===// 1401// Atomic operations 1402//===----------------------------------------------------------------------===// 1403 1404// A serialization instruction that acts as a barrier for all memory 1405// accesses, which expands to "bcr 14, 0". 1406let hasSideEffects = 1 in 1407def Serialize : Alias<2, (outs), (ins), [(z_serialize)]>; 1408 1409// A pseudo instruction that serves as a compiler barrier. 1410let hasSideEffects = 1 in 1411def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1412 1413let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1414 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1415 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1416 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1417 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1418 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1419 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1420 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1421 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1422 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1423 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1424} 1425 1426def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1427def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1428def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1429 1430def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1431def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1432let Predicates = [FeatureNoInterlockedAccess1] in { 1433 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1434 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1435 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1436 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1437 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1438 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1439} 1440 1441def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1442def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1443def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1444 1445def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1446def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1447let Predicates = [FeatureNoInterlockedAccess1] in { 1448 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1449 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1450 imm32ll16c>; 1451 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1452 imm32lh16c>; 1453 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1454 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1455 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1456 imm64ll16c>; 1457 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1458 imm64lh16c>; 1459 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1460 imm64hl16c>; 1461 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1462 imm64hh16c>; 1463 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1464 imm64lf32c>; 1465 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1466 imm64hf32c>; 1467} 1468 1469def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1470def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1471let Predicates = [FeatureNoInterlockedAccess1] in { 1472 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1473 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1474 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1475 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1476 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1477 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1478 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1479 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1480 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1481 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1482 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1483} 1484 1485def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1486def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1487let Predicates = [FeatureNoInterlockedAccess1] in { 1488 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1489 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1490 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1491 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1492 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1493} 1494 1495def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1496def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1497 imm32lh16c>; 1498def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1499def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1500 imm32ll16c>; 1501def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1502 imm32lh16c>; 1503def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1504def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1505def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1506 imm64ll16c>; 1507def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1508 imm64lh16c>; 1509def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1510 imm64hl16c>; 1511def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1512 imm64hh16c>; 1513def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1514 imm64lf32c>; 1515def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1516 imm64hf32c>; 1517 1518def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1519def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1520def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1521 1522def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1523def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1524def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1525 1526def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1527def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1528def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1529 1530def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1531def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1532def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1533 1534def ATOMIC_CMP_SWAPW 1535 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1536 ADDR32:$bitshift, ADDR32:$negbitshift, 1537 uimm32:$bitsize), 1538 [(set GR32:$dst, 1539 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1540 ADDR32:$bitshift, ADDR32:$negbitshift, 1541 uimm32:$bitsize))]> { 1542 let Defs = [CC]; 1543 let mayLoad = 1; 1544 let mayStore = 1; 1545 let usesCustomInserter = 1; 1546} 1547 1548let Defs = [CC] in { 1549 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>; 1550 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>; 1551} 1552 1553//===----------------------------------------------------------------------===// 1554// Transactional execution 1555//===----------------------------------------------------------------------===// 1556 1557let Predicates = [FeatureTransactionalExecution] in { 1558 // Transaction Begin 1559 let hasSideEffects = 1, mayStore = 1, 1560 usesCustomInserter = 1, Defs = [CC] in { 1561 def TBEGIN : InstSIL<0xE560, 1562 (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2), 1563 "tbegin\t$BD1, $I2", 1564 [(z_tbegin bdaddr12only:$BD1, imm32zx16:$I2)]>; 1565 def TBEGIN_nofloat : Pseudo<(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2), 1566 [(z_tbegin_nofloat bdaddr12only:$BD1, 1567 imm32zx16:$I2)]>; 1568 def TBEGINC : InstSIL<0xE561, 1569 (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2), 1570 "tbeginc\t$BD1, $I2", 1571 [(int_s390_tbeginc bdaddr12only:$BD1, 1572 imm32zx16:$I2)]>; 1573 } 1574 1575 // Transaction End 1576 let hasSideEffects = 1, Defs = [CC], BD2 = 0 in 1577 def TEND : InstS<0xB2F8, (outs), (ins), "tend", [(z_tend)]>; 1578 1579 // Transaction Abort 1580 let hasSideEffects = 1, isTerminator = 1, isBarrier = 1 in 1581 def TABORT : InstS<0xB2FC, (outs), (ins bdaddr12only:$BD2), 1582 "tabort\t$BD2", 1583 [(int_s390_tabort bdaddr12only:$BD2)]>; 1584 1585 // Nontransactional Store 1586 let hasSideEffects = 1 in 1587 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 1588 1589 // Extract Transaction Nesting Depth 1590 let hasSideEffects = 1 in 1591 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, (int_s390_etnd)>; 1592} 1593 1594//===----------------------------------------------------------------------===// 1595// Processor assist 1596//===----------------------------------------------------------------------===// 1597 1598let Predicates = [FeatureProcessorAssist] in { 1599 let hasSideEffects = 1, R4 = 0 in 1600 def PPA : InstRRF<0xB2E8, (outs), (ins GR64:$R1, GR64:$R2, imm32zx4:$R3), 1601 "ppa\t$R1, $R2, $R3", []>; 1602 def : Pat<(int_s390_ppa_txassist GR32:$src), 1603 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 1604 0, 1)>; 1605} 1606 1607//===----------------------------------------------------------------------===// 1608// Miscellaneous Instructions. 1609//===----------------------------------------------------------------------===// 1610 1611// Extract CC into bits 29 and 28 of a register. 1612let Uses = [CC] in 1613 def IPM : InherentRRE<"ipm", 0xB222, GR32, (z_ipm)>; 1614 1615// Read a 32-bit access register into a GR32. As with all GR32 operations, 1616// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 1617// when a 64-bit address is stored in a pair of access registers. 1618def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2), 1619 "ear\t$R1, $R2", 1620 [(set GR32:$R1, (z_extract_access access_reg:$R2))]>; 1621 1622// Find leftmost one, AKA count leading zeros. The instruction actually 1623// returns a pair of GR64s, the first giving the number of leading zeros 1624// and the second giving a copy of the source with the leftmost one bit 1625// cleared. We only use the first result here. 1626let Defs = [CC] in { 1627 def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>; 1628} 1629def : Pat<(ctlz GR64:$src), 1630 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 1631 1632// Population count. Counts bits set per byte. 1633let Predicates = [FeaturePopulationCount], Defs = [CC] in { 1634 def POPCNT : InstRRE<0xB9E1, (outs GR64:$R1), (ins GR64:$R2), 1635 "popcnt\t$R1, $R2", 1636 [(set GR64:$R1, (z_popcnt GR64:$R2))]>; 1637} 1638 1639// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 1640def : Pat<(i64 (anyext GR32:$src)), 1641 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 1642 1643// Extend GR32s and GR64s to GR128s. 1644let usesCustomInserter = 1 in { 1645 def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 1646 def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>; 1647 def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 1648} 1649 1650// Search a block of memory for a character. 1651let mayLoad = 1, Defs = [CC] in 1652 defm SRST : StringRRE<"srst", 0xb25e, z_search_string>; 1653 1654// Other instructions for inline assembly 1655let hasSideEffects = 1, Defs = [CC], isCall = 1 in 1656 def SVC : InstI<0x0A, (outs), (ins imm32zx8:$I1), 1657 "svc\t$I1", 1658 []>; 1659let hasSideEffects = 1, Defs = [CC], mayStore = 1 in 1660 def STCK : InstS<0xB205, (outs), (ins bdaddr12only:$BD2), 1661 "stck\t$BD2", 1662 []>; 1663let hasSideEffects = 1, Defs = [CC], mayStore = 1 in 1664 def STCKF : InstS<0xB27C, (outs), (ins bdaddr12only:$BD2), 1665 "stckf\t$BD2", 1666 []>; 1667let hasSideEffects = 1, Defs = [CC], mayStore = 1 in 1668 def STCKE : InstS<0xB278, (outs), (ins bdaddr12only:$BD2), 1669 "stcke\t$BD2", 1670 []>; 1671let hasSideEffects = 1, Defs = [CC], mayStore = 1 in 1672 def STFLE : InstS<0xB2B0, (outs), (ins bdaddr12only:$BD2), 1673 "stfle\t$BD2", 1674 []>; 1675 1676let hasSideEffects = 1 in { 1677 def EX : InstRX<0x44, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2), 1678 "ex\t$R1, $XBD2", []>; 1679 def EXRL : InstRIL<0xC60, (outs), (ins GR64:$R1, pcrel32:$I2), 1680 "exrl\t$R1, $I2", []>; 1681} 1682 1683 1684//===----------------------------------------------------------------------===// 1685// Peepholes. 1686//===----------------------------------------------------------------------===// 1687 1688// Use AL* for GR64 additions of unsigned 32-bit values. 1689defm : ZXB<add, GR64, ALGFR>; 1690def : Pat<(add GR64:$src1, imm64zx32:$src2), 1691 (ALGFI GR64:$src1, imm64zx32:$src2)>; 1692def : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)), 1693 (ALGF GR64:$src1, bdxaddr20only:$addr)>; 1694 1695// Use SL* for GR64 subtractions of unsigned 32-bit values. 1696defm : ZXB<sub, GR64, SLGFR>; 1697def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1698 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1699def : Pat<(sub GR64:$src1, (azextloadi32 bdxaddr20only:$addr)), 1700 (SLGF GR64:$src1, bdxaddr20only:$addr)>; 1701 1702// Optimize sign-extended 1/0 selects to -1/0 selects. This is important 1703// for vector legalization. 1704def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, imm32zx4:$cc)), 1705 (i32 31)), 1706 (i32 31)), 1707 (Select32 (LHI -1), (LHI 0), imm32zx4:$valid, imm32zx4:$cc)>; 1708def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, 1709 imm32zx4:$cc)))), 1710 (i32 63)), 1711 (i32 63)), 1712 (Select64 (LGHI -1), (LGHI 0), imm32zx4:$valid, imm32zx4:$cc)>; 1713 1714// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 1715// equivalent to (and (xor x, -1), y) 1716def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 1717 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 1718 1719// Shift/rotate instructions only use the last 6 bits of the second operand 1720// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 1721// last 16 bits. 1722// Complexity is added so that we match this before we match NILF on the AND 1723// operation alone. 1724let AddedComplexity = 4 in { 1725 def : Pat<(shl GR32:$val, (and GR32:$shift, uimm32:$imm)), 1726 (SLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1727 1728 def : Pat<(sra GR32:$val, (and GR32:$shift, uimm32:$imm)), 1729 (SRA GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1730 1731 def : Pat<(srl GR32:$val, (and GR32:$shift, uimm32:$imm)), 1732 (SRL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1733 1734 def : Pat<(shl GR64:$val, (and GR32:$shift, uimm32:$imm)), 1735 (SLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1736 1737 def : Pat<(sra GR64:$val, (and GR32:$shift, uimm32:$imm)), 1738 (SRAG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1739 1740 def : Pat<(srl GR64:$val, (and GR32:$shift, uimm32:$imm)), 1741 (SRLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1742 1743 def : Pat<(rotl GR32:$val, (and GR32:$shift, uimm32:$imm)), 1744 (RLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1745 1746 def : Pat<(rotl GR64:$val, (and GR32:$shift, uimm32:$imm)), 1747 (RLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1748} 1749 1750// Peepholes for turning scalar operations into block operations. 1751defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence, 1752 XCSequence, 1>; 1753defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence, 1754 XCSequence, 2>; 1755defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence, 1756 XCSequence, 4>; 1757defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence, 1758 OCSequence, XCSequence, 1>; 1759defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence, 1760 XCSequence, 2>; 1761defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence, 1762 XCSequence, 4>; 1763defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence, 1764 XCSequence, 8>; 1765