1 //===-- XCoreTargetMachine.cpp - Define TargetMachine for XCore -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "XCoreTargetMachine.h"
14 #include "XCoreTargetObjectFile.h"
15 #include "XCoreTargetTransformInfo.h"
16 #include "XCore.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/TargetPassConfig.h"
19 #include "llvm/IR/Module.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/Support/TargetRegistry.h"
22 using namespace llvm;
23
getEffectiveRelocModel(Optional<Reloc::Model> RM)24 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
25 if (!RM.hasValue())
26 return Reloc::Static;
27 return *RM;
28 }
29
30 /// Create an ILP32 architecture model
31 ///
XCoreTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,CodeModel::Model CM,CodeGenOpt::Level OL)32 XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT,
33 StringRef CPU, StringRef FS,
34 const TargetOptions &Options,
35 Optional<Reloc::Model> RM,
36 CodeModel::Model CM,
37 CodeGenOpt::Level OL)
38 : LLVMTargetMachine(
39 T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32",
40 TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM, OL),
41 TLOF(make_unique<XCoreTargetObjectFile>()),
42 Subtarget(TT, CPU, FS, *this) {
43 initAsmInfo();
44 }
45
~XCoreTargetMachine()46 XCoreTargetMachine::~XCoreTargetMachine() {}
47
48 namespace {
49 /// XCore Code Generator Pass Configuration Options.
50 class XCorePassConfig : public TargetPassConfig {
51 public:
XCorePassConfig(XCoreTargetMachine * TM,PassManagerBase & PM)52 XCorePassConfig(XCoreTargetMachine *TM, PassManagerBase &PM)
53 : TargetPassConfig(TM, PM) {}
54
getXCoreTargetMachine() const55 XCoreTargetMachine &getXCoreTargetMachine() const {
56 return getTM<XCoreTargetMachine>();
57 }
58
59 void addIRPasses() override;
60 bool addPreISel() override;
61 bool addInstSelector() override;
62 void addPreEmitPass() override;
63 };
64 } // namespace
65
createPassConfig(PassManagerBase & PM)66 TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) {
67 return new XCorePassConfig(this, PM);
68 }
69
addIRPasses()70 void XCorePassConfig::addIRPasses() {
71 addPass(createAtomicExpandPass(&getXCoreTargetMachine()));
72
73 TargetPassConfig::addIRPasses();
74 }
75
addPreISel()76 bool XCorePassConfig::addPreISel() {
77 addPass(createXCoreLowerThreadLocalPass());
78 return false;
79 }
80
addInstSelector()81 bool XCorePassConfig::addInstSelector() {
82 addPass(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
83 return false;
84 }
85
addPreEmitPass()86 void XCorePassConfig::addPreEmitPass() {
87 addPass(createXCoreFrameToArgsOffsetEliminationPass(), false);
88 }
89
90 // Force static initialization.
LLVMInitializeXCoreTarget()91 extern "C" void LLVMInitializeXCoreTarget() {
92 RegisterTargetMachine<XCoreTargetMachine> X(TheXCoreTarget);
93 }
94
getTargetIRAnalysis()95 TargetIRAnalysis XCoreTargetMachine::getTargetIRAnalysis() {
96 return TargetIRAnalysis([this](const Function &F) {
97 return TargetTransformInfo(XCoreTTIImpl(this, F));
98 });
99 }
100