1; RUN: llc < %s -mtriple=armv8-linux-gnu -mattr=+neon | FileCheck %s
2
3; CHECK-LABEL: t1
4; CHECK: vmax.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
5define <4 x i32> @t1(<4 x i32> %a, <4 x i32> %b) {
6  %t1 = icmp sgt <4 x i32> %a, %b
7  %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
8  ret <4 x i32> %t2
9}
10
11; CHECK-LABEL: t2
12; CHECK: vmin.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
13define <4 x i32> @t2(<4 x i32> %a, <4 x i32> %b) {
14  %t1 = icmp slt <4 x i32> %a, %b
15  %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
16  ret <4 x i32> %t2
17}
18
19; CHECK-LABEL: t3
20; CHECK: vmax.u32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
21define <4 x i32> @t3(<4 x i32> %a, <4 x i32> %b) {
22  %t1 = icmp ugt <4 x i32> %a, %b
23  %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
24  ret <4 x i32> %t2
25}
26
27; CHECK-LABEL: t4
28; CHECK: vmin.u32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
29define <4 x i32> @t4(<4 x i32> %a, <4 x i32> %b) {
30  %t1 = icmp ult <4 x i32> %a, %b
31  %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
32  ret <4 x i32> %t2
33}
34
35; CHECK-LABEL: t5
36; CHECK: vmax.s32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
37define <2 x i32> @t5(<2 x i32> %a, <2 x i32> %b) {
38  %t1 = icmp sgt <2 x i32> %a, %b
39  %t2 = select <2 x i1> %t1, <2 x i32> %a, <2 x i32> %b
40  ret <2 x i32> %t2
41}
42
43; CHECK-LABEL: t6
44; CHECK: vmin.s32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
45define <2 x i32> @t6(<2 x i32> %a, <2 x i32> %b) {
46  %t1 = icmp slt <2 x i32> %a, %b
47  %t2 = select <2 x i1> %t1, <2 x i32> %a, <2 x i32> %b
48  ret <2 x i32> %t2
49}
50
51; CHECK-LABEL: t7
52; CHECK: vmax.u32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
53define <2 x i32> @t7(<2 x i32> %a, <2 x i32> %b) {
54  %t1 = icmp ugt <2 x i32> %a, %b
55  %t2 = select <2 x i1> %t1, <2 x i32> %a, <2 x i32> %b
56  ret <2 x i32> %t2
57}
58
59; CHECK-LABEL: t8
60; CHECK: vmin.u32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
61define <2 x i32> @t8(<2 x i32> %a, <2 x i32> %b) {
62  %t1 = icmp ult <2 x i32> %a, %b
63  %t2 = select <2 x i1> %t1, <2 x i32> %a, <2 x i32> %b
64  ret <2 x i32> %t2
65}
66
67; CHECK-LABEL: t9
68; CHECK: vmax.s16 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
69define <8 x i16> @t9(<8 x i16> %a, <8 x i16> %b) {
70  %t1 = icmp sgt <8 x i16> %a, %b
71  %t2 = select <8 x i1> %t1, <8 x i16> %a, <8 x i16> %b
72  ret <8 x i16> %t2
73}
74
75; CHECK-LABEL: t10
76; CHECK: vmin.s16 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
77define <8 x i16> @t10(<8 x i16> %a, <8 x i16> %b) {
78  %t1 = icmp slt <8 x i16> %a, %b
79  %t2 = select <8 x i1> %t1, <8 x i16> %a, <8 x i16> %b
80  ret <8 x i16> %t2
81}
82
83; CHECK-LABEL: t11
84; CHECK: vmax.u16 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
85define <8 x i16> @t11(<8 x i16> %a, <8 x i16> %b) {
86  %t1 = icmp ugt <8 x i16> %a, %b
87  %t2 = select <8 x i1> %t1, <8 x i16> %a, <8 x i16> %b
88  ret <8 x i16> %t2
89}
90
91; CHECK-LABEL: t12
92; CHECK: vmin.u16 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
93define <8 x i16> @t12(<8 x i16> %a, <8 x i16> %b) {
94  %t1 = icmp ult <8 x i16> %a, %b
95  %t2 = select <8 x i1> %t1, <8 x i16> %a, <8 x i16> %b
96  ret <8 x i16> %t2
97}
98
99; CHECK-LABEL: t13
100; CHECK: vmax.s16
101define <4 x i16> @t13(<4 x i16> %a, <4 x i16> %b) {
102  %t1 = icmp sgt <4 x i16> %a, %b
103  %t2 = select <4 x i1> %t1, <4 x i16> %a, <4 x i16> %b
104  ret <4 x i16> %t2
105}
106
107; CHECK-LABEL: t14
108; CHECK: vmin.s16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
109define <4 x i16> @t14(<4 x i16> %a, <4 x i16> %b) {
110  %t1 = icmp slt <4 x i16> %a, %b
111  %t2 = select <4 x i1> %t1, <4 x i16> %a, <4 x i16> %b
112  ret <4 x i16> %t2
113}
114
115; CHECK-LABEL: t15
116; CHECK: vmax.u16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
117define <4 x i16> @t15(<4 x i16> %a, <4 x i16> %b) {
118  %t1 = icmp ugt <4 x i16> %a, %b
119  %t2 = select <4 x i1> %t1, <4 x i16> %a, <4 x i16> %b
120  ret <4 x i16> %t2
121}
122
123; CHECK-LABEL: t16
124; CHECK: vmin.u16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
125define <4 x i16> @t16(<4 x i16> %a, <4 x i16> %b) {
126  %t1 = icmp ult <4 x i16> %a, %b
127  %t2 = select <4 x i1> %t1, <4 x i16> %a, <4 x i16> %b
128  ret <4 x i16> %t2
129}
130
131; CHECK-LABEL: t17
132; CHECK: vmax.s8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
133define <16 x i8> @t17(<16 x i8> %a, <16 x i8> %b) {
134  %t1 = icmp sgt <16 x i8> %a, %b
135  %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b
136  ret <16 x i8> %t2
137}
138
139; CHECK-LABEL: t18
140; CHECK: vmin.s8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
141define <16 x i8> @t18(<16 x i8> %a, <16 x i8> %b) {
142  %t1 = icmp slt <16 x i8> %a, %b
143  %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b
144  ret <16 x i8> %t2
145}
146
147; CHECK-LABEL: t19
148; CHECK: vmax.u8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
149define <16 x i8> @t19(<16 x i8> %a, <16 x i8> %b) {
150  %t1 = icmp ugt <16 x i8> %a, %b
151  %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b
152  ret <16 x i8> %t2
153}
154
155; CHECK-LABEL: t20
156; CHECK: vmin.u8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
157define <16 x i8> @t20(<16 x i8> %a, <16 x i8> %b) {
158  %t1 = icmp ult <16 x i8> %a, %b
159  %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b
160  ret <16 x i8> %t2
161}
162
163; CHECK-LABEL: t21
164; CHECK: vmax.s8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
165define <8 x i8> @t21(<8 x i8> %a, <8 x i8> %b) {
166  %t1 = icmp sgt <8 x i8> %a, %b
167  %t2 = select <8 x i1> %t1, <8 x i8> %a, <8 x i8> %b
168  ret <8 x i8> %t2
169}
170
171; CHECK-LABEL: t22
172; CHECK: vmin.s8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
173define <8 x i8> @t22(<8 x i8> %a, <8 x i8> %b) {
174  %t1 = icmp slt <8 x i8> %a, %b
175  %t2 = select <8 x i1> %t1, <8 x i8> %a, <8 x i8> %b
176  ret <8 x i8> %t2
177}
178
179; CHECK-LABEL: t23
180; CHECK: vmax.u8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
181define <8 x i8> @t23(<8 x i8> %a, <8 x i8> %b) {
182  %t1 = icmp ugt <8 x i8> %a, %b
183  %t2 = select <8 x i1> %t1, <8 x i8> %a, <8 x i8> %b
184  ret <8 x i8> %t2
185}
186
187; CHECK-LABEL: t24
188; CHECK: vmin.u8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
189define <8 x i8> @t24(<8 x i8> %a, <8 x i8> %b) {
190  %t1 = icmp ult <8 x i8> %a, %b
191  %t2 = select <8 x i1> %t1, <8 x i8> %a, <8 x i8> %b
192  ret <8 x i8> %t2
193}
194