1; RUN: llc -O3 -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
2;
3; Generate hardware loop when loop 'latch' block is different
4; from the loop 'exiting' block.
5
6; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}})
7; CHECK: endloop0
8
9define void @test(i32* nocapture %pFL, i16 signext %nBS, i16* nocapture readonly %pHT) #0 {
10entry:
11  %0 = load i32, i32* %pFL, align 4
12  %1 = tail call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %0, i32 246)
13  %2 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %1, i32 -13)
14  %3 = tail call i32 @llvm.hexagon.A2.sat(i64 %2)
15  store i32 %3, i32* %pFL, align 4
16  %cmp16 = icmp sgt i16 %nBS, 0
17  br i1 %cmp16, label %for.body.lr.ph, label %for.end
18
19for.body.lr.ph:
20  %4 = sext i16 %nBS to i32
21  br label %for.body
22
23for.body:
24  %5 = phi i32 [ %3, %for.body.lr.ph ], [ %.pre, %for.body.for.body_crit_edge ]
25  %arrayidx3.phi = phi i32* [ %pFL, %for.body.lr.ph ], [ %arrayidx3.inc, %for.body.for.body_crit_edge ]
26  %arrayidx5.phi = phi i16* [ %pHT, %for.body.lr.ph ], [ %arrayidx5.inc, %for.body.for.body_crit_edge ]
27  %i.017.pmt = phi i32 [ 1, %for.body.lr.ph ], [ %phitmp, %for.body.for.body_crit_edge ]
28  %6 = load i16, i16* %arrayidx5.phi, align 2
29  %conv6 = sext i16 %6 to i32
30  %7 = tail call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %5, i32 %conv6)
31  %8 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %7, i32 -13)
32  %9 = tail call i32 @llvm.hexagon.A2.sat(i64 %8)
33  store i32 %9, i32* %arrayidx3.phi, align 4
34  %exitcond = icmp eq i32 %i.017.pmt, %4
35  %arrayidx3.inc = getelementptr i32, i32* %arrayidx3.phi, i32 1
36  br i1 %exitcond, label %for.end.loopexit, label %for.body.for.body_crit_edge
37
38for.body.for.body_crit_edge:
39  %arrayidx5.inc = getelementptr i16, i16* %arrayidx5.phi, i32 1
40  %.pre = load i32, i32* %arrayidx3.inc, align 4
41  %phitmp = add i32 %i.017.pmt, 1
42  br label %for.body
43
44for.end.loopexit:
45  br label %for.end
46
47for.end:
48  ret void
49}
50
51declare i32 @llvm.hexagon.A2.sat(i64) #1
52
53declare i64 @llvm.hexagon.S2.asl.r.p(i64, i32) #1
54
55declare i64 @llvm.hexagon.M2.dpmpyss.s0(i32, i32) #1
56
57attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "ssp-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
58attributes #1 = { nounwind readnone }
59