1; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ 2; RUN: -check-prefixes=ALL,GP32,NOT-R6,NOT-R2-R6 3; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ 4; RUN: -check-prefixes=ALL,GP32,NOT-R6,NOT-R2-R6 5; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ 6; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 7; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ 8; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 9; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ 10; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 11; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ 12; RUN: -check-prefixes=ALL,GP32,R6,R2-R6 13 14; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ 15; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 16; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ 17; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 18; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ 19; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 20; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ 21; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 22; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ 23; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 24; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ 25; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 26; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ 27; RUN: -check-prefixes=ALL,64R6,R6,R2-R6 28 29; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 30; RUN: -check-prefixes=ALL,MMR3,MM32 31; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 32; RUN: -check-prefixes=ALL,MMR6,MM32 33; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 34; RUN: -check-prefixes=ALL,MMR6,MM64 35 36define signext i1 @urem_i1(i1 signext %a, i1 signext %b) { 37entry: 38; ALL-LABEL: urem_i1: 39 40 ; NOT-R6: andi $[[T0:[0-9]+]], $5, 1 41 ; NOT-R6: andi $[[T1:[0-9]+]], $4, 1 42 ; NOT-R6: divu $zero, $[[T1]], $[[T0]] 43 ; NOT-R6: teq $[[T0]], $zero, 7 44 ; NOT-R6: mfhi $[[T2:[0-9]+]] 45 ; NOT-R6: sll $[[T3:[0-9]+]], $[[T2]], 31 46 ; NOT-R6: sra $2, $[[T3]], 31 47 48 ; R6: andi $[[T0:[0-9]+]], $5, 1 49 ; R6: andi $[[T1:[0-9]+]], $4, 1 50 ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] 51 ; R6: teq $[[T0]], $zero, 7 52 ; R6: sll $[[T3:[0-9]+]], $[[T2]], 31 53 ; R6: sra $2, $[[T3]], 31 54 55 ; MMR3: andi16 $[[T0:[0-9]+]], $5, 1 56 ; MMR3: andi16 $[[T1:[0-9]+]], $4, 1 57 ; MMR3: divu $zero, $[[T1]], $[[T0]] 58 ; MMR3: teq $[[T0]], $zero, 7 59 ; MMR3: mfhi $[[T2:[0-9]+]] 60 ; MMR3: sll $[[T3:[0-9]+]], $[[T2]], 31 61 ; MMR3: sra $2, $[[T3]], 31 62 63 ; MMR6: andi16 $[[T0:[0-9]+]], $5, 1 64 ; MMR6: andi16 $[[T1:[0-9]+]], $4, 1 65 ; MMR6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] 66 ; MMR6: teq $[[T0]], $zero, 7 67 ; MMR6: sll $[[T3:[0-9]+]], $[[T2]], 31 68 ; MMR6: sra $2, $[[T3]], 31 69 70 %r = urem i1 %a, %b 71 ret i1 %r 72} 73 74define signext i8 @urem_i8(i8 signext %a, i8 signext %b) { 75entry: 76; ALL-LABEL: urem_i8: 77 78 ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255 79 ; NOT-R2-R6: andi $[[T1:[0-9]+]], $4, 255 80 ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]] 81 ; NOT-R2-R6: teq $[[T0]], $zero, 7 82 ; NOT-R2-R6: mfhi $[[T2:[0-9]+]] 83 ; NOT-R2-R6: sll $[[T3:[0-9]+]], $[[T2]], 24 84 ; NOT-R2-R6: sra $2, $[[T3]], 24 85 86 ; R2-R5: andi $[[T0:[0-9]+]], $5, 255 87 ; R2-R5: andi $[[T1:[0-9]+]], $4, 255 88 ; R2-R5: divu $zero, $[[T1]], $[[T0]] 89 ; R2-R5: teq $[[T0]], $zero, 7 90 ; R2-R5: mfhi $[[T2:[0-9]+]] 91 ; R2-R5: seb $2, $[[T2]] 92 93 ; R6: andi $[[T0:[0-9]+]], $5, 255 94 ; R6: andi $[[T1:[0-9]+]], $4, 255 95 ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] 96 ; R6: teq $[[T0]], $zero, 7 97 ; R6: seb $2, $[[T2]] 98 99 ; MMR3: andi16 $[[T0:[0-9]+]], $5, 255 100 ; MMR3: andi16 $[[T1:[0-9]+]], $4, 255 101 ; MMR3: divu $zero, $[[T1]], $[[T0]] 102 ; MMR3: teq $[[T0]], $zero, 7 103 ; MMR3: mfhi $[[T2:[0-9]+]] 104 ; MMR3: seb $2, $[[T2]] 105 106 ; MMR6: andi16 $[[T0:[0-9]+]], $5, 255 107 ; MMR6: andi16 $[[T1:[0-9]+]], $4, 255 108 ; MMR6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] 109 ; MMR6: teq $[[T0]], $zero, 7 110 ; MMR6: seb $2, $[[T2]] 111 112 %r = urem i8 %a, %b 113 ret i8 %r 114} 115 116define signext i16 @urem_i16(i16 signext %a, i16 signext %b) { 117entry: 118; ALL-LABEL: urem_i16: 119 120 ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 65535 121 ; NOT-R2-R6: andi $[[T1:[0-9]+]], $4, 65535 122 ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]] 123 ; NOT-R2-R6: teq $[[T0]], $zero, 7 124 ; NOT-R2-R6: mfhi $[[T2:[0-9]+]] 125 ; NOT-R2-R6: sll $[[T3:[0-9]+]], $[[T2]], 16 126 ; NOT-R2-R6: sra $2, $[[T3]], 16 127 128 ; R2-R5: andi $[[T0:[0-9]+]], $5, 65535 129 ; R2-R5: andi $[[T1:[0-9]+]], $4, 65535 130 ; R2-R5: divu $zero, $[[T1]], $[[T0]] 131 ; R2-R5: teq $[[T0]], $zero, 7 132 ; R2-R5: mfhi $[[T3:[0-9]+]] 133 ; R2-R5: seh $2, $[[T2]] 134 135 ; R6: andi $[[T0:[0-9]+]], $5, 65535 136 ; R6: andi $[[T1:[0-9]+]], $4, 65535 137 ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] 138 ; R6: teq $[[T0]], $zero, 7 139 ; R6: seh $2, $[[T2]] 140 141 ; MMR3: andi16 $[[T0:[0-9]+]], $5, 65535 142 ; MMR3: andi16 $[[T1:[0-9]+]], $4, 65535 143 ; MMR3: divu $zero, $[[T1]], $[[T0]] 144 ; MMR3: teq $[[T0]], $zero, 7 145 ; MMR3: mfhi $[[T2:[0-9]+]] 146 ; MMR3: seh $2, $[[T2]] 147 148 ; MMR6: andi16 $[[T0:[0-9]+]], $5, 65535 149 ; MMR6: andi16 $[[T1:[0-9]+]], $4, 65535 150 ; MMR6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] 151 ; MMR6: teq $[[T0]], $zero, 7 152 ; MMR6: seh $2, $[[T2]] 153 154 %r = urem i16 %a, %b 155 ret i16 %r 156} 157 158define signext i32 @urem_i32(i32 signext %a, i32 signext %b) { 159entry: 160; ALL-LABEL: urem_i32: 161 162 ; NOT-R6: divu $zero, $4, $5 163 ; NOT-R6: teq $5, $zero, 7 164 ; NOT-R6: mfhi $2 165 166 ; R6: modu $2, $4, $5 167 ; R6: teq $5, $zero, 7 168 169 ; MMR3: divu $zero, $4, $5 170 ; MMR3: teq $5, $zero, 7 171 ; MMR3: mfhi $2 172 173 ; MMR6: modu $2, $4, $5 174 ; MMR6: teq $5, $zero, 7 175 176 %r = urem i32 %a, %b 177 ret i32 %r 178} 179 180define signext i64 @urem_i64(i64 signext %a, i64 signext %b) { 181entry: 182; ALL-LABEL: urem_i64: 183 184 ; GP32: lw $25, %call16(__umoddi3)($gp) 185 186 ; GP64-NOT-R6: ddivu $zero, $4, $5 187 ; GP64-NOT-R6: teq $5, $zero, 7 188 ; GP64-NOT-R6: mfhi $2 189 190 ; 64R6: dmodu $2, $4, $5 191 ; 64R6: teq $5, $zero, 7 192 193 ; MM32: lw $25, %call16(__umoddi3)($2) 194 195 ; MM64: dmodu $2, $4, $5 196 ; MM64: teq $5, $zero, 7 197 198 %r = urem i64 %a, %b 199 ret i64 %r 200} 201 202define signext i128 @urem_i128(i128 signext %a, i128 signext %b) { 203entry: 204 ; ALL-LABEL: urem_i128: 205 206 ; GP32: lw $25, %call16(__umodti3)($gp) 207 208 ; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp) 209 ; 64R6: ld $25, %call16(__umodti3)($gp) 210 211 ; MM32: lw $25, %call16(__umodti3)($2) 212 213 ; MM64: ld $25, %call16(__umodti3)($2) 214 215 %r = urem i128 %a, %b 216 ret i128 %r 217} 218