1//====- X86Instr3DNow.td - The 3DNow! Instruction Set ------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the 3DNow! instruction set, which extends MMX to support
11// floating point and also adds a few more random instructions for good measure.
12//
13//===----------------------------------------------------------------------===//
14
15class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pat>
16      : I<o, F, outs, ins, asm, pat>, TB, Requires<[Has3DNow]> {
17}
18
19class I3DNow_binop<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat>
20      : I3DNow<o, F, (outs VR64:$dst), ins,
21          !strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), pat>,
22        Has3DNow0F0FOpcode {
23  // FIXME: The disassembler doesn't support Has3DNow0F0FOpcode yet.
24  let isAsmParserOnly = 1;
25  let Constraints = "$src1 = $dst";
26}
27
28class I3DNow_conv<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat>
29      : I3DNow<o, F, (outs VR64:$dst), ins,
30          !strconcat(Mnemonic, "\t{$src, $dst|$dst, $src}"), pat>,
31        Has3DNow0F0FOpcode {
32  // FIXME: The disassembler doesn't support Has3DNow0F0FOpcode yet.
33  let isAsmParserOnly = 1;
34}
35
36multiclass I3DNow_binop_rm<bits<8> opc, string Mn> {
37  def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, []>;
38  def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn, []>;
39}
40
41multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn, string Ver = ""> {
42  def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
43    [(set VR64:$dst, (!cast<Intrinsic>(
44      !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, VR64:$src2))]>;
45  def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn,
46    [(set VR64:$dst, (!cast<Intrinsic>(
47      !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1,
48        (bitconvert (load_mmx addr:$src2))))]>;
49}
50
51multiclass I3DNow_conv_rm<bits<8> opc, string Mn> {
52  def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src1), Mn, []>;
53  def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src1), Mn, []>;
54}
55
56multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn, string Ver = ""> {
57  def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn,
58    [(set VR64:$dst, (!cast<Intrinsic>(
59      !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src))]>;
60  def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src), Mn,
61    [(set VR64:$dst, (!cast<Intrinsic>(
62      !strconcat("int_x86_3dnow", Ver, "_", Mn))
63        (bitconvert (load_mmx addr:$src))))]>;
64}
65
66defm PAVGUSB  : I3DNow_binop_rm_int<0xBF, "pavgusb">;
67defm PF2ID    : I3DNow_conv_rm_int<0x1D, "pf2id">;
68defm PFACC    : I3DNow_binop_rm_int<0xAE, "pfacc">;
69defm PFADD    : I3DNow_binop_rm_int<0x9E, "pfadd">;
70defm PFCMPEQ  : I3DNow_binop_rm_int<0xB0, "pfcmpeq">;
71defm PFCMPGE  : I3DNow_binop_rm_int<0x90, "pfcmpge">;
72defm PFCMPGT  : I3DNow_binop_rm_int<0xA0, "pfcmpgt">;
73defm PFMAX    : I3DNow_binop_rm_int<0xA4, "pfmax">;
74defm PFMIN    : I3DNow_binop_rm_int<0x94, "pfmin">;
75defm PFMUL    : I3DNow_binop_rm_int<0xB4, "pfmul">;
76defm PFRCP    : I3DNow_conv_rm_int<0x96, "pfrcp">;
77defm PFRCPIT1 : I3DNow_binop_rm_int<0xA6, "pfrcpit1">;
78defm PFRCPIT2 : I3DNow_binop_rm_int<0xB6, "pfrcpit2">;
79defm PFRSQIT1 : I3DNow_binop_rm_int<0xA7, "pfrsqit1">;
80defm PFRSQRT  : I3DNow_conv_rm_int<0x97, "pfrsqrt">;
81defm PFSUB    : I3DNow_binop_rm_int<0x9A, "pfsub">;
82defm PFSUBR   : I3DNow_binop_rm_int<0xAA, "pfsubr">;
83defm PI2FD    : I3DNow_conv_rm_int<0x0D, "pi2fd">;
84defm PMULHRW  : I3DNow_binop_rm_int<0xB7, "pmulhrw">;
85
86
87def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;
88
89def PREFETCH  : I3DNow<0x0D, MRM0m, (outs), (ins i32mem:$addr),
90                       "prefetch $addr", []>;
91
92// FIXME: Diassembler gets a bogus decode conflict.
93let isAsmParserOnly = 1 in
94def PREFETCHW : I3DNow<0x0D, MRM1m, (outs), (ins i16mem:$addr),
95                       "prefetchw $addr", []>;
96
97// "3DNowA" instructions
98defm PF2IW    : I3DNow_conv_rm_int<0x1C, "pf2iw", "a">;
99defm PI2FW    : I3DNow_conv_rm_int<0x0C, "pi2fw", "a">;
100defm PFNACC   : I3DNow_binop_rm_int<0x8A, "pfnacc", "a">;
101defm PFPNACC  : I3DNow_binop_rm_int<0x8E, "pfpnacc", "a">;
102defm PSWAPD   : I3DNow_conv_rm_int<0xBB, "pswapd", "a">;
103