1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/LLVMContext.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/LiveVariables.h"
28 #include "llvm/CodeGen/PseudoSourceValue.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include <limits>
37
38 #define GET_INSTRINFO_CTOR
39 #include "X86GenInstrInfo.inc"
40
41 using namespace llvm;
42
43 static cl::opt<bool>
44 NoFusing("disable-spill-fusing",
45 cl::desc("Disable fusing of spill code into instructions"));
46 static cl::opt<bool>
47 PrintFailedFusing("print-failed-fuse-candidates",
48 cl::desc("Print instructions that the allocator wants to"
49 " fuse, but the X86 backend currently can't"),
50 cl::Hidden);
51 static cl::opt<bool>
52 ReMatPICStubLoad("remat-pic-stub-load",
53 cl::desc("Re-materialize load from stub in PIC mode"),
54 cl::init(false), cl::Hidden);
55
56 enum {
57 // Select which memory operand is being unfolded.
58 // (stored in bits 0 - 7)
59 TB_INDEX_0 = 0,
60 TB_INDEX_1 = 1,
61 TB_INDEX_2 = 2,
62 TB_INDEX_MASK = 0xff,
63
64 // Minimum alignment required for load/store.
65 // Used for RegOp->MemOp conversion.
66 // (stored in bits 8 - 15)
67 TB_ALIGN_SHIFT = 8,
68 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
69 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
70 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
71 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT,
72
73 // Do not insert the reverse map (MemOp -> RegOp) into the table.
74 // This may be needed because there is a many -> one mapping.
75 TB_NO_REVERSE = 1 << 16,
76
77 // Do not insert the forward map (RegOp -> MemOp) into the table.
78 // This is needed for Native Client, which prohibits branch
79 // instructions from using a memory operand.
80 TB_NO_FORWARD = 1 << 17,
81
82 TB_FOLDED_LOAD = 1 << 18,
83 TB_FOLDED_STORE = 1 << 19
84 };
85
X86InstrInfo(X86TargetMachine & tm)86 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
87 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
88 ? X86::ADJCALLSTACKDOWN64
89 : X86::ADJCALLSTACKDOWN32),
90 (tm.getSubtarget<X86Subtarget>().is64Bit()
91 ? X86::ADJCALLSTACKUP64
92 : X86::ADJCALLSTACKUP32)),
93 TM(tm), RI(tm, *this) {
94
95 static const unsigned OpTbl2Addr[][3] = {
96 { X86::ADC32ri, X86::ADC32mi, 0 },
97 { X86::ADC32ri8, X86::ADC32mi8, 0 },
98 { X86::ADC32rr, X86::ADC32mr, 0 },
99 { X86::ADC64ri32, X86::ADC64mi32, 0 },
100 { X86::ADC64ri8, X86::ADC64mi8, 0 },
101 { X86::ADC64rr, X86::ADC64mr, 0 },
102 { X86::ADD16ri, X86::ADD16mi, 0 },
103 { X86::ADD16ri8, X86::ADD16mi8, 0 },
104 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
105 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
106 { X86::ADD16rr, X86::ADD16mr, 0 },
107 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
108 { X86::ADD32ri, X86::ADD32mi, 0 },
109 { X86::ADD32ri8, X86::ADD32mi8, 0 },
110 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
111 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
112 { X86::ADD32rr, X86::ADD32mr, 0 },
113 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
114 { X86::ADD64ri32, X86::ADD64mi32, 0 },
115 { X86::ADD64ri8, X86::ADD64mi8, 0 },
116 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
117 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
118 { X86::ADD64rr, X86::ADD64mr, 0 },
119 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
120 { X86::ADD8ri, X86::ADD8mi, 0 },
121 { X86::ADD8rr, X86::ADD8mr, 0 },
122 { X86::AND16ri, X86::AND16mi, 0 },
123 { X86::AND16ri8, X86::AND16mi8, 0 },
124 { X86::AND16rr, X86::AND16mr, 0 },
125 { X86::AND32ri, X86::AND32mi, 0 },
126 { X86::AND32ri8, X86::AND32mi8, 0 },
127 { X86::AND32rr, X86::AND32mr, 0 },
128 { X86::AND64ri32, X86::AND64mi32, 0 },
129 { X86::AND64ri8, X86::AND64mi8, 0 },
130 { X86::AND64rr, X86::AND64mr, 0 },
131 { X86::AND8ri, X86::AND8mi, 0 },
132 { X86::AND8rr, X86::AND8mr, 0 },
133 { X86::DEC16r, X86::DEC16m, 0 },
134 { X86::DEC32r, X86::DEC32m, 0 },
135 { X86::DEC64_16r, X86::DEC64_16m, 0 },
136 { X86::DEC64_32r, X86::DEC64_32m, 0 },
137 { X86::DEC64r, X86::DEC64m, 0 },
138 { X86::DEC8r, X86::DEC8m, 0 },
139 { X86::INC16r, X86::INC16m, 0 },
140 { X86::INC32r, X86::INC32m, 0 },
141 { X86::INC64_16r, X86::INC64_16m, 0 },
142 { X86::INC64_32r, X86::INC64_32m, 0 },
143 { X86::INC64r, X86::INC64m, 0 },
144 { X86::INC8r, X86::INC8m, 0 },
145 { X86::NEG16r, X86::NEG16m, 0 },
146 { X86::NEG32r, X86::NEG32m, 0 },
147 { X86::NEG64r, X86::NEG64m, 0 },
148 { X86::NEG8r, X86::NEG8m, 0 },
149 { X86::NOT16r, X86::NOT16m, 0 },
150 { X86::NOT32r, X86::NOT32m, 0 },
151 { X86::NOT64r, X86::NOT64m, 0 },
152 { X86::NOT8r, X86::NOT8m, 0 },
153 { X86::OR16ri, X86::OR16mi, 0 },
154 { X86::OR16ri8, X86::OR16mi8, 0 },
155 { X86::OR16rr, X86::OR16mr, 0 },
156 { X86::OR32ri, X86::OR32mi, 0 },
157 { X86::OR32ri8, X86::OR32mi8, 0 },
158 { X86::OR32rr, X86::OR32mr, 0 },
159 { X86::OR64ri32, X86::OR64mi32, 0 },
160 { X86::OR64ri8, X86::OR64mi8, 0 },
161 { X86::OR64rr, X86::OR64mr, 0 },
162 { X86::OR8ri, X86::OR8mi, 0 },
163 { X86::OR8rr, X86::OR8mr, 0 },
164 { X86::ROL16r1, X86::ROL16m1, 0 },
165 { X86::ROL16rCL, X86::ROL16mCL, 0 },
166 { X86::ROL16ri, X86::ROL16mi, 0 },
167 { X86::ROL32r1, X86::ROL32m1, 0 },
168 { X86::ROL32rCL, X86::ROL32mCL, 0 },
169 { X86::ROL32ri, X86::ROL32mi, 0 },
170 { X86::ROL64r1, X86::ROL64m1, 0 },
171 { X86::ROL64rCL, X86::ROL64mCL, 0 },
172 { X86::ROL64ri, X86::ROL64mi, 0 },
173 { X86::ROL8r1, X86::ROL8m1, 0 },
174 { X86::ROL8rCL, X86::ROL8mCL, 0 },
175 { X86::ROL8ri, X86::ROL8mi, 0 },
176 { X86::ROR16r1, X86::ROR16m1, 0 },
177 { X86::ROR16rCL, X86::ROR16mCL, 0 },
178 { X86::ROR16ri, X86::ROR16mi, 0 },
179 { X86::ROR32r1, X86::ROR32m1, 0 },
180 { X86::ROR32rCL, X86::ROR32mCL, 0 },
181 { X86::ROR32ri, X86::ROR32mi, 0 },
182 { X86::ROR64r1, X86::ROR64m1, 0 },
183 { X86::ROR64rCL, X86::ROR64mCL, 0 },
184 { X86::ROR64ri, X86::ROR64mi, 0 },
185 { X86::ROR8r1, X86::ROR8m1, 0 },
186 { X86::ROR8rCL, X86::ROR8mCL, 0 },
187 { X86::ROR8ri, X86::ROR8mi, 0 },
188 { X86::SAR16r1, X86::SAR16m1, 0 },
189 { X86::SAR16rCL, X86::SAR16mCL, 0 },
190 { X86::SAR16ri, X86::SAR16mi, 0 },
191 { X86::SAR32r1, X86::SAR32m1, 0 },
192 { X86::SAR32rCL, X86::SAR32mCL, 0 },
193 { X86::SAR32ri, X86::SAR32mi, 0 },
194 { X86::SAR64r1, X86::SAR64m1, 0 },
195 { X86::SAR64rCL, X86::SAR64mCL, 0 },
196 { X86::SAR64ri, X86::SAR64mi, 0 },
197 { X86::SAR8r1, X86::SAR8m1, 0 },
198 { X86::SAR8rCL, X86::SAR8mCL, 0 },
199 { X86::SAR8ri, X86::SAR8mi, 0 },
200 { X86::SBB32ri, X86::SBB32mi, 0 },
201 { X86::SBB32ri8, X86::SBB32mi8, 0 },
202 { X86::SBB32rr, X86::SBB32mr, 0 },
203 { X86::SBB64ri32, X86::SBB64mi32, 0 },
204 { X86::SBB64ri8, X86::SBB64mi8, 0 },
205 { X86::SBB64rr, X86::SBB64mr, 0 },
206 { X86::SHL16rCL, X86::SHL16mCL, 0 },
207 { X86::SHL16ri, X86::SHL16mi, 0 },
208 { X86::SHL32rCL, X86::SHL32mCL, 0 },
209 { X86::SHL32ri, X86::SHL32mi, 0 },
210 { X86::SHL64rCL, X86::SHL64mCL, 0 },
211 { X86::SHL64ri, X86::SHL64mi, 0 },
212 { X86::SHL8rCL, X86::SHL8mCL, 0 },
213 { X86::SHL8ri, X86::SHL8mi, 0 },
214 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
215 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
216 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
217 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
218 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
219 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
220 { X86::SHR16r1, X86::SHR16m1, 0 },
221 { X86::SHR16rCL, X86::SHR16mCL, 0 },
222 { X86::SHR16ri, X86::SHR16mi, 0 },
223 { X86::SHR32r1, X86::SHR32m1, 0 },
224 { X86::SHR32rCL, X86::SHR32mCL, 0 },
225 { X86::SHR32ri, X86::SHR32mi, 0 },
226 { X86::SHR64r1, X86::SHR64m1, 0 },
227 { X86::SHR64rCL, X86::SHR64mCL, 0 },
228 { X86::SHR64ri, X86::SHR64mi, 0 },
229 { X86::SHR8r1, X86::SHR8m1, 0 },
230 { X86::SHR8rCL, X86::SHR8mCL, 0 },
231 { X86::SHR8ri, X86::SHR8mi, 0 },
232 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
233 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
234 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
235 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
236 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
237 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
238 { X86::SUB16ri, X86::SUB16mi, 0 },
239 { X86::SUB16ri8, X86::SUB16mi8, 0 },
240 { X86::SUB16rr, X86::SUB16mr, 0 },
241 { X86::SUB32ri, X86::SUB32mi, 0 },
242 { X86::SUB32ri8, X86::SUB32mi8, 0 },
243 { X86::SUB32rr, X86::SUB32mr, 0 },
244 { X86::SUB64ri32, X86::SUB64mi32, 0 },
245 { X86::SUB64ri8, X86::SUB64mi8, 0 },
246 { X86::SUB64rr, X86::SUB64mr, 0 },
247 { X86::SUB8ri, X86::SUB8mi, 0 },
248 { X86::SUB8rr, X86::SUB8mr, 0 },
249 { X86::XOR16ri, X86::XOR16mi, 0 },
250 { X86::XOR16ri8, X86::XOR16mi8, 0 },
251 { X86::XOR16rr, X86::XOR16mr, 0 },
252 { X86::XOR32ri, X86::XOR32mi, 0 },
253 { X86::XOR32ri8, X86::XOR32mi8, 0 },
254 { X86::XOR32rr, X86::XOR32mr, 0 },
255 { X86::XOR64ri32, X86::XOR64mi32, 0 },
256 { X86::XOR64ri8, X86::XOR64mi8, 0 },
257 { X86::XOR64rr, X86::XOR64mr, 0 },
258 { X86::XOR8ri, X86::XOR8mi, 0 },
259 { X86::XOR8rr, X86::XOR8mr, 0 }
260 };
261
262 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
263 unsigned RegOp = OpTbl2Addr[i][0];
264 unsigned MemOp = OpTbl2Addr[i][1];
265 unsigned Flags = OpTbl2Addr[i][2];
266 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
267 RegOp, MemOp,
268 // Index 0, folded load and store, no alignment requirement.
269 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
270 }
271
272 static const unsigned OpTbl0[][3] = {
273 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
274 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
275 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
276 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
277 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
278 { X86::WINCALL64r, X86::WINCALL64m, TB_FOLDED_LOAD },
279 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
280 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
281 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
282 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
283 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
284 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
285 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
286 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
287 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
288 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
289 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
290 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
291 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
292 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
293 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
294 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
295 { X86::FsMOVAPDrr, X86::MOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
296 { X86::FsMOVAPSrr, X86::MOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
297 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
298 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
299 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
300 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
301 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
302 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
303 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
304 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
305 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
306 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
307 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
308 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
309 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
310 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
311 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
312 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
313 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
314 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
315 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
316 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
317 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
318 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
319 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
320 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
321 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
322 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
323 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
324 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
325 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
326 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
327 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
328 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
329 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
330 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
331 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
332 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
333 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
334 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
335 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
336 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
337 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
338 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
339 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
340 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
341 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
342 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
343 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
344 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
345 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
346 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
347 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
348 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
349 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
350 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
351 // AVX 128-bit versions of foldable instructions
352 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
353 { X86::FsVMOVAPDrr, X86::VMOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
354 { X86::FsVMOVAPSrr, X86::VMOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
355 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
356 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
357 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
358 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
359 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
360 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
361 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
362 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
363 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
364 // AVX 256-bit foldable instructions
365 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
366 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
367 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
368 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
369 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE }
370 };
371
372 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
373 unsigned RegOp = OpTbl0[i][0];
374 unsigned MemOp = OpTbl0[i][1];
375 unsigned Flags = OpTbl0[i][2];
376 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
377 RegOp, MemOp, TB_INDEX_0 | Flags);
378 }
379
380 static const unsigned OpTbl1[][3] = {
381 { X86::CMP16rr, X86::CMP16rm, 0 },
382 { X86::CMP32rr, X86::CMP32rm, 0 },
383 { X86::CMP64rr, X86::CMP64rm, 0 },
384 { X86::CMP8rr, X86::CMP8rm, 0 },
385 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
386 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
387 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
388 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
389 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
390 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
391 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
392 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
393 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
394 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
395 { X86::FsMOVAPDrr, X86::MOVSDrm, TB_NO_REVERSE },
396 { X86::FsMOVAPSrr, X86::MOVSSrm, TB_NO_REVERSE },
397 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
398 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
399 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
400 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
401 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
402 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
403 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
404 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
405 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, TB_ALIGN_16 },
406 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, TB_ALIGN_16 },
407 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, TB_ALIGN_16 },
408 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, TB_ALIGN_16 },
409 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, TB_ALIGN_16 },
410 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
411 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
412 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
413 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
414 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
415 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
416 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
417 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
418 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
419 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
420 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
421 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
422 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
423 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
424 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
425 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
426 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
427 { X86::MOV16rr, X86::MOV16rm, 0 },
428 { X86::MOV32rr, X86::MOV32rm, 0 },
429 { X86::MOV64rr, X86::MOV64rm, 0 },
430 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
431 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
432 { X86::MOV8rr, X86::MOV8rm, 0 },
433 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
434 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
435 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
436 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
437 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
438 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
439 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
440 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
441 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
442 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
443 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
444 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
445 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
446 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
447 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
448 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
449 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
450 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
451 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
452 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
453 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
454 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
455 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
456 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
457 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
458 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
459 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
460 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
461 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
462 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
463 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
464 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
465 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
466 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
467 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
468 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
469 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, TB_ALIGN_16 },
470 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
471 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, TB_ALIGN_16 },
472 { X86::SQRTSDr, X86::SQRTSDm, 0 },
473 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
474 { X86::SQRTSSr, X86::SQRTSSm, 0 },
475 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
476 { X86::TEST16rr, X86::TEST16rm, 0 },
477 { X86::TEST32rr, X86::TEST32rm, 0 },
478 { X86::TEST64rr, X86::TEST64rm, 0 },
479 { X86::TEST8rr, X86::TEST8rm, 0 },
480 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
481 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
482 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
483 // AVX 128-bit versions of foldable instructions
484 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
485 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
486 { X86::Int_VCVTDQ2PDrr, X86::Int_VCVTDQ2PDrm, TB_ALIGN_16 },
487 { X86::Int_VCVTDQ2PSrr, X86::Int_VCVTDQ2PSrm, TB_ALIGN_16 },
488 { X86::Int_VCVTPD2DQrr, X86::Int_VCVTPD2DQrm, TB_ALIGN_16 },
489 { X86::Int_VCVTPD2PSrr, X86::Int_VCVTPD2PSrm, TB_ALIGN_16 },
490 { X86::Int_VCVTPS2DQrr, X86::Int_VCVTPS2DQrm, TB_ALIGN_16 },
491 { X86::Int_VCVTPS2PDrr, X86::Int_VCVTPS2PDrm, 0 },
492 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
493 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
494 { X86::FsVMOVAPDrr, X86::VMOVSDrm, TB_NO_REVERSE },
495 { X86::FsVMOVAPSrr, X86::VMOVSSrm, TB_NO_REVERSE },
496 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
497 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
498 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
499 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
500 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
501 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
502 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
503 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
504 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 },
505 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 },
506 { X86::VMOVUPDrr, X86::VMOVUPDrm, TB_ALIGN_16 },
507 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
508 { X86::VMOVZDI2PDIrr, X86::VMOVZDI2PDIrm, 0 },
509 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
510 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
511 { X86::VPSHUFDri, X86::VPSHUFDmi, TB_ALIGN_16 },
512 { X86::VPSHUFHWri, X86::VPSHUFHWmi, TB_ALIGN_16 },
513 { X86::VPSHUFLWri, X86::VPSHUFLWmi, TB_ALIGN_16 },
514 { X86::VRCPPSr, X86::VRCPPSm, TB_ALIGN_16 },
515 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, TB_ALIGN_16 },
516 { X86::VRSQRTPSr, X86::VRSQRTPSm, TB_ALIGN_16 },
517 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, TB_ALIGN_16 },
518 { X86::VSQRTPDr, X86::VSQRTPDm, TB_ALIGN_16 },
519 { X86::VSQRTPDr_Int, X86::VSQRTPDm_Int, TB_ALIGN_16 },
520 { X86::VSQRTPSr, X86::VSQRTPSm, TB_ALIGN_16 },
521 { X86::VSQRTPSr_Int, X86::VSQRTPSm_Int, TB_ALIGN_16 },
522 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
523 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
524 // AVX 256-bit foldable instructions
525 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
526 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
527 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_16 },
528 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
529 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 }
530 };
531
532 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
533 unsigned RegOp = OpTbl1[i][0];
534 unsigned MemOp = OpTbl1[i][1];
535 unsigned Flags = OpTbl1[i][2];
536 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
537 RegOp, MemOp,
538 // Index 1, folded load
539 Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
540 }
541
542 static const unsigned OpTbl2[][3] = {
543 { X86::ADC32rr, X86::ADC32rm, 0 },
544 { X86::ADC64rr, X86::ADC64rm, 0 },
545 { X86::ADD16rr, X86::ADD16rm, 0 },
546 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
547 { X86::ADD32rr, X86::ADD32rm, 0 },
548 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
549 { X86::ADD64rr, X86::ADD64rm, 0 },
550 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
551 { X86::ADD8rr, X86::ADD8rm, 0 },
552 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
553 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
554 { X86::ADDSDrr, X86::ADDSDrm, 0 },
555 { X86::ADDSSrr, X86::ADDSSrm, 0 },
556 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
557 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
558 { X86::AND16rr, X86::AND16rm, 0 },
559 { X86::AND32rr, X86::AND32rm, 0 },
560 { X86::AND64rr, X86::AND64rm, 0 },
561 { X86::AND8rr, X86::AND8rm, 0 },
562 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
563 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
564 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
565 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
566 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
567 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
568 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
569 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
570 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
571 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
572 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
573 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
574 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
575 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
576 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
577 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
578 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
579 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
580 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
581 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
582 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
583 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
584 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
585 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
586 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
587 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
588 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
589 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
590 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
591 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
592 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
593 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
594 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
595 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
596 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
597 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
598 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
599 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
600 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
601 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
602 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
603 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
604 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
605 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
606 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
607 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
608 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
609 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
610 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
611 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
612 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
613 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
614 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
615 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
616 { X86::CMPSDrr, X86::CMPSDrm, 0 },
617 { X86::CMPSSrr, X86::CMPSSrm, 0 },
618 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
619 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
620 { X86::DIVSDrr, X86::DIVSDrm, 0 },
621 { X86::DIVSSrr, X86::DIVSSrm, 0 },
622 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
623 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
624 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
625 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
626 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
627 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
628 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
629 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
630 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
631 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
632 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
633 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
634 { X86::IMUL16rr, X86::IMUL16rm, 0 },
635 { X86::IMUL32rr, X86::IMUL32rm, 0 },
636 { X86::IMUL64rr, X86::IMUL64rm, 0 },
637 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
638 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
639 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
640 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, TB_ALIGN_16 },
641 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
642 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, TB_ALIGN_16 },
643 { X86::MAXSDrr, X86::MAXSDrm, 0 },
644 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
645 { X86::MAXSSrr, X86::MAXSSrm, 0 },
646 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
647 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
648 { X86::MINPDrr_Int, X86::MINPDrm_Int, TB_ALIGN_16 },
649 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
650 { X86::MINPSrr_Int, X86::MINPSrm_Int, TB_ALIGN_16 },
651 { X86::MINSDrr, X86::MINSDrm, 0 },
652 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
653 { X86::MINSSrr, X86::MINSSrm, 0 },
654 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
655 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
656 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
657 { X86::MULSDrr, X86::MULSDrm, 0 },
658 { X86::MULSSrr, X86::MULSSrm, 0 },
659 { X86::OR16rr, X86::OR16rm, 0 },
660 { X86::OR32rr, X86::OR32rm, 0 },
661 { X86::OR64rr, X86::OR64rm, 0 },
662 { X86::OR8rr, X86::OR8rm, 0 },
663 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
664 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
665 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
666 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
667 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
668 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
669 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
670 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
671 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
672 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
673 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
674 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
675 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
676 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
677 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
678 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
679 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
680 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
681 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
682 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
683 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
684 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 },
685 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
686 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
687 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
688 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
689 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
690 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
691 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
692 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
693 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
694 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
695 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
696 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
697 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
698 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
699 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
700 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
701 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
702 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
703 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
704 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
705 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
706 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
707 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
708 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
709 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
710 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
711 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
712 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
713 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
714 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
715 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
716 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
717 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
718 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
719 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
720 { X86::SBB32rr, X86::SBB32rm, 0 },
721 { X86::SBB64rr, X86::SBB64rm, 0 },
722 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
723 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
724 { X86::SUB16rr, X86::SUB16rm, 0 },
725 { X86::SUB32rr, X86::SUB32rm, 0 },
726 { X86::SUB64rr, X86::SUB64rm, 0 },
727 { X86::SUB8rr, X86::SUB8rm, 0 },
728 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
729 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
730 { X86::SUBSDrr, X86::SUBSDrm, 0 },
731 { X86::SUBSSrr, X86::SUBSSrm, 0 },
732 // FIXME: TEST*rr -> swapped operand of TEST*mr.
733 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
734 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
735 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
736 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
737 { X86::XOR16rr, X86::XOR16rm, 0 },
738 { X86::XOR32rr, X86::XOR32rm, 0 },
739 { X86::XOR64rr, X86::XOR64rm, 0 },
740 { X86::XOR8rr, X86::XOR8rm, 0 },
741 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
742 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
743 // AVX 128-bit versions of foldable instructions
744 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
745 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
746 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
747 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
748 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
749 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
750 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
751 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
752 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
753 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
754 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
755 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
756 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
757 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm, 0 },
758 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
759 { X86::Int_VCVTTSD2SIrr, X86::Int_VCVTTSD2SIrm, 0 },
760 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
761 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm, 0 },
762 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
763 { X86::Int_VCVTTSS2SIrr, X86::Int_VCVTTSS2SIrm, 0 },
764 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
765 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
766 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQrm, TB_ALIGN_16 },
767 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, TB_ALIGN_16 },
768 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
769 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
770 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
771 { X86::VADDPDrr, X86::VADDPDrm, TB_ALIGN_16 },
772 { X86::VADDPSrr, X86::VADDPSrm, TB_ALIGN_16 },
773 { X86::VADDSDrr, X86::VADDSDrm, 0 },
774 { X86::VADDSSrr, X86::VADDSSrm, 0 },
775 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, TB_ALIGN_16 },
776 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, TB_ALIGN_16 },
777 { X86::VANDNPDrr, X86::VANDNPDrm, TB_ALIGN_16 },
778 { X86::VANDNPSrr, X86::VANDNPSrm, TB_ALIGN_16 },
779 { X86::VANDPDrr, X86::VANDPDrm, TB_ALIGN_16 },
780 { X86::VANDPSrr, X86::VANDPSrm, TB_ALIGN_16 },
781 { X86::VCMPPDrri, X86::VCMPPDrmi, TB_ALIGN_16 },
782 { X86::VCMPPSrri, X86::VCMPPSrmi, TB_ALIGN_16 },
783 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
784 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
785 { X86::VDIVPDrr, X86::VDIVPDrm, TB_ALIGN_16 },
786 { X86::VDIVPSrr, X86::VDIVPSrm, TB_ALIGN_16 },
787 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
788 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
789 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 },
790 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 },
791 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 },
792 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 },
793 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 },
794 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 },
795 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 },
796 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 },
797 { X86::VHADDPDrr, X86::VHADDPDrm, TB_ALIGN_16 },
798 { X86::VHADDPSrr, X86::VHADDPSrm, TB_ALIGN_16 },
799 { X86::VHSUBPDrr, X86::VHSUBPDrm, TB_ALIGN_16 },
800 { X86::VHSUBPSrr, X86::VHSUBPSrm, TB_ALIGN_16 },
801 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
802 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
803 { X86::VMAXPDrr, X86::VMAXPDrm, TB_ALIGN_16 },
804 { X86::VMAXPDrr_Int, X86::VMAXPDrm_Int, TB_ALIGN_16 },
805 { X86::VMAXPSrr, X86::VMAXPSrm, TB_ALIGN_16 },
806 { X86::VMAXPSrr_Int, X86::VMAXPSrm_Int, TB_ALIGN_16 },
807 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
808 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
809 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
810 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
811 { X86::VMINPDrr, X86::VMINPDrm, TB_ALIGN_16 },
812 { X86::VMINPDrr_Int, X86::VMINPDrm_Int, TB_ALIGN_16 },
813 { X86::VMINPSrr, X86::VMINPSrm, TB_ALIGN_16 },
814 { X86::VMINPSrr_Int, X86::VMINPSrm_Int, TB_ALIGN_16 },
815 { X86::VMINSDrr, X86::VMINSDrm, 0 },
816 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
817 { X86::VMINSSrr, X86::VMINSSrm, 0 },
818 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
819 { X86::VMULPDrr, X86::VMULPDrm, TB_ALIGN_16 },
820 { X86::VMULPSrr, X86::VMULPSrm, TB_ALIGN_16 },
821 { X86::VMULSDrr, X86::VMULSDrm, 0 },
822 { X86::VMULSSrr, X86::VMULSSrm, 0 },
823 { X86::VORPDrr, X86::VORPDrm, TB_ALIGN_16 },
824 { X86::VORPSrr, X86::VORPSrm, TB_ALIGN_16 },
825 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, TB_ALIGN_16 },
826 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, TB_ALIGN_16 },
827 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, TB_ALIGN_16 },
828 { X86::VPADDBrr, X86::VPADDBrm, TB_ALIGN_16 },
829 { X86::VPADDDrr, X86::VPADDDrm, TB_ALIGN_16 },
830 { X86::VPADDQrr, X86::VPADDQrm, TB_ALIGN_16 },
831 { X86::VPADDSBrr, X86::VPADDSBrm, TB_ALIGN_16 },
832 { X86::VPADDSWrr, X86::VPADDSWrm, TB_ALIGN_16 },
833 { X86::VPADDWrr, X86::VPADDWrm, TB_ALIGN_16 },
834 { X86::VPANDNrr, X86::VPANDNrm, TB_ALIGN_16 },
835 { X86::VPANDrr, X86::VPANDrm, TB_ALIGN_16 },
836 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, TB_ALIGN_16 },
837 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, TB_ALIGN_16 },
838 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, TB_ALIGN_16 },
839 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, TB_ALIGN_16 },
840 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, TB_ALIGN_16 },
841 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, TB_ALIGN_16 },
842 { X86::VPINSRWrri, X86::VPINSRWrmi, TB_ALIGN_16 },
843 { X86::VPMADDWDrr, X86::VPMADDWDrm, TB_ALIGN_16 },
844 { X86::VPMAXSWrr, X86::VPMAXSWrm, TB_ALIGN_16 },
845 { X86::VPMAXUBrr, X86::VPMAXUBrm, TB_ALIGN_16 },
846 { X86::VPMINSWrr, X86::VPMINSWrm, TB_ALIGN_16 },
847 { X86::VPMINUBrr, X86::VPMINUBrm, TB_ALIGN_16 },
848 { X86::VPMULDQrr, X86::VPMULDQrm, TB_ALIGN_16 },
849 { X86::VPMULHUWrr, X86::VPMULHUWrm, TB_ALIGN_16 },
850 { X86::VPMULHWrr, X86::VPMULHWrm, TB_ALIGN_16 },
851 { X86::VPMULLDrr, X86::VPMULLDrm, TB_ALIGN_16 },
852 { X86::VPMULLWrr, X86::VPMULLWrm, TB_ALIGN_16 },
853 { X86::VPMULUDQrr, X86::VPMULUDQrm, TB_ALIGN_16 },
854 { X86::VPORrr, X86::VPORrm, TB_ALIGN_16 },
855 { X86::VPSADBWrr, X86::VPSADBWrm, TB_ALIGN_16 },
856 { X86::VPSLLDrr, X86::VPSLLDrm, TB_ALIGN_16 },
857 { X86::VPSLLQrr, X86::VPSLLQrm, TB_ALIGN_16 },
858 { X86::VPSLLWrr, X86::VPSLLWrm, TB_ALIGN_16 },
859 { X86::VPSRADrr, X86::VPSRADrm, TB_ALIGN_16 },
860 { X86::VPSRAWrr, X86::VPSRAWrm, TB_ALIGN_16 },
861 { X86::VPSRLDrr, X86::VPSRLDrm, TB_ALIGN_16 },
862 { X86::VPSRLQrr, X86::VPSRLQrm, TB_ALIGN_16 },
863 { X86::VPSRLWrr, X86::VPSRLWrm, TB_ALIGN_16 },
864 { X86::VPSUBBrr, X86::VPSUBBrm, TB_ALIGN_16 },
865 { X86::VPSUBDrr, X86::VPSUBDrm, TB_ALIGN_16 },
866 { X86::VPSUBSBrr, X86::VPSUBSBrm, TB_ALIGN_16 },
867 { X86::VPSUBSWrr, X86::VPSUBSWrm, TB_ALIGN_16 },
868 { X86::VPSUBWrr, X86::VPSUBWrm, TB_ALIGN_16 },
869 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, TB_ALIGN_16 },
870 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, TB_ALIGN_16 },
871 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, TB_ALIGN_16 },
872 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, TB_ALIGN_16 },
873 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, TB_ALIGN_16 },
874 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, TB_ALIGN_16 },
875 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, TB_ALIGN_16 },
876 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, TB_ALIGN_16 },
877 { X86::VPXORrr, X86::VPXORrm, TB_ALIGN_16 },
878 { X86::VSHUFPDrri, X86::VSHUFPDrmi, TB_ALIGN_16 },
879 { X86::VSHUFPSrri, X86::VSHUFPSrmi, TB_ALIGN_16 },
880 { X86::VSUBPDrr, X86::VSUBPDrm, TB_ALIGN_16 },
881 { X86::VSUBPSrr, X86::VSUBPSrm, TB_ALIGN_16 },
882 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
883 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
884 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, TB_ALIGN_16 },
885 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, TB_ALIGN_16 },
886 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, TB_ALIGN_16 },
887 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, TB_ALIGN_16 },
888 { X86::VXORPDrr, X86::VXORPDrm, TB_ALIGN_16 },
889 { X86::VXORPSrr, X86::VXORPSrm, TB_ALIGN_16 }
890 // FIXME: add AVX 256-bit foldable instructions
891 };
892
893 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
894 unsigned RegOp = OpTbl2[i][0];
895 unsigned MemOp = OpTbl2[i][1];
896 unsigned Flags = OpTbl2[i][2];
897 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
898 RegOp, MemOp,
899 // Index 2, folded load
900 Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
901 }
902 }
903
904 void
AddTableEntry(RegOp2MemOpTableType & R2MTable,MemOp2RegOpTableType & M2RTable,unsigned RegOp,unsigned MemOp,unsigned Flags)905 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
906 MemOp2RegOpTableType &M2RTable,
907 unsigned RegOp, unsigned MemOp, unsigned Flags) {
908 if ((Flags & TB_NO_FORWARD) == 0) {
909 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
910 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
911 }
912 if ((Flags & TB_NO_REVERSE) == 0) {
913 assert(!M2RTable.count(MemOp) &&
914 "Duplicated entries in unfolding maps?");
915 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
916 }
917 }
918
919 bool
isCoalescableExtInstr(const MachineInstr & MI,unsigned & SrcReg,unsigned & DstReg,unsigned & SubIdx) const920 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
921 unsigned &SrcReg, unsigned &DstReg,
922 unsigned &SubIdx) const {
923 switch (MI.getOpcode()) {
924 default: break;
925 case X86::MOVSX16rr8:
926 case X86::MOVZX16rr8:
927 case X86::MOVSX32rr8:
928 case X86::MOVZX32rr8:
929 case X86::MOVSX64rr8:
930 case X86::MOVZX64rr8:
931 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
932 // It's not always legal to reference the low 8-bit of the larger
933 // register in 32-bit mode.
934 return false;
935 case X86::MOVSX32rr16:
936 case X86::MOVZX32rr16:
937 case X86::MOVSX64rr16:
938 case X86::MOVZX64rr16:
939 case X86::MOVSX64rr32:
940 case X86::MOVZX64rr32: {
941 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
942 // Be conservative.
943 return false;
944 SrcReg = MI.getOperand(1).getReg();
945 DstReg = MI.getOperand(0).getReg();
946 switch (MI.getOpcode()) {
947 default:
948 llvm_unreachable(0);
949 break;
950 case X86::MOVSX16rr8:
951 case X86::MOVZX16rr8:
952 case X86::MOVSX32rr8:
953 case X86::MOVZX32rr8:
954 case X86::MOVSX64rr8:
955 case X86::MOVZX64rr8:
956 SubIdx = X86::sub_8bit;
957 break;
958 case X86::MOVSX32rr16:
959 case X86::MOVZX32rr16:
960 case X86::MOVSX64rr16:
961 case X86::MOVZX64rr16:
962 SubIdx = X86::sub_16bit;
963 break;
964 case X86::MOVSX64rr32:
965 case X86::MOVZX64rr32:
966 SubIdx = X86::sub_32bit;
967 break;
968 }
969 return true;
970 }
971 }
972 return false;
973 }
974
975 /// isFrameOperand - Return true and the FrameIndex if the specified
976 /// operand and follow operands form a reference to the stack frame.
isFrameOperand(const MachineInstr * MI,unsigned int Op,int & FrameIndex) const977 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
978 int &FrameIndex) const {
979 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
980 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
981 MI->getOperand(Op+1).getImm() == 1 &&
982 MI->getOperand(Op+2).getReg() == 0 &&
983 MI->getOperand(Op+3).getImm() == 0) {
984 FrameIndex = MI->getOperand(Op).getIndex();
985 return true;
986 }
987 return false;
988 }
989
isFrameLoadOpcode(int Opcode)990 static bool isFrameLoadOpcode(int Opcode) {
991 switch (Opcode) {
992 default: break;
993 case X86::MOV8rm:
994 case X86::MOV16rm:
995 case X86::MOV32rm:
996 case X86::MOV64rm:
997 case X86::LD_Fp64m:
998 case X86::MOVSSrm:
999 case X86::MOVSDrm:
1000 case X86::MOVAPSrm:
1001 case X86::MOVAPDrm:
1002 case X86::MOVDQArm:
1003 case X86::VMOVSSrm:
1004 case X86::VMOVSDrm:
1005 case X86::VMOVAPSrm:
1006 case X86::VMOVAPDrm:
1007 case X86::VMOVDQArm:
1008 case X86::VMOVAPSYrm:
1009 case X86::VMOVAPDYrm:
1010 case X86::VMOVDQAYrm:
1011 case X86::MMX_MOVD64rm:
1012 case X86::MMX_MOVQ64rm:
1013 return true;
1014 break;
1015 }
1016 return false;
1017 }
1018
isFrameStoreOpcode(int Opcode)1019 static bool isFrameStoreOpcode(int Opcode) {
1020 switch (Opcode) {
1021 default: break;
1022 case X86::MOV8mr:
1023 case X86::MOV16mr:
1024 case X86::MOV32mr:
1025 case X86::MOV64mr:
1026 case X86::ST_FpP64m:
1027 case X86::MOVSSmr:
1028 case X86::MOVSDmr:
1029 case X86::MOVAPSmr:
1030 case X86::MOVAPDmr:
1031 case X86::MOVDQAmr:
1032 case X86::VMOVSSmr:
1033 case X86::VMOVSDmr:
1034 case X86::VMOVAPSmr:
1035 case X86::VMOVAPDmr:
1036 case X86::VMOVDQAmr:
1037 case X86::VMOVAPSYmr:
1038 case X86::VMOVAPDYmr:
1039 case X86::VMOVDQAYmr:
1040 case X86::MMX_MOVD64mr:
1041 case X86::MMX_MOVQ64mr:
1042 case X86::MMX_MOVNTQmr:
1043 return true;
1044 }
1045 return false;
1046 }
1047
isLoadFromStackSlot(const MachineInstr * MI,int & FrameIndex) const1048 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1049 int &FrameIndex) const {
1050 if (isFrameLoadOpcode(MI->getOpcode()))
1051 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1052 return MI->getOperand(0).getReg();
1053 return 0;
1054 }
1055
isLoadFromStackSlotPostFE(const MachineInstr * MI,int & FrameIndex) const1056 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1057 int &FrameIndex) const {
1058 if (isFrameLoadOpcode(MI->getOpcode())) {
1059 unsigned Reg;
1060 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1061 return Reg;
1062 // Check for post-frame index elimination operations
1063 const MachineMemOperand *Dummy;
1064 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1065 }
1066 return 0;
1067 }
1068
isStoreToStackSlot(const MachineInstr * MI,int & FrameIndex) const1069 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1070 int &FrameIndex) const {
1071 if (isFrameStoreOpcode(MI->getOpcode()))
1072 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1073 isFrameOperand(MI, 0, FrameIndex))
1074 return MI->getOperand(X86::AddrNumOperands).getReg();
1075 return 0;
1076 }
1077
isStoreToStackSlotPostFE(const MachineInstr * MI,int & FrameIndex) const1078 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1079 int &FrameIndex) const {
1080 if (isFrameStoreOpcode(MI->getOpcode())) {
1081 unsigned Reg;
1082 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1083 return Reg;
1084 // Check for post-frame index elimination operations
1085 const MachineMemOperand *Dummy;
1086 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1087 }
1088 return 0;
1089 }
1090
1091 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1092 /// X86::MOVPC32r.
regIsPICBase(unsigned BaseReg,const MachineRegisterInfo & MRI)1093 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1094 bool isPICBase = false;
1095 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1096 E = MRI.def_end(); I != E; ++I) {
1097 MachineInstr *DefMI = I.getOperand().getParent();
1098 if (DefMI->getOpcode() != X86::MOVPC32r)
1099 return false;
1100 assert(!isPICBase && "More than one PIC base?");
1101 isPICBase = true;
1102 }
1103 return isPICBase;
1104 }
1105
1106 bool
isReallyTriviallyReMaterializable(const MachineInstr * MI,AliasAnalysis * AA) const1107 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1108 AliasAnalysis *AA) const {
1109 switch (MI->getOpcode()) {
1110 default: break;
1111 case X86::MOV8rm:
1112 case X86::MOV16rm:
1113 case X86::MOV32rm:
1114 case X86::MOV64rm:
1115 case X86::LD_Fp64m:
1116 case X86::MOVSSrm:
1117 case X86::MOVSDrm:
1118 case X86::MOVAPSrm:
1119 case X86::MOVUPSrm:
1120 case X86::MOVAPDrm:
1121 case X86::MOVDQArm:
1122 case X86::VMOVSSrm:
1123 case X86::VMOVSDrm:
1124 case X86::VMOVAPSrm:
1125 case X86::VMOVUPSrm:
1126 case X86::VMOVAPDrm:
1127 case X86::VMOVDQArm:
1128 case X86::VMOVAPSYrm:
1129 case X86::VMOVUPSYrm:
1130 case X86::VMOVAPDYrm:
1131 case X86::VMOVDQAYrm:
1132 case X86::MMX_MOVD64rm:
1133 case X86::MMX_MOVQ64rm:
1134 case X86::FsVMOVAPSrm:
1135 case X86::FsVMOVAPDrm:
1136 case X86::FsMOVAPSrm:
1137 case X86::FsMOVAPDrm: {
1138 // Loads from constant pools are trivially rematerializable.
1139 if (MI->getOperand(1).isReg() &&
1140 MI->getOperand(2).isImm() &&
1141 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1142 MI->isInvariantLoad(AA)) {
1143 unsigned BaseReg = MI->getOperand(1).getReg();
1144 if (BaseReg == 0 || BaseReg == X86::RIP)
1145 return true;
1146 // Allow re-materialization of PIC load.
1147 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
1148 return false;
1149 const MachineFunction &MF = *MI->getParent()->getParent();
1150 const MachineRegisterInfo &MRI = MF.getRegInfo();
1151 bool isPICBase = false;
1152 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1153 E = MRI.def_end(); I != E; ++I) {
1154 MachineInstr *DefMI = I.getOperand().getParent();
1155 if (DefMI->getOpcode() != X86::MOVPC32r)
1156 return false;
1157 assert(!isPICBase && "More than one PIC base?");
1158 isPICBase = true;
1159 }
1160 return isPICBase;
1161 }
1162 return false;
1163 }
1164
1165 case X86::LEA32r:
1166 case X86::LEA64r: {
1167 if (MI->getOperand(2).isImm() &&
1168 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1169 !MI->getOperand(4).isReg()) {
1170 // lea fi#, lea GV, etc. are all rematerializable.
1171 if (!MI->getOperand(1).isReg())
1172 return true;
1173 unsigned BaseReg = MI->getOperand(1).getReg();
1174 if (BaseReg == 0)
1175 return true;
1176 // Allow re-materialization of lea PICBase + x.
1177 const MachineFunction &MF = *MI->getParent()->getParent();
1178 const MachineRegisterInfo &MRI = MF.getRegInfo();
1179 return regIsPICBase(BaseReg, MRI);
1180 }
1181 return false;
1182 }
1183 }
1184
1185 // All other instructions marked M_REMATERIALIZABLE are always trivially
1186 // rematerializable.
1187 return true;
1188 }
1189
1190 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
1191 /// would clobber the EFLAGS condition register. Note the result may be
1192 /// conservative. If it cannot definitely determine the safety after visiting
1193 /// a few instructions in each direction it assumes it's not safe.
isSafeToClobberEFLAGS(MachineBasicBlock & MBB,MachineBasicBlock::iterator I)1194 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1195 MachineBasicBlock::iterator I) {
1196 MachineBasicBlock::iterator E = MBB.end();
1197
1198 // For compile time consideration, if we are not able to determine the
1199 // safety after visiting 4 instructions in each direction, we will assume
1200 // it's not safe.
1201 MachineBasicBlock::iterator Iter = I;
1202 for (unsigned i = 0; Iter != E && i < 4; ++i) {
1203 bool SeenDef = false;
1204 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1205 MachineOperand &MO = Iter->getOperand(j);
1206 if (!MO.isReg())
1207 continue;
1208 if (MO.getReg() == X86::EFLAGS) {
1209 if (MO.isUse())
1210 return false;
1211 SeenDef = true;
1212 }
1213 }
1214
1215 if (SeenDef)
1216 // This instruction defines EFLAGS, no need to look any further.
1217 return true;
1218 ++Iter;
1219 // Skip over DBG_VALUE.
1220 while (Iter != E && Iter->isDebugValue())
1221 ++Iter;
1222 }
1223
1224 // It is safe to clobber EFLAGS at the end of a block of no successor has it
1225 // live in.
1226 if (Iter == E) {
1227 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1228 SE = MBB.succ_end(); SI != SE; ++SI)
1229 if ((*SI)->isLiveIn(X86::EFLAGS))
1230 return false;
1231 return true;
1232 }
1233
1234 MachineBasicBlock::iterator B = MBB.begin();
1235 Iter = I;
1236 for (unsigned i = 0; i < 4; ++i) {
1237 // If we make it to the beginning of the block, it's safe to clobber
1238 // EFLAGS iff EFLAGS is not live-in.
1239 if (Iter == B)
1240 return !MBB.isLiveIn(X86::EFLAGS);
1241
1242 --Iter;
1243 // Skip over DBG_VALUE.
1244 while (Iter != B && Iter->isDebugValue())
1245 --Iter;
1246
1247 bool SawKill = false;
1248 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1249 MachineOperand &MO = Iter->getOperand(j);
1250 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1251 if (MO.isDef()) return MO.isDead();
1252 if (MO.isKill()) SawKill = true;
1253 }
1254 }
1255
1256 if (SawKill)
1257 // This instruction kills EFLAGS and doesn't redefine it, so
1258 // there's no need to look further.
1259 return true;
1260 }
1261
1262 // Conservative answer.
1263 return false;
1264 }
1265
reMaterialize(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned DestReg,unsigned SubIdx,const MachineInstr * Orig,const TargetRegisterInfo & TRI) const1266 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1267 MachineBasicBlock::iterator I,
1268 unsigned DestReg, unsigned SubIdx,
1269 const MachineInstr *Orig,
1270 const TargetRegisterInfo &TRI) const {
1271 DebugLoc DL = Orig->getDebugLoc();
1272
1273 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1274 // Re-materialize them as movri instructions to avoid side effects.
1275 bool Clone = true;
1276 unsigned Opc = Orig->getOpcode();
1277 switch (Opc) {
1278 default: break;
1279 case X86::MOV8r0:
1280 case X86::MOV16r0:
1281 case X86::MOV32r0:
1282 case X86::MOV64r0: {
1283 if (!isSafeToClobberEFLAGS(MBB, I)) {
1284 switch (Opc) {
1285 default: break;
1286 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1287 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1288 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1289 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1290 }
1291 Clone = false;
1292 }
1293 break;
1294 }
1295 }
1296
1297 if (Clone) {
1298 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1299 MBB.insert(I, MI);
1300 } else {
1301 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
1302 }
1303
1304 MachineInstr *NewMI = prior(I);
1305 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1306 }
1307
1308 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1309 /// is not marked dead.
hasLiveCondCodeDef(MachineInstr * MI)1310 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1311 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1312 MachineOperand &MO = MI->getOperand(i);
1313 if (MO.isReg() && MO.isDef() &&
1314 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1315 return true;
1316 }
1317 }
1318 return false;
1319 }
1320
1321 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1322 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1323 /// to a 32-bit superregister and then truncating back down to a 16-bit
1324 /// subregister.
1325 MachineInstr *
convertToThreeAddressWithLEA(unsigned MIOpc,MachineFunction::iterator & MFI,MachineBasicBlock::iterator & MBBI,LiveVariables * LV) const1326 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1327 MachineFunction::iterator &MFI,
1328 MachineBasicBlock::iterator &MBBI,
1329 LiveVariables *LV) const {
1330 MachineInstr *MI = MBBI;
1331 unsigned Dest = MI->getOperand(0).getReg();
1332 unsigned Src = MI->getOperand(1).getReg();
1333 bool isDead = MI->getOperand(0).isDead();
1334 bool isKill = MI->getOperand(1).isKill();
1335
1336 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1337 ? X86::LEA64_32r : X86::LEA32r;
1338 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1339 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1340 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1341
1342 // Build and insert into an implicit UNDEF value. This is OK because
1343 // well be shifting and then extracting the lower 16-bits.
1344 // This has the potential to cause partial register stall. e.g.
1345 // movw (%rbp,%rcx,2), %dx
1346 // leal -65(%rdx), %esi
1347 // But testing has shown this *does* help performance in 64-bit mode (at
1348 // least on modern x86 machines).
1349 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1350 MachineInstr *InsMI =
1351 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1352 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1353 .addReg(Src, getKillRegState(isKill));
1354
1355 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1356 get(Opc), leaOutReg);
1357 switch (MIOpc) {
1358 default:
1359 llvm_unreachable(0);
1360 break;
1361 case X86::SHL16ri: {
1362 unsigned ShAmt = MI->getOperand(2).getImm();
1363 MIB.addReg(0).addImm(1 << ShAmt)
1364 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1365 break;
1366 }
1367 case X86::INC16r:
1368 case X86::INC64_16r:
1369 addRegOffset(MIB, leaInReg, true, 1);
1370 break;
1371 case X86::DEC16r:
1372 case X86::DEC64_16r:
1373 addRegOffset(MIB, leaInReg, true, -1);
1374 break;
1375 case X86::ADD16ri:
1376 case X86::ADD16ri8:
1377 case X86::ADD16ri_DB:
1378 case X86::ADD16ri8_DB:
1379 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1380 break;
1381 case X86::ADD16rr:
1382 case X86::ADD16rr_DB: {
1383 unsigned Src2 = MI->getOperand(2).getReg();
1384 bool isKill2 = MI->getOperand(2).isKill();
1385 unsigned leaInReg2 = 0;
1386 MachineInstr *InsMI2 = 0;
1387 if (Src == Src2) {
1388 // ADD16rr %reg1028<kill>, %reg1028
1389 // just a single insert_subreg.
1390 addRegReg(MIB, leaInReg, true, leaInReg, false);
1391 } else {
1392 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1393 // Build and insert into an implicit UNDEF value. This is OK because
1394 // well be shifting and then extracting the lower 16-bits.
1395 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
1396 InsMI2 =
1397 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1398 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1399 .addReg(Src2, getKillRegState(isKill2));
1400 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1401 }
1402 if (LV && isKill2 && InsMI2)
1403 LV->replaceKillInstruction(Src2, MI, InsMI2);
1404 break;
1405 }
1406 }
1407
1408 MachineInstr *NewMI = MIB;
1409 MachineInstr *ExtMI =
1410 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1411 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1412 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
1413
1414 if (LV) {
1415 // Update live variables
1416 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1417 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1418 if (isKill)
1419 LV->replaceKillInstruction(Src, MI, InsMI);
1420 if (isDead)
1421 LV->replaceKillInstruction(Dest, MI, ExtMI);
1422 }
1423
1424 return ExtMI;
1425 }
1426
1427 /// convertToThreeAddress - This method must be implemented by targets that
1428 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1429 /// may be able to convert a two-address instruction into a true
1430 /// three-address instruction on demand. This allows the X86 target (for
1431 /// example) to convert ADD and SHL instructions into LEA instructions if they
1432 /// would require register copies due to two-addressness.
1433 ///
1434 /// This method returns a null pointer if the transformation cannot be
1435 /// performed, otherwise it returns the new instruction.
1436 ///
1437 MachineInstr *
convertToThreeAddress(MachineFunction::iterator & MFI,MachineBasicBlock::iterator & MBBI,LiveVariables * LV) const1438 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1439 MachineBasicBlock::iterator &MBBI,
1440 LiveVariables *LV) const {
1441 MachineInstr *MI = MBBI;
1442 MachineFunction &MF = *MI->getParent()->getParent();
1443 // All instructions input are two-addr instructions. Get the known operands.
1444 unsigned Dest = MI->getOperand(0).getReg();
1445 unsigned Src = MI->getOperand(1).getReg();
1446 bool isDead = MI->getOperand(0).isDead();
1447 bool isKill = MI->getOperand(1).isKill();
1448
1449 MachineInstr *NewMI = NULL;
1450 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1451 // we have better subtarget support, enable the 16-bit LEA generation here.
1452 // 16-bit LEA is also slow on Core2.
1453 bool DisableLEA16 = true;
1454 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1455
1456 unsigned MIOpc = MI->getOpcode();
1457 switch (MIOpc) {
1458 case X86::SHUFPSrri: {
1459 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1460 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1461
1462 unsigned B = MI->getOperand(1).getReg();
1463 unsigned C = MI->getOperand(2).getReg();
1464 if (B != C) return 0;
1465 unsigned A = MI->getOperand(0).getReg();
1466 unsigned M = MI->getOperand(3).getImm();
1467 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1468 .addReg(A, RegState::Define | getDeadRegState(isDead))
1469 .addReg(B, getKillRegState(isKill)).addImm(M);
1470 break;
1471 }
1472 case X86::SHL64ri: {
1473 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1474 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1475 // the flags produced by a shift yet, so this is safe.
1476 unsigned ShAmt = MI->getOperand(2).getImm();
1477 if (ShAmt == 0 || ShAmt >= 4) return 0;
1478
1479 // LEA can't handle RSP.
1480 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1481 !MF.getRegInfo().constrainRegClass(Src, &X86::GR64_NOSPRegClass))
1482 return 0;
1483
1484 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1485 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1486 .addReg(0).addImm(1 << ShAmt)
1487 .addReg(Src, getKillRegState(isKill))
1488 .addImm(0).addReg(0);
1489 break;
1490 }
1491 case X86::SHL32ri: {
1492 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1493 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1494 // the flags produced by a shift yet, so this is safe.
1495 unsigned ShAmt = MI->getOperand(2).getImm();
1496 if (ShAmt == 0 || ShAmt >= 4) return 0;
1497
1498 // LEA can't handle ESP.
1499 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1500 !MF.getRegInfo().constrainRegClass(Src, &X86::GR32_NOSPRegClass))
1501 return 0;
1502
1503 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1504 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1505 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1506 .addReg(0).addImm(1 << ShAmt)
1507 .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0);
1508 break;
1509 }
1510 case X86::SHL16ri: {
1511 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1512 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1513 // the flags produced by a shift yet, so this is safe.
1514 unsigned ShAmt = MI->getOperand(2).getImm();
1515 if (ShAmt == 0 || ShAmt >= 4) return 0;
1516
1517 if (DisableLEA16)
1518 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1519 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1520 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1521 .addReg(0).addImm(1 << ShAmt)
1522 .addReg(Src, getKillRegState(isKill))
1523 .addImm(0).addReg(0);
1524 break;
1525 }
1526 default: {
1527 // The following opcodes also sets the condition code register(s). Only
1528 // convert them to equivalent lea if the condition code register def's
1529 // are dead!
1530 if (hasLiveCondCodeDef(MI))
1531 return 0;
1532
1533 switch (MIOpc) {
1534 default: return 0;
1535 case X86::INC64r:
1536 case X86::INC32r:
1537 case X86::INC64_32r: {
1538 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1539 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1540 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1541
1542 // LEA can't handle RSP.
1543 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1544 !MF.getRegInfo().constrainRegClass(Src,
1545 MIOpc == X86::INC64r ? X86::GR64_NOSPRegisterClass :
1546 X86::GR32_NOSPRegisterClass))
1547 return 0;
1548
1549 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1550 .addReg(Dest, RegState::Define |
1551 getDeadRegState(isDead)),
1552 Src, isKill, 1);
1553 break;
1554 }
1555 case X86::INC16r:
1556 case X86::INC64_16r:
1557 if (DisableLEA16)
1558 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1559 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1560 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1561 .addReg(Dest, RegState::Define |
1562 getDeadRegState(isDead)),
1563 Src, isKill, 1);
1564 break;
1565 case X86::DEC64r:
1566 case X86::DEC32r:
1567 case X86::DEC64_32r: {
1568 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1569 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1570 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1571 // LEA can't handle RSP.
1572 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1573 !MF.getRegInfo().constrainRegClass(Src,
1574 MIOpc == X86::DEC64r ? X86::GR64_NOSPRegisterClass :
1575 X86::GR32_NOSPRegisterClass))
1576 return 0;
1577
1578 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1579 .addReg(Dest, RegState::Define |
1580 getDeadRegState(isDead)),
1581 Src, isKill, -1);
1582 break;
1583 }
1584 case X86::DEC16r:
1585 case X86::DEC64_16r:
1586 if (DisableLEA16)
1587 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1588 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1589 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1590 .addReg(Dest, RegState::Define |
1591 getDeadRegState(isDead)),
1592 Src, isKill, -1);
1593 break;
1594 case X86::ADD64rr:
1595 case X86::ADD64rr_DB:
1596 case X86::ADD32rr:
1597 case X86::ADD32rr_DB: {
1598 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1599 unsigned Opc;
1600 TargetRegisterClass *RC;
1601 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
1602 Opc = X86::LEA64r;
1603 RC = X86::GR64_NOSPRegisterClass;
1604 } else {
1605 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1606 RC = X86::GR32_NOSPRegisterClass;
1607 }
1608
1609
1610 unsigned Src2 = MI->getOperand(2).getReg();
1611 bool isKill2 = MI->getOperand(2).isKill();
1612
1613 // LEA can't handle RSP.
1614 if (TargetRegisterInfo::isVirtualRegister(Src2) &&
1615 !MF.getRegInfo().constrainRegClass(Src2, RC))
1616 return 0;
1617
1618 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1619 .addReg(Dest, RegState::Define |
1620 getDeadRegState(isDead)),
1621 Src, isKill, Src2, isKill2);
1622 if (LV && isKill2)
1623 LV->replaceKillInstruction(Src2, MI, NewMI);
1624 break;
1625 }
1626 case X86::ADD16rr:
1627 case X86::ADD16rr_DB: {
1628 if (DisableLEA16)
1629 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1630 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1631 unsigned Src2 = MI->getOperand(2).getReg();
1632 bool isKill2 = MI->getOperand(2).isKill();
1633 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1634 .addReg(Dest, RegState::Define |
1635 getDeadRegState(isDead)),
1636 Src, isKill, Src2, isKill2);
1637 if (LV && isKill2)
1638 LV->replaceKillInstruction(Src2, MI, NewMI);
1639 break;
1640 }
1641 case X86::ADD64ri32:
1642 case X86::ADD64ri8:
1643 case X86::ADD64ri32_DB:
1644 case X86::ADD64ri8_DB:
1645 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1646 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1647 .addReg(Dest, RegState::Define |
1648 getDeadRegState(isDead)),
1649 Src, isKill, MI->getOperand(2).getImm());
1650 break;
1651 case X86::ADD32ri:
1652 case X86::ADD32ri8:
1653 case X86::ADD32ri_DB:
1654 case X86::ADD32ri8_DB: {
1655 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1656 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1657 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1658 .addReg(Dest, RegState::Define |
1659 getDeadRegState(isDead)),
1660 Src, isKill, MI->getOperand(2).getImm());
1661 break;
1662 }
1663 case X86::ADD16ri:
1664 case X86::ADD16ri8:
1665 case X86::ADD16ri_DB:
1666 case X86::ADD16ri8_DB:
1667 if (DisableLEA16)
1668 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1669 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1670 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1671 .addReg(Dest, RegState::Define |
1672 getDeadRegState(isDead)),
1673 Src, isKill, MI->getOperand(2).getImm());
1674 break;
1675 }
1676 }
1677 }
1678
1679 if (!NewMI) return 0;
1680
1681 if (LV) { // Update live variables
1682 if (isKill)
1683 LV->replaceKillInstruction(Src, MI, NewMI);
1684 if (isDead)
1685 LV->replaceKillInstruction(Dest, MI, NewMI);
1686 }
1687
1688 MFI->insert(MBBI, NewMI); // Insert the new inst
1689 return NewMI;
1690 }
1691
1692 /// commuteInstruction - We have a few instructions that must be hacked on to
1693 /// commute them.
1694 ///
1695 MachineInstr *
commuteInstruction(MachineInstr * MI,bool NewMI) const1696 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1697 switch (MI->getOpcode()) {
1698 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1699 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1700 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1701 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1702 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1703 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1704 unsigned Opc;
1705 unsigned Size;
1706 switch (MI->getOpcode()) {
1707 default: llvm_unreachable("Unreachable!");
1708 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1709 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1710 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1711 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1712 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1713 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1714 }
1715 unsigned Amt = MI->getOperand(3).getImm();
1716 if (NewMI) {
1717 MachineFunction &MF = *MI->getParent()->getParent();
1718 MI = MF.CloneMachineInstr(MI);
1719 NewMI = false;
1720 }
1721 MI->setDesc(get(Opc));
1722 MI->getOperand(3).setImm(Size-Amt);
1723 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1724 }
1725 case X86::CMOVB16rr:
1726 case X86::CMOVB32rr:
1727 case X86::CMOVB64rr:
1728 case X86::CMOVAE16rr:
1729 case X86::CMOVAE32rr:
1730 case X86::CMOVAE64rr:
1731 case X86::CMOVE16rr:
1732 case X86::CMOVE32rr:
1733 case X86::CMOVE64rr:
1734 case X86::CMOVNE16rr:
1735 case X86::CMOVNE32rr:
1736 case X86::CMOVNE64rr:
1737 case X86::CMOVBE16rr:
1738 case X86::CMOVBE32rr:
1739 case X86::CMOVBE64rr:
1740 case X86::CMOVA16rr:
1741 case X86::CMOVA32rr:
1742 case X86::CMOVA64rr:
1743 case X86::CMOVL16rr:
1744 case X86::CMOVL32rr:
1745 case X86::CMOVL64rr:
1746 case X86::CMOVGE16rr:
1747 case X86::CMOVGE32rr:
1748 case X86::CMOVGE64rr:
1749 case X86::CMOVLE16rr:
1750 case X86::CMOVLE32rr:
1751 case X86::CMOVLE64rr:
1752 case X86::CMOVG16rr:
1753 case X86::CMOVG32rr:
1754 case X86::CMOVG64rr:
1755 case X86::CMOVS16rr:
1756 case X86::CMOVS32rr:
1757 case X86::CMOVS64rr:
1758 case X86::CMOVNS16rr:
1759 case X86::CMOVNS32rr:
1760 case X86::CMOVNS64rr:
1761 case X86::CMOVP16rr:
1762 case X86::CMOVP32rr:
1763 case X86::CMOVP64rr:
1764 case X86::CMOVNP16rr:
1765 case X86::CMOVNP32rr:
1766 case X86::CMOVNP64rr:
1767 case X86::CMOVO16rr:
1768 case X86::CMOVO32rr:
1769 case X86::CMOVO64rr:
1770 case X86::CMOVNO16rr:
1771 case X86::CMOVNO32rr:
1772 case X86::CMOVNO64rr: {
1773 unsigned Opc = 0;
1774 switch (MI->getOpcode()) {
1775 default: break;
1776 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1777 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1778 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1779 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1780 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1781 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1782 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1783 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1784 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1785 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1786 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1787 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1788 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1789 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1790 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1791 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1792 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1793 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1794 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1795 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1796 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1797 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1798 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1799 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1800 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1801 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1802 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1803 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1804 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1805 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1806 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1807 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1808 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1809 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1810 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1811 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1812 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1813 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1814 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1815 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1816 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1817 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1818 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1819 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1820 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1821 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1822 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1823 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1824 }
1825 if (NewMI) {
1826 MachineFunction &MF = *MI->getParent()->getParent();
1827 MI = MF.CloneMachineInstr(MI);
1828 NewMI = false;
1829 }
1830 MI->setDesc(get(Opc));
1831 // Fallthrough intended.
1832 }
1833 default:
1834 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1835 }
1836 }
1837
GetCondFromBranchOpc(unsigned BrOpc)1838 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1839 switch (BrOpc) {
1840 default: return X86::COND_INVALID;
1841 case X86::JE_4: return X86::COND_E;
1842 case X86::JNE_4: return X86::COND_NE;
1843 case X86::JL_4: return X86::COND_L;
1844 case X86::JLE_4: return X86::COND_LE;
1845 case X86::JG_4: return X86::COND_G;
1846 case X86::JGE_4: return X86::COND_GE;
1847 case X86::JB_4: return X86::COND_B;
1848 case X86::JBE_4: return X86::COND_BE;
1849 case X86::JA_4: return X86::COND_A;
1850 case X86::JAE_4: return X86::COND_AE;
1851 case X86::JS_4: return X86::COND_S;
1852 case X86::JNS_4: return X86::COND_NS;
1853 case X86::JP_4: return X86::COND_P;
1854 case X86::JNP_4: return X86::COND_NP;
1855 case X86::JO_4: return X86::COND_O;
1856 case X86::JNO_4: return X86::COND_NO;
1857 }
1858 }
1859
GetCondBranchFromCond(X86::CondCode CC)1860 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1861 switch (CC) {
1862 default: llvm_unreachable("Illegal condition code!");
1863 case X86::COND_E: return X86::JE_4;
1864 case X86::COND_NE: return X86::JNE_4;
1865 case X86::COND_L: return X86::JL_4;
1866 case X86::COND_LE: return X86::JLE_4;
1867 case X86::COND_G: return X86::JG_4;
1868 case X86::COND_GE: return X86::JGE_4;
1869 case X86::COND_B: return X86::JB_4;
1870 case X86::COND_BE: return X86::JBE_4;
1871 case X86::COND_A: return X86::JA_4;
1872 case X86::COND_AE: return X86::JAE_4;
1873 case X86::COND_S: return X86::JS_4;
1874 case X86::COND_NS: return X86::JNS_4;
1875 case X86::COND_P: return X86::JP_4;
1876 case X86::COND_NP: return X86::JNP_4;
1877 case X86::COND_O: return X86::JO_4;
1878 case X86::COND_NO: return X86::JNO_4;
1879 }
1880 }
1881
1882 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1883 /// e.g. turning COND_E to COND_NE.
GetOppositeBranchCondition(X86::CondCode CC)1884 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1885 switch (CC) {
1886 default: llvm_unreachable("Illegal condition code!");
1887 case X86::COND_E: return X86::COND_NE;
1888 case X86::COND_NE: return X86::COND_E;
1889 case X86::COND_L: return X86::COND_GE;
1890 case X86::COND_LE: return X86::COND_G;
1891 case X86::COND_G: return X86::COND_LE;
1892 case X86::COND_GE: return X86::COND_L;
1893 case X86::COND_B: return X86::COND_AE;
1894 case X86::COND_BE: return X86::COND_A;
1895 case X86::COND_A: return X86::COND_BE;
1896 case X86::COND_AE: return X86::COND_B;
1897 case X86::COND_S: return X86::COND_NS;
1898 case X86::COND_NS: return X86::COND_S;
1899 case X86::COND_P: return X86::COND_NP;
1900 case X86::COND_NP: return X86::COND_P;
1901 case X86::COND_O: return X86::COND_NO;
1902 case X86::COND_NO: return X86::COND_O;
1903 }
1904 }
1905
isUnpredicatedTerminator(const MachineInstr * MI) const1906 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1907 const MCInstrDesc &MCID = MI->getDesc();
1908 if (!MCID.isTerminator()) return false;
1909
1910 // Conditional branch is a special case.
1911 if (MCID.isBranch() && !MCID.isBarrier())
1912 return true;
1913 if (!MCID.isPredicable())
1914 return true;
1915 return !isPredicated(MI);
1916 }
1917
AnalyzeBranch(MachineBasicBlock & MBB,MachineBasicBlock * & TBB,MachineBasicBlock * & FBB,SmallVectorImpl<MachineOperand> & Cond,bool AllowModify) const1918 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1919 MachineBasicBlock *&TBB,
1920 MachineBasicBlock *&FBB,
1921 SmallVectorImpl<MachineOperand> &Cond,
1922 bool AllowModify) const {
1923 // Start from the bottom of the block and work up, examining the
1924 // terminator instructions.
1925 MachineBasicBlock::iterator I = MBB.end();
1926 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
1927 while (I != MBB.begin()) {
1928 --I;
1929 if (I->isDebugValue())
1930 continue;
1931
1932 // Working from the bottom, when we see a non-terminator instruction, we're
1933 // done.
1934 if (!isUnpredicatedTerminator(I))
1935 break;
1936
1937 // A terminator that isn't a branch can't easily be handled by this
1938 // analysis.
1939 if (!I->getDesc().isBranch())
1940 return true;
1941
1942 // Handle unconditional branches.
1943 if (I->getOpcode() == X86::JMP_4) {
1944 UnCondBrIter = I;
1945
1946 if (!AllowModify) {
1947 TBB = I->getOperand(0).getMBB();
1948 continue;
1949 }
1950
1951 // If the block has any instructions after a JMP, delete them.
1952 while (llvm::next(I) != MBB.end())
1953 llvm::next(I)->eraseFromParent();
1954
1955 Cond.clear();
1956 FBB = 0;
1957
1958 // Delete the JMP if it's equivalent to a fall-through.
1959 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1960 TBB = 0;
1961 I->eraseFromParent();
1962 I = MBB.end();
1963 UnCondBrIter = MBB.end();
1964 continue;
1965 }
1966
1967 // TBB is used to indicate the unconditional destination.
1968 TBB = I->getOperand(0).getMBB();
1969 continue;
1970 }
1971
1972 // Handle conditional branches.
1973 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1974 if (BranchCode == X86::COND_INVALID)
1975 return true; // Can't handle indirect branch.
1976
1977 // Working from the bottom, handle the first conditional branch.
1978 if (Cond.empty()) {
1979 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
1980 if (AllowModify && UnCondBrIter != MBB.end() &&
1981 MBB.isLayoutSuccessor(TargetBB)) {
1982 // If we can modify the code and it ends in something like:
1983 //
1984 // jCC L1
1985 // jmp L2
1986 // L1:
1987 // ...
1988 // L2:
1989 //
1990 // Then we can change this to:
1991 //
1992 // jnCC L2
1993 // L1:
1994 // ...
1995 // L2:
1996 //
1997 // Which is a bit more efficient.
1998 // We conditionally jump to the fall-through block.
1999 BranchCode = GetOppositeBranchCondition(BranchCode);
2000 unsigned JNCC = GetCondBranchFromCond(BranchCode);
2001 MachineBasicBlock::iterator OldInst = I;
2002
2003 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2004 .addMBB(UnCondBrIter->getOperand(0).getMBB());
2005 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2006 .addMBB(TargetBB);
2007
2008 OldInst->eraseFromParent();
2009 UnCondBrIter->eraseFromParent();
2010
2011 // Restart the analysis.
2012 UnCondBrIter = MBB.end();
2013 I = MBB.end();
2014 continue;
2015 }
2016
2017 FBB = TBB;
2018 TBB = I->getOperand(0).getMBB();
2019 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2020 continue;
2021 }
2022
2023 // Handle subsequent conditional branches. Only handle the case where all
2024 // conditional branches branch to the same destination and their condition
2025 // opcodes fit one of the special multi-branch idioms.
2026 assert(Cond.size() == 1);
2027 assert(TBB);
2028
2029 // Only handle the case where all conditional branches branch to the same
2030 // destination.
2031 if (TBB != I->getOperand(0).getMBB())
2032 return true;
2033
2034 // If the conditions are the same, we can leave them alone.
2035 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2036 if (OldBranchCode == BranchCode)
2037 continue;
2038
2039 // If they differ, see if they fit one of the known patterns. Theoretically,
2040 // we could handle more patterns here, but we shouldn't expect to see them
2041 // if instruction selection has done a reasonable job.
2042 if ((OldBranchCode == X86::COND_NP &&
2043 BranchCode == X86::COND_E) ||
2044 (OldBranchCode == X86::COND_E &&
2045 BranchCode == X86::COND_NP))
2046 BranchCode = X86::COND_NP_OR_E;
2047 else if ((OldBranchCode == X86::COND_P &&
2048 BranchCode == X86::COND_NE) ||
2049 (OldBranchCode == X86::COND_NE &&
2050 BranchCode == X86::COND_P))
2051 BranchCode = X86::COND_NE_OR_P;
2052 else
2053 return true;
2054
2055 // Update the MachineOperand.
2056 Cond[0].setImm(BranchCode);
2057 }
2058
2059 return false;
2060 }
2061
RemoveBranch(MachineBasicBlock & MBB) const2062 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
2063 MachineBasicBlock::iterator I = MBB.end();
2064 unsigned Count = 0;
2065
2066 while (I != MBB.begin()) {
2067 --I;
2068 if (I->isDebugValue())
2069 continue;
2070 if (I->getOpcode() != X86::JMP_4 &&
2071 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2072 break;
2073 // Remove the branch.
2074 I->eraseFromParent();
2075 I = MBB.end();
2076 ++Count;
2077 }
2078
2079 return Count;
2080 }
2081
2082 unsigned
InsertBranch(MachineBasicBlock & MBB,MachineBasicBlock * TBB,MachineBasicBlock * FBB,const SmallVectorImpl<MachineOperand> & Cond,DebugLoc DL) const2083 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2084 MachineBasicBlock *FBB,
2085 const SmallVectorImpl<MachineOperand> &Cond,
2086 DebugLoc DL) const {
2087 // Shouldn't be a fall through.
2088 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
2089 assert((Cond.size() == 1 || Cond.size() == 0) &&
2090 "X86 branch conditions have one component!");
2091
2092 if (Cond.empty()) {
2093 // Unconditional branch?
2094 assert(!FBB && "Unconditional branch with multiple successors!");
2095 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2096 return 1;
2097 }
2098
2099 // Conditional branch.
2100 unsigned Count = 0;
2101 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2102 switch (CC) {
2103 case X86::COND_NP_OR_E:
2104 // Synthesize NP_OR_E with two branches.
2105 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2106 ++Count;
2107 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2108 ++Count;
2109 break;
2110 case X86::COND_NE_OR_P:
2111 // Synthesize NE_OR_P with two branches.
2112 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2113 ++Count;
2114 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2115 ++Count;
2116 break;
2117 default: {
2118 unsigned Opc = GetCondBranchFromCond(CC);
2119 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2120 ++Count;
2121 }
2122 }
2123 if (FBB) {
2124 // Two-way Conditional branch. Insert the second branch.
2125 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2126 ++Count;
2127 }
2128 return Count;
2129 }
2130
2131 /// isHReg - Test if the given register is a physical h register.
isHReg(unsigned Reg)2132 static bool isHReg(unsigned Reg) {
2133 return X86::GR8_ABCD_HRegClass.contains(Reg);
2134 }
2135
2136 // Try and copy between VR128/VR64 and GR64 registers.
CopyToFromAsymmetricReg(unsigned DestReg,unsigned SrcReg,bool HasAVX)2137 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2138 bool HasAVX) {
2139 // SrcReg(VR128) -> DestReg(GR64)
2140 // SrcReg(VR64) -> DestReg(GR64)
2141 // SrcReg(GR64) -> DestReg(VR128)
2142 // SrcReg(GR64) -> DestReg(VR64)
2143
2144 if (X86::GR64RegClass.contains(DestReg)) {
2145 if (X86::VR128RegClass.contains(SrcReg)) {
2146 // Copy from a VR128 register to a GR64 register.
2147 return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr;
2148 } else if (X86::VR64RegClass.contains(SrcReg)) {
2149 // Copy from a VR64 register to a GR64 register.
2150 return X86::MOVSDto64rr;
2151 }
2152 } else if (X86::GR64RegClass.contains(SrcReg)) {
2153 // Copy from a GR64 register to a VR128 register.
2154 if (X86::VR128RegClass.contains(DestReg))
2155 return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr;
2156 // Copy from a GR64 register to a VR64 register.
2157 else if (X86::VR64RegClass.contains(DestReg))
2158 return X86::MOV64toSDrr;
2159 }
2160
2161 // SrcReg(FR32) -> DestReg(GR32)
2162 // SrcReg(GR32) -> DestReg(FR32)
2163
2164 if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg))
2165 // Copy from a FR32 register to a GR32 register.
2166 return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr;
2167
2168 if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
2169 // Copy from a GR32 register to a FR32 register.
2170 return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr;
2171
2172 return 0;
2173 }
2174
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,DebugLoc DL,unsigned DestReg,unsigned SrcReg,bool KillSrc) const2175 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2176 MachineBasicBlock::iterator MI, DebugLoc DL,
2177 unsigned DestReg, unsigned SrcReg,
2178 bool KillSrc) const {
2179 // First deal with the normal symmetric copies.
2180 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2181 unsigned Opc = 0;
2182 if (X86::GR64RegClass.contains(DestReg, SrcReg))
2183 Opc = X86::MOV64rr;
2184 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2185 Opc = X86::MOV32rr;
2186 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2187 Opc = X86::MOV16rr;
2188 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2189 // Copying to or from a physical H register on x86-64 requires a NOREX
2190 // move. Otherwise use a normal move.
2191 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2192 TM.getSubtarget<X86Subtarget>().is64Bit()) {
2193 Opc = X86::MOV8rr_NOREX;
2194 // Both operands must be encodable without an REX prefix.
2195 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2196 "8-bit H register can not be copied outside GR8_NOREX");
2197 } else
2198 Opc = X86::MOV8rr;
2199 } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2200 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2201 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
2202 Opc = X86::VMOVAPSYrr;
2203 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2204 Opc = X86::MMX_MOVQ64rr;
2205 else
2206 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX);
2207
2208 if (Opc) {
2209 BuildMI(MBB, MI, DL, get(Opc), DestReg)
2210 .addReg(SrcReg, getKillRegState(KillSrc));
2211 return;
2212 }
2213
2214 // Moving EFLAGS to / from another register requires a push and a pop.
2215 if (SrcReg == X86::EFLAGS) {
2216 if (X86::GR64RegClass.contains(DestReg)) {
2217 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
2218 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
2219 return;
2220 } else if (X86::GR32RegClass.contains(DestReg)) {
2221 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
2222 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
2223 return;
2224 }
2225 }
2226 if (DestReg == X86::EFLAGS) {
2227 if (X86::GR64RegClass.contains(SrcReg)) {
2228 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
2229 .addReg(SrcReg, getKillRegState(KillSrc));
2230 BuildMI(MBB, MI, DL, get(X86::POPF64));
2231 return;
2232 } else if (X86::GR32RegClass.contains(SrcReg)) {
2233 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
2234 .addReg(SrcReg, getKillRegState(KillSrc));
2235 BuildMI(MBB, MI, DL, get(X86::POPF32));
2236 return;
2237 }
2238 }
2239
2240 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
2241 << " to " << RI.getName(DestReg) << '\n');
2242 llvm_unreachable("Cannot emit physreg copy instruction");
2243 }
2244
getLoadStoreRegOpcode(unsigned Reg,const TargetRegisterClass * RC,bool isStackAligned,const TargetMachine & TM,bool load)2245 static unsigned getLoadStoreRegOpcode(unsigned Reg,
2246 const TargetRegisterClass *RC,
2247 bool isStackAligned,
2248 const TargetMachine &TM,
2249 bool load) {
2250 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2251 switch (RC->getSize()) {
2252 default:
2253 llvm_unreachable("Unknown spill size");
2254 case 1:
2255 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
2256 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2257 // Copying to or from a physical H register on x86-64 requires a NOREX
2258 // move. Otherwise use a normal move.
2259 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2260 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2261 return load ? X86::MOV8rm : X86::MOV8mr;
2262 case 2:
2263 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2264 return load ? X86::MOV16rm : X86::MOV16mr;
2265 case 4:
2266 if (X86::GR32RegClass.hasSubClassEq(RC))
2267 return load ? X86::MOV32rm : X86::MOV32mr;
2268 if (X86::FR32RegClass.hasSubClassEq(RC))
2269 return load ?
2270 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
2271 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
2272 if (X86::RFP32RegClass.hasSubClassEq(RC))
2273 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2274 llvm_unreachable("Unknown 4-byte regclass");
2275 case 8:
2276 if (X86::GR64RegClass.hasSubClassEq(RC))
2277 return load ? X86::MOV64rm : X86::MOV64mr;
2278 if (X86::FR64RegClass.hasSubClassEq(RC))
2279 return load ?
2280 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
2281 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
2282 if (X86::VR64RegClass.hasSubClassEq(RC))
2283 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2284 if (X86::RFP64RegClass.hasSubClassEq(RC))
2285 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2286 llvm_unreachable("Unknown 8-byte regclass");
2287 case 10:
2288 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
2289 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
2290 case 16: {
2291 assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
2292 // If stack is realigned we can use aligned stores.
2293 if (isStackAligned)
2294 return load ?
2295 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
2296 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
2297 else
2298 return load ?
2299 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
2300 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
2301 }
2302 case 32:
2303 assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
2304 // If stack is realigned we can use aligned stores.
2305 if (isStackAligned)
2306 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
2307 else
2308 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
2309 }
2310 }
2311
getStoreRegOpcode(unsigned SrcReg,const TargetRegisterClass * RC,bool isStackAligned,TargetMachine & TM)2312 static unsigned getStoreRegOpcode(unsigned SrcReg,
2313 const TargetRegisterClass *RC,
2314 bool isStackAligned,
2315 TargetMachine &TM) {
2316 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2317 }
2318
2319
getLoadRegOpcode(unsigned DestReg,const TargetRegisterClass * RC,bool isStackAligned,const TargetMachine & TM)2320 static unsigned getLoadRegOpcode(unsigned DestReg,
2321 const TargetRegisterClass *RC,
2322 bool isStackAligned,
2323 const TargetMachine &TM) {
2324 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
2325 }
2326
storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned SrcReg,bool isKill,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const2327 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2328 MachineBasicBlock::iterator MI,
2329 unsigned SrcReg, bool isKill, int FrameIdx,
2330 const TargetRegisterClass *RC,
2331 const TargetRegisterInfo *TRI) const {
2332 const MachineFunction &MF = *MBB.getParent();
2333 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
2334 "Stack slot too small for store");
2335 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2336 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
2337 RI.canRealignStack(MF);
2338 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2339 DebugLoc DL = MBB.findDebugLoc(MI);
2340 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2341 .addReg(SrcReg, getKillRegState(isKill));
2342 }
2343
storeRegToAddr(MachineFunction & MF,unsigned SrcReg,bool isKill,SmallVectorImpl<MachineOperand> & Addr,const TargetRegisterClass * RC,MachineInstr::mmo_iterator MMOBegin,MachineInstr::mmo_iterator MMOEnd,SmallVectorImpl<MachineInstr * > & NewMIs) const2344 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2345 bool isKill,
2346 SmallVectorImpl<MachineOperand> &Addr,
2347 const TargetRegisterClass *RC,
2348 MachineInstr::mmo_iterator MMOBegin,
2349 MachineInstr::mmo_iterator MMOEnd,
2350 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2351 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2352 bool isAligned = MMOBegin != MMOEnd &&
2353 (*MMOBegin)->getAlignment() >= Alignment;
2354 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2355 DebugLoc DL;
2356 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2357 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2358 MIB.addOperand(Addr[i]);
2359 MIB.addReg(SrcReg, getKillRegState(isKill));
2360 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2361 NewMIs.push_back(MIB);
2362 }
2363
2364
loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned DestReg,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const2365 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2366 MachineBasicBlock::iterator MI,
2367 unsigned DestReg, int FrameIdx,
2368 const TargetRegisterClass *RC,
2369 const TargetRegisterInfo *TRI) const {
2370 const MachineFunction &MF = *MBB.getParent();
2371 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2372 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
2373 RI.canRealignStack(MF);
2374 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2375 DebugLoc DL = MBB.findDebugLoc(MI);
2376 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2377 }
2378
loadRegFromAddr(MachineFunction & MF,unsigned DestReg,SmallVectorImpl<MachineOperand> & Addr,const TargetRegisterClass * RC,MachineInstr::mmo_iterator MMOBegin,MachineInstr::mmo_iterator MMOEnd,SmallVectorImpl<MachineInstr * > & NewMIs) const2379 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2380 SmallVectorImpl<MachineOperand> &Addr,
2381 const TargetRegisterClass *RC,
2382 MachineInstr::mmo_iterator MMOBegin,
2383 MachineInstr::mmo_iterator MMOEnd,
2384 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2385 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2386 bool isAligned = MMOBegin != MMOEnd &&
2387 (*MMOBegin)->getAlignment() >= Alignment;
2388 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2389 DebugLoc DL;
2390 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2391 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2392 MIB.addOperand(Addr[i]);
2393 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2394 NewMIs.push_back(MIB);
2395 }
2396
2397 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
2398 /// instruction with two undef reads of the register being defined. This is
2399 /// used for mapping:
2400 /// %xmm4 = V_SET0
2401 /// to:
2402 /// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
2403 ///
Expand2AddrUndef(MachineInstr * MI,const MCInstrDesc & Desc)2404 static bool Expand2AddrUndef(MachineInstr *MI, const MCInstrDesc &Desc) {
2405 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
2406 unsigned Reg = MI->getOperand(0).getReg();
2407 MI->setDesc(Desc);
2408
2409 // MachineInstr::addOperand() will insert explicit operands before any
2410 // implicit operands.
2411 MachineInstrBuilder(MI).addReg(Reg, RegState::Undef)
2412 .addReg(Reg, RegState::Undef);
2413 // But we don't trust that.
2414 assert(MI->getOperand(1).getReg() == Reg &&
2415 MI->getOperand(2).getReg() == Reg && "Misplaced operand");
2416 return true;
2417 }
2418
expandPostRAPseudo(MachineBasicBlock::iterator MI) const2419 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
2420 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2421 switch (MI->getOpcode()) {
2422 case X86::V_SET0:
2423 case X86::FsFLD0SS:
2424 case X86::FsFLD0SD:
2425 return Expand2AddrUndef(MI, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
2426 case X86::TEST8ri_NOREX:
2427 MI->setDesc(get(X86::TEST8ri));
2428 return true;
2429 }
2430 return false;
2431 }
2432
2433 MachineInstr*
emitFrameIndexDebugValue(MachineFunction & MF,int FrameIx,uint64_t Offset,const MDNode * MDPtr,DebugLoc DL) const2434 X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
2435 int FrameIx, uint64_t Offset,
2436 const MDNode *MDPtr,
2437 DebugLoc DL) const {
2438 X86AddressMode AM;
2439 AM.BaseType = X86AddressMode::FrameIndexBase;
2440 AM.Base.FrameIndex = FrameIx;
2441 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
2442 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
2443 return &*MIB;
2444 }
2445
FuseTwoAddrInst(MachineFunction & MF,unsigned Opcode,const SmallVectorImpl<MachineOperand> & MOs,MachineInstr * MI,const TargetInstrInfo & TII)2446 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2447 const SmallVectorImpl<MachineOperand> &MOs,
2448 MachineInstr *MI,
2449 const TargetInstrInfo &TII) {
2450 // Create the base instruction with the memory operand as the first part.
2451 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2452 MI->getDebugLoc(), true);
2453 MachineInstrBuilder MIB(NewMI);
2454 unsigned NumAddrOps = MOs.size();
2455 for (unsigned i = 0; i != NumAddrOps; ++i)
2456 MIB.addOperand(MOs[i]);
2457 if (NumAddrOps < 4) // FrameIndex only
2458 addOffset(MIB, 0);
2459
2460 // Loop over the rest of the ri operands, converting them over.
2461 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2462 for (unsigned i = 0; i != NumOps; ++i) {
2463 MachineOperand &MO = MI->getOperand(i+2);
2464 MIB.addOperand(MO);
2465 }
2466 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2467 MachineOperand &MO = MI->getOperand(i);
2468 MIB.addOperand(MO);
2469 }
2470 return MIB;
2471 }
2472
FuseInst(MachineFunction & MF,unsigned Opcode,unsigned OpNo,const SmallVectorImpl<MachineOperand> & MOs,MachineInstr * MI,const TargetInstrInfo & TII)2473 static MachineInstr *FuseInst(MachineFunction &MF,
2474 unsigned Opcode, unsigned OpNo,
2475 const SmallVectorImpl<MachineOperand> &MOs,
2476 MachineInstr *MI, const TargetInstrInfo &TII) {
2477 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2478 MI->getDebugLoc(), true);
2479 MachineInstrBuilder MIB(NewMI);
2480
2481 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2482 MachineOperand &MO = MI->getOperand(i);
2483 if (i == OpNo) {
2484 assert(MO.isReg() && "Expected to fold into reg operand!");
2485 unsigned NumAddrOps = MOs.size();
2486 for (unsigned i = 0; i != NumAddrOps; ++i)
2487 MIB.addOperand(MOs[i]);
2488 if (NumAddrOps < 4) // FrameIndex only
2489 addOffset(MIB, 0);
2490 } else {
2491 MIB.addOperand(MO);
2492 }
2493 }
2494 return MIB;
2495 }
2496
MakeM0Inst(const TargetInstrInfo & TII,unsigned Opcode,const SmallVectorImpl<MachineOperand> & MOs,MachineInstr * MI)2497 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2498 const SmallVectorImpl<MachineOperand> &MOs,
2499 MachineInstr *MI) {
2500 MachineFunction &MF = *MI->getParent()->getParent();
2501 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2502
2503 unsigned NumAddrOps = MOs.size();
2504 for (unsigned i = 0; i != NumAddrOps; ++i)
2505 MIB.addOperand(MOs[i]);
2506 if (NumAddrOps < 4) // FrameIndex only
2507 addOffset(MIB, 0);
2508 return MIB.addImm(0);
2509 }
2510
2511 MachineInstr*
foldMemoryOperandImpl(MachineFunction & MF,MachineInstr * MI,unsigned i,const SmallVectorImpl<MachineOperand> & MOs,unsigned Size,unsigned Align) const2512 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2513 MachineInstr *MI, unsigned i,
2514 const SmallVectorImpl<MachineOperand> &MOs,
2515 unsigned Size, unsigned Align) const {
2516 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
2517 bool isTwoAddrFold = false;
2518 unsigned NumOps = MI->getDesc().getNumOperands();
2519 bool isTwoAddr = NumOps > 1 &&
2520 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
2521
2522 // FIXME: AsmPrinter doesn't know how to handle
2523 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
2524 if (MI->getOpcode() == X86::ADD32ri &&
2525 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
2526 return NULL;
2527
2528 MachineInstr *NewMI = NULL;
2529 // Folding a memory location into the two-address part of a two-address
2530 // instruction is different than folding it other places. It requires
2531 // replacing the *two* registers with the memory location.
2532 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2533 MI->getOperand(0).isReg() &&
2534 MI->getOperand(1).isReg() &&
2535 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2536 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2537 isTwoAddrFold = true;
2538 } else if (i == 0) { // If operand 0
2539 if (MI->getOpcode() == X86::MOV64r0)
2540 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2541 else if (MI->getOpcode() == X86::MOV32r0)
2542 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2543 else if (MI->getOpcode() == X86::MOV16r0)
2544 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2545 else if (MI->getOpcode() == X86::MOV8r0)
2546 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2547 if (NewMI)
2548 return NewMI;
2549
2550 OpcodeTablePtr = &RegOp2MemOpTable0;
2551 } else if (i == 1) {
2552 OpcodeTablePtr = &RegOp2MemOpTable1;
2553 } else if (i == 2) {
2554 OpcodeTablePtr = &RegOp2MemOpTable2;
2555 }
2556
2557 // If table selected...
2558 if (OpcodeTablePtr) {
2559 // Find the Opcode to fuse
2560 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2561 OpcodeTablePtr->find(MI->getOpcode());
2562 if (I != OpcodeTablePtr->end()) {
2563 unsigned Opcode = I->second.first;
2564 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
2565 if (Align < MinAlign)
2566 return NULL;
2567 bool NarrowToMOV32rm = false;
2568 if (Size) {
2569 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI)->getSize();
2570 if (Size < RCSize) {
2571 // Check if it's safe to fold the load. If the size of the object is
2572 // narrower than the load width, then it's not.
2573 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2574 return NULL;
2575 // If this is a 64-bit load, but the spill slot is 32, then we can do
2576 // a 32-bit load which is implicitly zero-extended. This likely is due
2577 // to liveintervalanalysis remat'ing a load from stack slot.
2578 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2579 return NULL;
2580 Opcode = X86::MOV32rm;
2581 NarrowToMOV32rm = true;
2582 }
2583 }
2584
2585 if (isTwoAddrFold)
2586 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2587 else
2588 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2589
2590 if (NarrowToMOV32rm) {
2591 // If this is the special case where we use a MOV32rm to load a 32-bit
2592 // value and zero-extend the top bits. Change the destination register
2593 // to a 32-bit one.
2594 unsigned DstReg = NewMI->getOperand(0).getReg();
2595 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2596 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2597 X86::sub_32bit));
2598 else
2599 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
2600 }
2601 return NewMI;
2602 }
2603 }
2604
2605 // No fusion
2606 if (PrintFailedFusing && !MI->isCopy())
2607 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2608 return NULL;
2609 }
2610
2611 /// hasPartialRegUpdate - Return true for all instructions that only update
2612 /// the first 32 or 64-bits of the destination register and leave the rest
2613 /// unmodified. This can be used to avoid folding loads if the instructions
2614 /// only update part of the destination register, and the non-updated part is
2615 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
2616 /// instructions breaks the partial register dependency and it can improve
2617 /// performance. e.g.:
2618 ///
2619 /// movss (%rdi), %xmm0
2620 /// cvtss2sd %xmm0, %xmm0
2621 ///
2622 /// Instead of
2623 /// cvtss2sd (%rdi), %xmm0
2624 ///
2625 /// FIXME: This should be turned into a TSFlags.
2626 ///
hasPartialRegUpdate(unsigned Opcode)2627 static bool hasPartialRegUpdate(unsigned Opcode) {
2628 switch (Opcode) {
2629 case X86::CVTSD2SSrr:
2630 case X86::Int_CVTSD2SSrr:
2631 case X86::CVTSS2SDrr:
2632 case X86::Int_CVTSS2SDrr:
2633 case X86::RCPSSr:
2634 case X86::RCPSSr_Int:
2635 case X86::ROUNDSDr:
2636 case X86::ROUNDSSr:
2637 case X86::RSQRTSSr:
2638 case X86::RSQRTSSr_Int:
2639 case X86::SQRTSSr:
2640 case X86::SQRTSSr_Int:
2641 // AVX encoded versions
2642 case X86::VCVTSD2SSrr:
2643 case X86::Int_VCVTSD2SSrr:
2644 case X86::VCVTSS2SDrr:
2645 case X86::Int_VCVTSS2SDrr:
2646 case X86::VRCPSSr:
2647 case X86::VROUNDSDr:
2648 case X86::VROUNDSSr:
2649 case X86::VRSQRTSSr:
2650 case X86::VSQRTSSr:
2651 return true;
2652 }
2653
2654 return false;
2655 }
2656
foldMemoryOperandImpl(MachineFunction & MF,MachineInstr * MI,const SmallVectorImpl<unsigned> & Ops,int FrameIndex) const2657 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2658 MachineInstr *MI,
2659 const SmallVectorImpl<unsigned> &Ops,
2660 int FrameIndex) const {
2661 // Check switch flag
2662 if (NoFusing) return NULL;
2663
2664 // Unless optimizing for size, don't fold to avoid partial
2665 // register update stalls
2666 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
2667 hasPartialRegUpdate(MI->getOpcode()))
2668 return 0;
2669
2670 const MachineFrameInfo *MFI = MF.getFrameInfo();
2671 unsigned Size = MFI->getObjectSize(FrameIndex);
2672 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2673 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2674 unsigned NewOpc = 0;
2675 unsigned RCSize = 0;
2676 switch (MI->getOpcode()) {
2677 default: return NULL;
2678 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2679 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
2680 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
2681 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
2682 }
2683 // Check if it's safe to fold the load. If the size of the object is
2684 // narrower than the load width, then it's not.
2685 if (Size < RCSize)
2686 return NULL;
2687 // Change to CMPXXri r, 0 first.
2688 MI->setDesc(get(NewOpc));
2689 MI->getOperand(1).ChangeToImmediate(0);
2690 } else if (Ops.size() != 1)
2691 return NULL;
2692
2693 SmallVector<MachineOperand,4> MOs;
2694 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2695 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2696 }
2697
foldMemoryOperandImpl(MachineFunction & MF,MachineInstr * MI,const SmallVectorImpl<unsigned> & Ops,MachineInstr * LoadMI) const2698 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2699 MachineInstr *MI,
2700 const SmallVectorImpl<unsigned> &Ops,
2701 MachineInstr *LoadMI) const {
2702 // Check switch flag
2703 if (NoFusing) return NULL;
2704
2705 // Unless optimizing for size, don't fold to avoid partial
2706 // register update stalls
2707 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
2708 hasPartialRegUpdate(MI->getOpcode()))
2709 return 0;
2710
2711 // Determine the alignment of the load.
2712 unsigned Alignment = 0;
2713 if (LoadMI->hasOneMemOperand())
2714 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2715 else
2716 switch (LoadMI->getOpcode()) {
2717 case X86::AVX_SET0PSY:
2718 case X86::AVX_SET0PDY:
2719 Alignment = 32;
2720 break;
2721 case X86::V_SET0:
2722 case X86::V_SETALLONES:
2723 case X86::AVX_SETALLONES:
2724 Alignment = 16;
2725 break;
2726 case X86::FsFLD0SD:
2727 Alignment = 8;
2728 break;
2729 case X86::FsFLD0SS:
2730 Alignment = 4;
2731 break;
2732 default:
2733 return 0;
2734 }
2735 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2736 unsigned NewOpc = 0;
2737 switch (MI->getOpcode()) {
2738 default: return NULL;
2739 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2740 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
2741 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
2742 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
2743 }
2744 // Change to CMPXXri r, 0 first.
2745 MI->setDesc(get(NewOpc));
2746 MI->getOperand(1).ChangeToImmediate(0);
2747 } else if (Ops.size() != 1)
2748 return NULL;
2749
2750 // Make sure the subregisters match.
2751 // Otherwise we risk changing the size of the load.
2752 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
2753 return NULL;
2754
2755 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
2756 switch (LoadMI->getOpcode()) {
2757 case X86::V_SET0:
2758 case X86::V_SETALLONES:
2759 case X86::AVX_SET0PSY:
2760 case X86::AVX_SET0PDY:
2761 case X86::AVX_SETALLONES:
2762 case X86::FsFLD0SD:
2763 case X86::FsFLD0SS: {
2764 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2765 // Create a constant-pool entry and operands to load from it.
2766
2767 // Medium and large mode can't fold loads this way.
2768 if (TM.getCodeModel() != CodeModel::Small &&
2769 TM.getCodeModel() != CodeModel::Kernel)
2770 return NULL;
2771
2772 // x86-32 PIC requires a PIC base register for constant pools.
2773 unsigned PICBase = 0;
2774 if (TM.getRelocationModel() == Reloc::PIC_) {
2775 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2776 PICBase = X86::RIP;
2777 else
2778 // FIXME: PICBase = getGlobalBaseReg(&MF);
2779 // This doesn't work for several reasons.
2780 // 1. GlobalBaseReg may have been spilled.
2781 // 2. It may not be live at MI.
2782 return NULL;
2783 }
2784
2785 // Create a constant-pool entry.
2786 MachineConstantPool &MCP = *MF.getConstantPool();
2787 Type *Ty;
2788 unsigned Opc = LoadMI->getOpcode();
2789 if (Opc == X86::FsFLD0SS)
2790 Ty = Type::getFloatTy(MF.getFunction()->getContext());
2791 else if (Opc == X86::FsFLD0SD)
2792 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2793 else if (Opc == X86::AVX_SET0PSY || Opc == X86::AVX_SET0PDY)
2794 Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8);
2795 else
2796 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2797
2798 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX_SETALLONES);
2799 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
2800 Constant::getNullValue(Ty);
2801 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2802
2803 // Create operands to load from the constant pool entry.
2804 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2805 MOs.push_back(MachineOperand::CreateImm(1));
2806 MOs.push_back(MachineOperand::CreateReg(0, false));
2807 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2808 MOs.push_back(MachineOperand::CreateReg(0, false));
2809 break;
2810 }
2811 default: {
2812 // Folding a normal load. Just copy the load's address operands.
2813 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2814 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
2815 MOs.push_back(LoadMI->getOperand(i));
2816 break;
2817 }
2818 }
2819 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2820 }
2821
2822
canFoldMemoryOperand(const MachineInstr * MI,const SmallVectorImpl<unsigned> & Ops) const2823 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2824 const SmallVectorImpl<unsigned> &Ops) const {
2825 // Check switch flag
2826 if (NoFusing) return 0;
2827
2828 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2829 switch (MI->getOpcode()) {
2830 default: return false;
2831 case X86::TEST8rr:
2832 case X86::TEST16rr:
2833 case X86::TEST32rr:
2834 case X86::TEST64rr:
2835 return true;
2836 case X86::ADD32ri:
2837 // FIXME: AsmPrinter doesn't know how to handle
2838 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
2839 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
2840 return false;
2841 break;
2842 }
2843 }
2844
2845 if (Ops.size() != 1)
2846 return false;
2847
2848 unsigned OpNum = Ops[0];
2849 unsigned Opc = MI->getOpcode();
2850 unsigned NumOps = MI->getDesc().getNumOperands();
2851 bool isTwoAddr = NumOps > 1 &&
2852 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
2853
2854 // Folding a memory location into the two-address part of a two-address
2855 // instruction is different than folding it other places. It requires
2856 // replacing the *two* registers with the memory location.
2857 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
2858 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2859 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2860 } else if (OpNum == 0) { // If operand 0
2861 switch (Opc) {
2862 case X86::MOV8r0:
2863 case X86::MOV16r0:
2864 case X86::MOV32r0:
2865 case X86::MOV64r0: return true;
2866 default: break;
2867 }
2868 OpcodeTablePtr = &RegOp2MemOpTable0;
2869 } else if (OpNum == 1) {
2870 OpcodeTablePtr = &RegOp2MemOpTable1;
2871 } else if (OpNum == 2) {
2872 OpcodeTablePtr = &RegOp2MemOpTable2;
2873 }
2874
2875 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
2876 return true;
2877 return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops);
2878 }
2879
unfoldMemoryOperand(MachineFunction & MF,MachineInstr * MI,unsigned Reg,bool UnfoldLoad,bool UnfoldStore,SmallVectorImpl<MachineInstr * > & NewMIs) const2880 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2881 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2882 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2883 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2884 MemOp2RegOpTable.find(MI->getOpcode());
2885 if (I == MemOp2RegOpTable.end())
2886 return false;
2887 unsigned Opc = I->second.first;
2888 unsigned Index = I->second.second & TB_INDEX_MASK;
2889 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
2890 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
2891 if (UnfoldLoad && !FoldedLoad)
2892 return false;
2893 UnfoldLoad &= FoldedLoad;
2894 if (UnfoldStore && !FoldedStore)
2895 return false;
2896 UnfoldStore &= FoldedStore;
2897
2898 const MCInstrDesc &MCID = get(Opc);
2899 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
2900 if (!MI->hasOneMemOperand() &&
2901 RC == &X86::VR128RegClass &&
2902 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2903 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
2904 // conservatively assume the address is unaligned. That's bad for
2905 // performance.
2906 return false;
2907 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
2908 SmallVector<MachineOperand,2> BeforeOps;
2909 SmallVector<MachineOperand,2> AfterOps;
2910 SmallVector<MachineOperand,4> ImpOps;
2911 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2912 MachineOperand &Op = MI->getOperand(i);
2913 if (i >= Index && i < Index + X86::AddrNumOperands)
2914 AddrOps.push_back(Op);
2915 else if (Op.isReg() && Op.isImplicit())
2916 ImpOps.push_back(Op);
2917 else if (i < Index)
2918 BeforeOps.push_back(Op);
2919 else if (i > Index)
2920 AfterOps.push_back(Op);
2921 }
2922
2923 // Emit the load instruction.
2924 if (UnfoldLoad) {
2925 std::pair<MachineInstr::mmo_iterator,
2926 MachineInstr::mmo_iterator> MMOs =
2927 MF.extractLoadMemRefs(MI->memoperands_begin(),
2928 MI->memoperands_end());
2929 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2930 if (UnfoldStore) {
2931 // Address operands cannot be marked isKill.
2932 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
2933 MachineOperand &MO = NewMIs[0]->getOperand(i);
2934 if (MO.isReg())
2935 MO.setIsKill(false);
2936 }
2937 }
2938 }
2939
2940 // Emit the data processing instruction.
2941 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
2942 MachineInstrBuilder MIB(DataMI);
2943
2944 if (FoldedStore)
2945 MIB.addReg(Reg, RegState::Define);
2946 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2947 MIB.addOperand(BeforeOps[i]);
2948 if (FoldedLoad)
2949 MIB.addReg(Reg);
2950 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2951 MIB.addOperand(AfterOps[i]);
2952 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2953 MachineOperand &MO = ImpOps[i];
2954 MIB.addReg(MO.getReg(),
2955 getDefRegState(MO.isDef()) |
2956 RegState::Implicit |
2957 getKillRegState(MO.isKill()) |
2958 getDeadRegState(MO.isDead()) |
2959 getUndefRegState(MO.isUndef()));
2960 }
2961 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2962 unsigned NewOpc = 0;
2963 switch (DataMI->getOpcode()) {
2964 default: break;
2965 case X86::CMP64ri32:
2966 case X86::CMP64ri8:
2967 case X86::CMP32ri:
2968 case X86::CMP32ri8:
2969 case X86::CMP16ri:
2970 case X86::CMP16ri8:
2971 case X86::CMP8ri: {
2972 MachineOperand &MO0 = DataMI->getOperand(0);
2973 MachineOperand &MO1 = DataMI->getOperand(1);
2974 if (MO1.getImm() == 0) {
2975 switch (DataMI->getOpcode()) {
2976 default: break;
2977 case X86::CMP64ri8:
2978 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2979 case X86::CMP32ri8:
2980 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2981 case X86::CMP16ri8:
2982 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2983 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2984 }
2985 DataMI->setDesc(get(NewOpc));
2986 MO1.ChangeToRegister(MO0.getReg(), false);
2987 }
2988 }
2989 }
2990 NewMIs.push_back(DataMI);
2991
2992 // Emit the store instruction.
2993 if (UnfoldStore) {
2994 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI);
2995 std::pair<MachineInstr::mmo_iterator,
2996 MachineInstr::mmo_iterator> MMOs =
2997 MF.extractStoreMemRefs(MI->memoperands_begin(),
2998 MI->memoperands_end());
2999 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
3000 }
3001
3002 return true;
3003 }
3004
3005 bool
unfoldMemoryOperand(SelectionDAG & DAG,SDNode * N,SmallVectorImpl<SDNode * > & NewNodes) const3006 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
3007 SmallVectorImpl<SDNode*> &NewNodes) const {
3008 if (!N->isMachineOpcode())
3009 return false;
3010
3011 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3012 MemOp2RegOpTable.find(N->getMachineOpcode());
3013 if (I == MemOp2RegOpTable.end())
3014 return false;
3015 unsigned Opc = I->second.first;
3016 unsigned Index = I->second.second & TB_INDEX_MASK;
3017 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3018 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3019 const MCInstrDesc &MCID = get(Opc);
3020 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
3021 unsigned NumDefs = MCID.NumDefs;
3022 std::vector<SDValue> AddrOps;
3023 std::vector<SDValue> BeforeOps;
3024 std::vector<SDValue> AfterOps;
3025 DebugLoc dl = N->getDebugLoc();
3026 unsigned NumOps = N->getNumOperands();
3027 for (unsigned i = 0; i != NumOps-1; ++i) {
3028 SDValue Op = N->getOperand(i);
3029 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
3030 AddrOps.push_back(Op);
3031 else if (i < Index-NumDefs)
3032 BeforeOps.push_back(Op);
3033 else if (i > Index-NumDefs)
3034 AfterOps.push_back(Op);
3035 }
3036 SDValue Chain = N->getOperand(NumOps-1);
3037 AddrOps.push_back(Chain);
3038
3039 // Emit the load instruction.
3040 SDNode *Load = 0;
3041 MachineFunction &MF = DAG.getMachineFunction();
3042 if (FoldedLoad) {
3043 EVT VT = *RC->vt_begin();
3044 std::pair<MachineInstr::mmo_iterator,
3045 MachineInstr::mmo_iterator> MMOs =
3046 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3047 cast<MachineSDNode>(N)->memoperands_end());
3048 if (!(*MMOs.first) &&
3049 RC == &X86::VR128RegClass &&
3050 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3051 // Do not introduce a slow unaligned load.
3052 return false;
3053 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3054 bool isAligned = (*MMOs.first) &&
3055 (*MMOs.first)->getAlignment() >= Alignment;
3056 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
3057 VT, MVT::Other, &AddrOps[0], AddrOps.size());
3058 NewNodes.push_back(Load);
3059
3060 // Preserve memory reference information.
3061 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
3062 }
3063
3064 // Emit the data processing instruction.
3065 std::vector<EVT> VTs;
3066 const TargetRegisterClass *DstRC = 0;
3067 if (MCID.getNumDefs() > 0) {
3068 DstRC = getRegClass(MCID, 0, &RI);
3069 VTs.push_back(*DstRC->vt_begin());
3070 }
3071 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
3072 EVT VT = N->getValueType(i);
3073 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
3074 VTs.push_back(VT);
3075 }
3076 if (Load)
3077 BeforeOps.push_back(SDValue(Load, 0));
3078 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
3079 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
3080 BeforeOps.size());
3081 NewNodes.push_back(NewNode);
3082
3083 // Emit the store instruction.
3084 if (FoldedStore) {
3085 AddrOps.pop_back();
3086 AddrOps.push_back(SDValue(NewNode, 0));
3087 AddrOps.push_back(Chain);
3088 std::pair<MachineInstr::mmo_iterator,
3089 MachineInstr::mmo_iterator> MMOs =
3090 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3091 cast<MachineSDNode>(N)->memoperands_end());
3092 if (!(*MMOs.first) &&
3093 RC == &X86::VR128RegClass &&
3094 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3095 // Do not introduce a slow unaligned store.
3096 return false;
3097 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3098 bool isAligned = (*MMOs.first) &&
3099 (*MMOs.first)->getAlignment() >= Alignment;
3100 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
3101 isAligned, TM),
3102 dl, MVT::Other,
3103 &AddrOps[0], AddrOps.size());
3104 NewNodes.push_back(Store);
3105
3106 // Preserve memory reference information.
3107 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
3108 }
3109
3110 return true;
3111 }
3112
getOpcodeAfterMemoryUnfold(unsigned Opc,bool UnfoldLoad,bool UnfoldStore,unsigned * LoadRegIndex) const3113 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
3114 bool UnfoldLoad, bool UnfoldStore,
3115 unsigned *LoadRegIndex) const {
3116 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3117 MemOp2RegOpTable.find(Opc);
3118 if (I == MemOp2RegOpTable.end())
3119 return 0;
3120 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3121 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3122 if (UnfoldLoad && !FoldedLoad)
3123 return 0;
3124 if (UnfoldStore && !FoldedStore)
3125 return 0;
3126 if (LoadRegIndex)
3127 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
3128 return I->second.first;
3129 }
3130
3131 bool
areLoadsFromSameBasePtr(SDNode * Load1,SDNode * Load2,int64_t & Offset1,int64_t & Offset2) const3132 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
3133 int64_t &Offset1, int64_t &Offset2) const {
3134 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
3135 return false;
3136 unsigned Opc1 = Load1->getMachineOpcode();
3137 unsigned Opc2 = Load2->getMachineOpcode();
3138 switch (Opc1) {
3139 default: return false;
3140 case X86::MOV8rm:
3141 case X86::MOV16rm:
3142 case X86::MOV32rm:
3143 case X86::MOV64rm:
3144 case X86::LD_Fp32m:
3145 case X86::LD_Fp64m:
3146 case X86::LD_Fp80m:
3147 case X86::MOVSSrm:
3148 case X86::MOVSDrm:
3149 case X86::MMX_MOVD64rm:
3150 case X86::MMX_MOVQ64rm:
3151 case X86::FsMOVAPSrm:
3152 case X86::FsMOVAPDrm:
3153 case X86::MOVAPSrm:
3154 case X86::MOVUPSrm:
3155 case X86::MOVAPDrm:
3156 case X86::MOVDQArm:
3157 case X86::MOVDQUrm:
3158 // AVX load instructions
3159 case X86::VMOVSSrm:
3160 case X86::VMOVSDrm:
3161 case X86::FsVMOVAPSrm:
3162 case X86::FsVMOVAPDrm:
3163 case X86::VMOVAPSrm:
3164 case X86::VMOVUPSrm:
3165 case X86::VMOVAPDrm:
3166 case X86::VMOVDQArm:
3167 case X86::VMOVDQUrm:
3168 case X86::VMOVAPSYrm:
3169 case X86::VMOVUPSYrm:
3170 case X86::VMOVAPDYrm:
3171 case X86::VMOVDQAYrm:
3172 case X86::VMOVDQUYrm:
3173 break;
3174 }
3175 switch (Opc2) {
3176 default: return false;
3177 case X86::MOV8rm:
3178 case X86::MOV16rm:
3179 case X86::MOV32rm:
3180 case X86::MOV64rm:
3181 case X86::LD_Fp32m:
3182 case X86::LD_Fp64m:
3183 case X86::LD_Fp80m:
3184 case X86::MOVSSrm:
3185 case X86::MOVSDrm:
3186 case X86::MMX_MOVD64rm:
3187 case X86::MMX_MOVQ64rm:
3188 case X86::FsMOVAPSrm:
3189 case X86::FsMOVAPDrm:
3190 case X86::MOVAPSrm:
3191 case X86::MOVUPSrm:
3192 case X86::MOVAPDrm:
3193 case X86::MOVDQArm:
3194 case X86::MOVDQUrm:
3195 // AVX load instructions
3196 case X86::VMOVSSrm:
3197 case X86::VMOVSDrm:
3198 case X86::FsVMOVAPSrm:
3199 case X86::FsVMOVAPDrm:
3200 case X86::VMOVAPSrm:
3201 case X86::VMOVUPSrm:
3202 case X86::VMOVAPDrm:
3203 case X86::VMOVDQArm:
3204 case X86::VMOVDQUrm:
3205 case X86::VMOVAPSYrm:
3206 case X86::VMOVUPSYrm:
3207 case X86::VMOVAPDYrm:
3208 case X86::VMOVDQAYrm:
3209 case X86::VMOVDQUYrm:
3210 break;
3211 }
3212
3213 // Check if chain operands and base addresses match.
3214 if (Load1->getOperand(0) != Load2->getOperand(0) ||
3215 Load1->getOperand(5) != Load2->getOperand(5))
3216 return false;
3217 // Segment operands should match as well.
3218 if (Load1->getOperand(4) != Load2->getOperand(4))
3219 return false;
3220 // Scale should be 1, Index should be Reg0.
3221 if (Load1->getOperand(1) == Load2->getOperand(1) &&
3222 Load1->getOperand(2) == Load2->getOperand(2)) {
3223 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
3224 return false;
3225
3226 // Now let's examine the displacements.
3227 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
3228 isa<ConstantSDNode>(Load2->getOperand(3))) {
3229 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
3230 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
3231 return true;
3232 }
3233 }
3234 return false;
3235 }
3236
shouldScheduleLoadsNear(SDNode * Load1,SDNode * Load2,int64_t Offset1,int64_t Offset2,unsigned NumLoads) const3237 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
3238 int64_t Offset1, int64_t Offset2,
3239 unsigned NumLoads) const {
3240 assert(Offset2 > Offset1);
3241 if ((Offset2 - Offset1) / 8 > 64)
3242 return false;
3243
3244 unsigned Opc1 = Load1->getMachineOpcode();
3245 unsigned Opc2 = Load2->getMachineOpcode();
3246 if (Opc1 != Opc2)
3247 return false; // FIXME: overly conservative?
3248
3249 switch (Opc1) {
3250 default: break;
3251 case X86::LD_Fp32m:
3252 case X86::LD_Fp64m:
3253 case X86::LD_Fp80m:
3254 case X86::MMX_MOVD64rm:
3255 case X86::MMX_MOVQ64rm:
3256 return false;
3257 }
3258
3259 EVT VT = Load1->getValueType(0);
3260 switch (VT.getSimpleVT().SimpleTy) {
3261 default:
3262 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
3263 // have 16 of them to play with.
3264 if (TM.getSubtargetImpl()->is64Bit()) {
3265 if (NumLoads >= 3)
3266 return false;
3267 } else if (NumLoads) {
3268 return false;
3269 }
3270 break;
3271 case MVT::i8:
3272 case MVT::i16:
3273 case MVT::i32:
3274 case MVT::i64:
3275 case MVT::f32:
3276 case MVT::f64:
3277 if (NumLoads)
3278 return false;
3279 break;
3280 }
3281
3282 return true;
3283 }
3284
3285
3286 bool X86InstrInfo::
ReverseBranchCondition(SmallVectorImpl<MachineOperand> & Cond) const3287 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
3288 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
3289 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
3290 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
3291 return true;
3292 Cond[0].setImm(GetOppositeBranchCondition(CC));
3293 return false;
3294 }
3295
3296 bool X86InstrInfo::
isSafeToMoveRegClassDefs(const TargetRegisterClass * RC) const3297 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
3298 // FIXME: Return false for x87 stack register classes for now. We can't
3299 // allow any loads of these registers before FpGet_ST0_80.
3300 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
3301 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
3302 }
3303
3304 /// getGlobalBaseReg - Return a virtual register initialized with the
3305 /// the global base register value. Output instructions required to
3306 /// initialize the register in the function entry block, if necessary.
3307 ///
3308 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
3309 ///
getGlobalBaseReg(MachineFunction * MF) const3310 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3311 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3312 "X86-64 PIC uses RIP relative addressing");
3313
3314 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3315 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3316 if (GlobalBaseReg != 0)
3317 return GlobalBaseReg;
3318
3319 // Create the register. The code to initialize it is inserted
3320 // later, by the CGBR pass (below).
3321 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3322 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3323 X86FI->setGlobalBaseReg(GlobalBaseReg);
3324 return GlobalBaseReg;
3325 }
3326
3327 // These are the replaceable SSE instructions. Some of these have Int variants
3328 // that we don't include here. We don't want to replace instructions selected
3329 // by intrinsics.
3330 static const unsigned ReplaceableInstrs[][3] = {
3331 //PackedSingle PackedDouble PackedInt
3332 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
3333 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
3334 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
3335 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
3336 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
3337 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
3338 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
3339 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
3340 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
3341 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
3342 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
3343 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
3344 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
3345 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
3346 // AVX 128-bit support
3347 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
3348 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
3349 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
3350 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
3351 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
3352 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
3353 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
3354 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
3355 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
3356 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
3357 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
3358 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
3359 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
3360 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
3361 // AVX 256-bit support
3362 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
3363 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
3364 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
3365 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
3366 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
3367 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr },
3368 };
3369
3370 // FIXME: Some shuffle and unpack instructions have equivalents in different
3371 // domains, but they require a bit more work than just switching opcodes.
3372
lookup(unsigned opcode,unsigned domain)3373 static const unsigned *lookup(unsigned opcode, unsigned domain) {
3374 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
3375 if (ReplaceableInstrs[i][domain-1] == opcode)
3376 return ReplaceableInstrs[i];
3377 return 0;
3378 }
3379
3380 std::pair<uint16_t, uint16_t>
getExecutionDomain(const MachineInstr * MI) const3381 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3382 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3383 return std::make_pair(domain,
3384 domain && lookup(MI->getOpcode(), domain) ? 0xe : 0);
3385 }
3386
setExecutionDomain(MachineInstr * MI,unsigned Domain) const3387 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
3388 assert(Domain>0 && Domain<4 && "Invalid execution domain");
3389 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3390 assert(dom && "Not an SSE instruction");
3391 const unsigned *table = lookup(MI->getOpcode(), dom);
3392 assert(table && "Cannot change domain");
3393 MI->setDesc(get(table[Domain-1]));
3394 }
3395
3396 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
getNoopForMachoTarget(MCInst & NopInst) const3397 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3398 NopInst.setOpcode(X86::NOOP);
3399 }
3400
isHighLatencyDef(int opc) const3401 bool X86InstrInfo::isHighLatencyDef(int opc) const {
3402 switch (opc) {
3403 default: return false;
3404 case X86::DIVSDrm:
3405 case X86::DIVSDrm_Int:
3406 case X86::DIVSDrr:
3407 case X86::DIVSDrr_Int:
3408 case X86::DIVSSrm:
3409 case X86::DIVSSrm_Int:
3410 case X86::DIVSSrr:
3411 case X86::DIVSSrr_Int:
3412 case X86::SQRTPDm:
3413 case X86::SQRTPDm_Int:
3414 case X86::SQRTPDr:
3415 case X86::SQRTPDr_Int:
3416 case X86::SQRTPSm:
3417 case X86::SQRTPSm_Int:
3418 case X86::SQRTPSr:
3419 case X86::SQRTPSr_Int:
3420 case X86::SQRTSDm:
3421 case X86::SQRTSDm_Int:
3422 case X86::SQRTSDr:
3423 case X86::SQRTSDr_Int:
3424 case X86::SQRTSSm:
3425 case X86::SQRTSSm_Int:
3426 case X86::SQRTSSr:
3427 case X86::SQRTSSr_Int:
3428 // AVX instructions with high latency
3429 case X86::VDIVSDrm:
3430 case X86::VDIVSDrm_Int:
3431 case X86::VDIVSDrr:
3432 case X86::VDIVSDrr_Int:
3433 case X86::VDIVSSrm:
3434 case X86::VDIVSSrm_Int:
3435 case X86::VDIVSSrr:
3436 case X86::VDIVSSrr_Int:
3437 case X86::VSQRTPDm:
3438 case X86::VSQRTPDm_Int:
3439 case X86::VSQRTPDr:
3440 case X86::VSQRTPDr_Int:
3441 case X86::VSQRTPSm:
3442 case X86::VSQRTPSm_Int:
3443 case X86::VSQRTPSr:
3444 case X86::VSQRTPSr_Int:
3445 case X86::VSQRTSDm:
3446 case X86::VSQRTSDm_Int:
3447 case X86::VSQRTSDr:
3448 case X86::VSQRTSSm:
3449 case X86::VSQRTSSm_Int:
3450 case X86::VSQRTSSr:
3451 return true;
3452 }
3453 }
3454
3455 bool X86InstrInfo::
hasHighOperandLatency(const InstrItineraryData * ItinData,const MachineRegisterInfo * MRI,const MachineInstr * DefMI,unsigned DefIdx,const MachineInstr * UseMI,unsigned UseIdx) const3456 hasHighOperandLatency(const InstrItineraryData *ItinData,
3457 const MachineRegisterInfo *MRI,
3458 const MachineInstr *DefMI, unsigned DefIdx,
3459 const MachineInstr *UseMI, unsigned UseIdx) const {
3460 return isHighLatencyDef(DefMI->getOpcode());
3461 }
3462
3463 namespace {
3464 /// CGBR - Create Global Base Reg pass. This initializes the PIC
3465 /// global base register for x86-32.
3466 struct CGBR : public MachineFunctionPass {
3467 static char ID;
CGBR__anon14a8066b0211::CGBR3468 CGBR() : MachineFunctionPass(ID) {}
3469
runOnMachineFunction__anon14a8066b0211::CGBR3470 virtual bool runOnMachineFunction(MachineFunction &MF) {
3471 const X86TargetMachine *TM =
3472 static_cast<const X86TargetMachine *>(&MF.getTarget());
3473
3474 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
3475 "X86-64 PIC uses RIP relative addressing");
3476
3477 // Only emit a global base reg in PIC mode.
3478 if (TM->getRelocationModel() != Reloc::PIC_)
3479 return false;
3480
3481 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
3482 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3483
3484 // If we didn't need a GlobalBaseReg, don't insert code.
3485 if (GlobalBaseReg == 0)
3486 return false;
3487
3488 // Insert the set of GlobalBaseReg into the first MBB of the function
3489 MachineBasicBlock &FirstMBB = MF.front();
3490 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3491 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3492 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3493 const X86InstrInfo *TII = TM->getInstrInfo();
3494
3495 unsigned PC;
3496 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
3497 PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3498 else
3499 PC = GlobalBaseReg;
3500
3501 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3502 // only used in JIT code emission as displacement to pc.
3503 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3504
3505 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3506 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3507 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3508 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3509 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3510 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3511 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3512 }
3513
3514 return true;
3515 }
3516
getPassName__anon14a8066b0211::CGBR3517 virtual const char *getPassName() const {
3518 return "X86 PIC Global Base Reg Initialization";
3519 }
3520
getAnalysisUsage__anon14a8066b0211::CGBR3521 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
3522 AU.setPreservesCFG();
3523 MachineFunctionPass::getAnalysisUsage(AU);
3524 }
3525 };
3526 }
3527
3528 char CGBR::ID = 0;
3529 FunctionPass*
createGlobalBaseRegPass()3530 llvm::createGlobalBaseRegPass() { return new CGBR(); }
3531