1; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
2; pr4843
3define <4 x i16> @v2regbug(<4 x i16>* %B) nounwind {
4;CHECK: v2regbug:
5;CHECK: vzip.16
6	%tmp1 = load <4 x i16>* %B
7	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32><i32 0, i32 0, i32 1, i32 1>
8	ret <4 x i16> %tmp2
9}
10