1; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 2; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=VFP2 3; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEON 4; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2 5 6define i32 @test1(float %a, float %b) { 7; VFP2: test1: 8; VFP2: vcvt.s32.f32 s{{.}}, s{{.}} 9; NEON: test1: 10; NEON: vadd.f32 [[D0:d[0-9]+]] 11; NEON: vcvt.s32.f32 d0, [[D0]] 12entry: 13 %0 = fadd float %a, %b 14 %1 = fptosi float %0 to i32 15 ret i32 %1 16} 17 18define i32 @test2(float %a, float %b) { 19; VFP2: test2: 20; VFP2: vcvt.u32.f32 s{{.}}, s{{.}} 21; NEON: test2: 22; NEON: vadd.f32 [[D0:d[0-9]+]] 23; NEON: vcvt.u32.f32 d0, [[D0]] 24entry: 25 %0 = fadd float %a, %b 26 %1 = fptoui float %0 to i32 27 ret i32 %1 28} 29 30define float @test3(i32 %a, i32 %b) { 31; VFP2: test3: 32; VFP2: vcvt.f32.u32 s{{.}}, s{{.}} 33; NEON: test3: 34; NEON: vcvt.f32.u32 d0, d0 35entry: 36 %0 = add i32 %a, %b 37 %1 = uitofp i32 %0 to float 38 ret float %1 39} 40 41define float @test4(i32 %a, i32 %b) { 42; VFP2: test4: 43; VFP2: vcvt.f32.s32 s{{.}}, s{{.}} 44; NEON: test4: 45; NEON: vcvt.f32.s32 d0, d0 46entry: 47 %0 = add i32 %a, %b 48 %1 = sitofp i32 %0 to float 49 ret float %1 50} 51