1; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARM
2; RUN: llc < %s -mtriple=thumb-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=T2
3; rdar://8662825
4
5define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
6; ARM: t1:
7; ARM: sub r0, r1, #-2147483647
8; ARM: movgt r0, r1
9
10; T2: t1:
11; T2: mvn r0, #-2147483648
12; T2: add r0, r1
13; T2: movgt r0, r1
14  %tmp1 = icmp sgt i32 %c, 10
15  %tmp2 = select i1 %tmp1, i32 0, i32 2147483647
16  %tmp3 = add i32 %tmp2, %b
17  ret i32 %tmp3
18}
19
20define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
21; ARM: t2:
22; ARM: sub r0, r1, #10
23; ARM: movgt r0, r1
24
25; T2: t2:
26; T2: sub.w r0, r1, #10
27; T2: movgt r0, r1
28  %tmp1 = icmp sgt i32 %c, 10
29  %tmp2 = select i1 %tmp1, i32 0, i32 10
30  %tmp3 = sub i32 %b, %tmp2
31  ret i32 %tmp3
32}
33
34define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
35; ARM: t3:
36; ARM: mvnlt r2, #0
37; ARM: and r0, r2, r3
38
39; T2: t3:
40; T2: movlt.w r2, #-1
41; T2: and.w r0, r2, r3
42  %cond = icmp slt i32 %a, %b
43  %z = select i1 %cond, i32 -1, i32 %x
44  %s = and i32 %z, %y
45 ret i32 %s
46}
47
48define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
49; ARM: t4:
50; ARM: movlt r2, #0
51; ARM: orr r0, r2, r3
52
53; T2: t4:
54; T2: movlt r2, #0
55; T2: orr.w r0, r2, r3
56  %cond = icmp slt i32 %a, %b
57  %z = select i1 %cond, i32 0, i32 %x
58  %s = or i32 %z, %y
59 ret i32 %s
60}
61