1; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
2
3define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
4;CHECK: vqsubs8:
5;CHECK: vqsub.s8
6	%tmp1 = load <8 x i8>* %A
7	%tmp2 = load <8 x i8>* %B
8	%tmp3 = call <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
9	ret <8 x i8> %tmp3
10}
11
12define <4 x i16> @vqsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
13;CHECK: vqsubs16:
14;CHECK: vqsub.s16
15	%tmp1 = load <4 x i16>* %A
16	%tmp2 = load <4 x i16>* %B
17	%tmp3 = call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
18	ret <4 x i16> %tmp3
19}
20
21define <2 x i32> @vqsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
22;CHECK: vqsubs32:
23;CHECK: vqsub.s32
24	%tmp1 = load <2 x i32>* %A
25	%tmp2 = load <2 x i32>* %B
26	%tmp3 = call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
27	ret <2 x i32> %tmp3
28}
29
30define <1 x i64> @vqsubs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
31;CHECK: vqsubs64:
32;CHECK: vqsub.s64
33	%tmp1 = load <1 x i64>* %A
34	%tmp2 = load <1 x i64>* %B
35	%tmp3 = call <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
36	ret <1 x i64> %tmp3
37}
38
39define <8 x i8> @vqsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
40;CHECK: vqsubu8:
41;CHECK: vqsub.u8
42	%tmp1 = load <8 x i8>* %A
43	%tmp2 = load <8 x i8>* %B
44	%tmp3 = call <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
45	ret <8 x i8> %tmp3
46}
47
48define <4 x i16> @vqsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
49;CHECK: vqsubu16:
50;CHECK: vqsub.u16
51	%tmp1 = load <4 x i16>* %A
52	%tmp2 = load <4 x i16>* %B
53	%tmp3 = call <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
54	ret <4 x i16> %tmp3
55}
56
57define <2 x i32> @vqsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
58;CHECK: vqsubu32:
59;CHECK: vqsub.u32
60	%tmp1 = load <2 x i32>* %A
61	%tmp2 = load <2 x i32>* %B
62	%tmp3 = call <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
63	ret <2 x i32> %tmp3
64}
65
66define <1 x i64> @vqsubu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
67;CHECK: vqsubu64:
68;CHECK: vqsub.u64
69	%tmp1 = load <1 x i64>* %A
70	%tmp2 = load <1 x i64>* %B
71	%tmp3 = call <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
72	ret <1 x i64> %tmp3
73}
74
75define <16 x i8> @vqsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
76;CHECK: vqsubQs8:
77;CHECK: vqsub.s8
78	%tmp1 = load <16 x i8>* %A
79	%tmp2 = load <16 x i8>* %B
80	%tmp3 = call <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
81	ret <16 x i8> %tmp3
82}
83
84define <8 x i16> @vqsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
85;CHECK: vqsubQs16:
86;CHECK: vqsub.s16
87	%tmp1 = load <8 x i16>* %A
88	%tmp2 = load <8 x i16>* %B
89	%tmp3 = call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
90	ret <8 x i16> %tmp3
91}
92
93define <4 x i32> @vqsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
94;CHECK: vqsubQs32:
95;CHECK: vqsub.s32
96	%tmp1 = load <4 x i32>* %A
97	%tmp2 = load <4 x i32>* %B
98	%tmp3 = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
99	ret <4 x i32> %tmp3
100}
101
102define <2 x i64> @vqsubQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
103;CHECK: vqsubQs64:
104;CHECK: vqsub.s64
105	%tmp1 = load <2 x i64>* %A
106	%tmp2 = load <2 x i64>* %B
107	%tmp3 = call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
108	ret <2 x i64> %tmp3
109}
110
111define <16 x i8> @vqsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
112;CHECK: vqsubQu8:
113;CHECK: vqsub.u8
114	%tmp1 = load <16 x i8>* %A
115	%tmp2 = load <16 x i8>* %B
116	%tmp3 = call <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
117	ret <16 x i8> %tmp3
118}
119
120define <8 x i16> @vqsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
121;CHECK: vqsubQu16:
122;CHECK: vqsub.u16
123	%tmp1 = load <8 x i16>* %A
124	%tmp2 = load <8 x i16>* %B
125	%tmp3 = call <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
126	ret <8 x i16> %tmp3
127}
128
129define <4 x i32> @vqsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
130;CHECK: vqsubQu32:
131;CHECK: vqsub.u32
132	%tmp1 = load <4 x i32>* %A
133	%tmp2 = load <4 x i32>* %B
134	%tmp3 = call <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
135	ret <4 x i32> %tmp3
136}
137
138define <2 x i64> @vqsubQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
139;CHECK: vqsubQu64:
140;CHECK: vqsub.u64
141	%tmp1 = load <2 x i64>* %A
142	%tmp2 = load <2 x i64>* %B
143	%tmp3 = call <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
144	ret <2 x i64> %tmp3
145}
146
147declare <8 x i8>  @llvm.arm.neon.vqsubs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
148declare <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
149declare <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
150declare <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
151
152declare <8 x i8>  @llvm.arm.neon.vqsubu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
153declare <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
154declare <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
155declare <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
156
157declare <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
158declare <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
159declare <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
160declare <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
161
162declare <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
163declare <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
164declare <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
165declare <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
166