1; RUN: llc < %s -march=cellspu > %t1.s
2; RUN: grep mpy     %t1.s | count 44
3; RUN: grep mpyu    %t1.s | count 4
4; RUN: grep mpyh    %t1.s | count 10
5; RUN: grep mpyhh   %t1.s | count 2
6; RUN: grep rotma   %t1.s | count 12
7; RUN: grep rotmahi %t1.s | count 4
8; RUN: grep and     %t1.s | count 2
9; RUN: grep selb    %t1.s | count 6
10; RUN: grep fsmbi   %t1.s | count 4
11; RUN: grep shli    %t1.s | count 4
12; RUN: grep shlhi   %t1.s | count 4
13; RUN: grep ila     %t1.s | count 2
14target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
15target triple = "spu"
16
17; 32-bit multiply instruction generation:
18define <4 x i32> @mpy_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
19entry:
20        %A = mul <4 x i32> %arg1, %arg2
21        ret <4 x i32> %A
22}
23
24define <4 x i32> @mpy_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
25entry:
26        %A = mul <4 x i32> %arg2, %arg1
27        ret <4 x i32> %A
28}
29
30define <8 x i16> @mpy_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
31entry:
32        %A = mul <8 x i16> %arg1, %arg2
33        ret <8 x i16> %A
34}
35
36define <8 x i16> @mpy_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) {
37entry:
38        %A = mul <8 x i16> %arg2, %arg1
39        ret <8 x i16> %A
40}
41
42define <16 x i8> @mul_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) {
43entry:
44        %A = mul <16 x i8> %arg2, %arg1
45        ret <16 x i8> %A
46}
47
48define <16 x i8> @mul_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) {
49entry:
50        %A = mul <16 x i8> %arg1, %arg2
51        ret <16 x i8> %A
52}
53
54define i32 @mul_i32_1(i32 %arg1, i32 %arg2) {
55entry:
56        %A = mul i32 %arg2, %arg1
57        ret i32 %A
58}
59
60define i32 @mul_i32_2(i32 %arg1, i32 %arg2) {
61entry:
62        %A = mul i32 %arg1, %arg2
63        ret i32 %A
64}
65
66define i16 @mul_i16_1(i16 %arg1, i16 %arg2) {
67entry:
68        %A = mul i16 %arg2, %arg1
69        ret i16 %A
70}
71
72define i16 @mul_i16_2(i16 %arg1, i16 %arg2) {
73entry:
74        %A = mul i16 %arg1, %arg2
75        ret i16 %A
76}
77
78define i8 @mul_i8_1(i8 %arg1, i8 %arg2) {
79entry:
80        %A = mul i8 %arg2, %arg1
81        ret i8 %A
82}
83
84define i8 @mul_i8_2(i8 %arg1, i8 %arg2) {
85entry:
86        %A = mul i8 %arg1, %arg2
87        ret i8 %A
88}
89