1//===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===//
2//
3//                        The Subzero Code Generator
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines properties of ARM32 instructions in the form of x-macros.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef SUBZERO_SRC_ICEINSTARM32_DEF
15#define SUBZERO_SRC_ICEINSTARM32_DEF
16
17#include "IceRegList.h"
18
19// NOTE: PC and SP are not considered isInt, to avoid register allocating.
20//
21// For the NaCl sandbox we also need to r9 (and the r8-r9 pair) for TLS, so
22// just reserve always.
23// TODO(jpp): Allow r9 to be isInt when sandboxing is turned off (native mode).
24//
25// IP is not considered isInt to reserve it as a scratch register. A scratch
26// register is useful for expanding instructions post-register allocation.
27//
28// LR is not considered isInt to avoid being allocated as a register. It is
29// technically preserved, but save/restore is handled separately, based on
30// whether or not the function MaybeLeafFunc.
31//
32// The register tables can be generated using the gen_arm32_reg_tables.py
33// script.
34
35#include "IceRegistersARM32.def"
36// The register tables defined in IceRegistersARM32 use the following x-macro:
37//#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,
38//          isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
39
40// We also provide a combined table, so that there is a namespace where all of
41// the registers are considered and have distinct numberings. This is in
42// contrast to the above, where the "encode" is based on how the register
43// numbers will be encoded in binaries and values can overlap.
44#define REGARM32_TABLE                                                         \
45  /* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,        \
46     isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */          \
47  REGARM32_GPR_TABLE                                                           \
48  REGARM32_I64PAIR_TABLE                                                       \
49  REGARM32_FP32_TABLE                                                          \
50  REGARM32_FP64_TABLE                                                          \
51  REGARM32_VEC128_TABLE
52//#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,
53//          isGPR, isInt, isFP32, isFP64, isVec128, alias_init)
54
55#define REGARM32_TABLE_BOUNDS                                                  \
56  /* val, init */                                                              \
57  X(Reg_GPR_First, = Reg_r0)                                                   \
58  X(Reg_GPR_Last, = Reg_pc)                                                    \
59  X(Reg_I64PAIR_First, = Reg_r0r1)                                             \
60  X(Reg_I64PAIR_Last, = Reg_r10fp)                                             \
61  X(Reg_SREG_First, = Reg_s0)                                                  \
62  X(Reg_SREG_Last, = Reg_s31)                                                  \
63  X(Reg_DREG_First, = Reg_d0)                                                  \
64  X(Reg_DREG_Last, = Reg_d31)                                                  \
65  X(Reg_QREG_First, = Reg_q0)                                                  \
66  X(Reg_QREG_Last, = Reg_q15)
67// define X(val, init)
68
69// Load/Store instruction width suffixes and FP/Vector element size suffixes
70// the # of offset bits allowed as part of an addressing mode (for sign or zero
71// extending load/stores).
72#define ICETYPEARM32_TABLE                                                     \
73  /* tag,          element type, int_width, fp_width, uvec_width, svec_width,  \
74     addr bits sext, zext, reg-reg addr allowed, shift allowed, */             \
75  X(IceType_void,  IceType_void, "" , ""    , ""    , ""    , 0 , 0 , 0, 0)    \
76  X(IceType_i1,    IceType_void, "b", ""    , ""    , ""    , 8 , 12, 1, 1)    \
77  X(IceType_i8,    IceType_void, "b", ""    , ""    , ""    , 8 , 12, 1, 1)    \
78  X(IceType_i16,   IceType_void, "h", ""    , ""    , ""    , 8 , 8 , 1, 0)    \
79  X(IceType_i32,   IceType_void, "" , ""    , ""    , ""    , 12, 12, 1, 1)    \
80  X(IceType_i64,   IceType_void, "d", ""    , ""    , ""    , 12, 12, 1, 1)    \
81  X(IceType_f32,   IceType_void, "" , ".f32", ""    , ""    , 8,  8 , 0, 0)    \
82  X(IceType_f64,   IceType_void, "" , ".f64", ""    , ""    , 8,  8 , 0, 0)    \
83  X(IceType_v4i1,  IceType_i32 , "" , ".i32", ".u32", ".s32", 0 , 0 , 1, 0)    \
84  X(IceType_v8i1,  IceType_i16 , "" , ".i16", ".u16", ".s16", 0 , 0 , 1, 0)    \
85  X(IceType_v16i1, IceType_i8  , "" , ".i8" , ".u8" , ".s8" , 0 , 0 , 1, 0)    \
86  X(IceType_v16i8, IceType_i8  , "" , ".i8" , ".u8" , ".s8" , 0 , 0 , 1, 0)    \
87  X(IceType_v8i16, IceType_i16 , "" , ".i16", ".u16", ".s16", 0 , 0 , 1, 0)    \
88  X(IceType_v4i32, IceType_i32 , "" , ".i32", ".u32", ".s32", 0 , 0 , 1, 0)    \
89  X(IceType_v4f32, IceType_f32 , "" , ".f32", ".f32", ".f32", 0 , 0 , 1, 0)
90//#define X(tag, elementty, int_width, fp_width, uvec_width, svec_width, sbits,
91//          ubits, rraddr, shaddr)
92
93// Shifter types for Data-processing operands as defined in section A5.1.2.
94#define ICEINSTARM32SHIFT_TABLE                                                \
95  /* enum value, emit */                                                       \
96  X(LSL, "lsl")                                                                \
97  X(LSR, "lsr")                                                                \
98  X(ASR, "asr")                                                                \
99  X(ROR, "ror")                                                                \
100  X(RRX, "rrx")
101//#define X(tag, emit)
102
103// Attributes for the condition code 4-bit encoding (that is independent of the
104// APSR's NZCV fields). For example, EQ is 0, but corresponds to Z = 1, and NE
105// is 1, but corresponds to Z = 0.
106#define ICEINSTARM32COND_TABLE                                                 \
107  /* enum value, encoding, opposite, emit */                                   \
108  X(EQ, 0, NE, "eq")        /* equal */                                        \
109  X(NE, 1, EQ, "ne")        /* not equal */                                    \
110  X(CS, 2, CC, "cs")        /* carry set/unsigned (AKA hs: higher or same) */  \
111  X(CC, 3, CS, "cc")        /* carry clear/unsigned (AKA lo: lower) */         \
112  X(MI, 4, PL, "mi")        /* minus/negative */                               \
113  X(PL, 5, MI, "pl")        /* plus/positive or zero */                        \
114  X(VS, 6, VC, "vs")        /* overflow (float unordered) */                   \
115  X(VC, 7, VS, "vc")        /* no overflow (float not unordered) */            \
116  X(HI, 8, LS, "hi")        /* unsigned higher */                              \
117  X(LS, 9, HI, "ls")        /* unsigned lower or same */                       \
118  X(GE, 10, LT, "ge")       /* signed greater than or equal */                 \
119  X(LT, 11, GE, "lt")       /* signed less than */                             \
120  X(GT, 12, LE, "gt")       /* signed greater than */                          \
121  X(LE, 13, GT, "le")       /* signed less than or equal */                    \
122  X(AL, 14, kNone, "")      /* always (unconditional) */                       \
123  X(kNone, 15, kNone, "??") /* special condition / none */
124//#define X(tag, encode, opp, emit)
125
126#endif // SUBZERO_SRC_ICEINSTARM32_DEF
127