1 // Copyright 2014 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ 6 #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ 7 8 namespace v8 { 9 namespace internal { 10 namespace compiler { 11 12 // IA32-specific opcodes that specify which assembly sequence to emit. 13 // Most opcodes specify a single instruction. 14 #define TARGET_ARCH_OPCODE_LIST(V) \ 15 V(IA32Add) \ 16 V(IA32And) \ 17 V(IA32Cmp) \ 18 V(IA32Cmp16) \ 19 V(IA32Cmp8) \ 20 V(IA32Test) \ 21 V(IA32Test16) \ 22 V(IA32Test8) \ 23 V(IA32Or) \ 24 V(IA32Xor) \ 25 V(IA32Sub) \ 26 V(IA32Imul) \ 27 V(IA32ImulHigh) \ 28 V(IA32UmulHigh) \ 29 V(IA32Idiv) \ 30 V(IA32Udiv) \ 31 V(IA32Not) \ 32 V(IA32Neg) \ 33 V(IA32Shl) \ 34 V(IA32Shr) \ 35 V(IA32Sar) \ 36 V(IA32AddPair) \ 37 V(IA32SubPair) \ 38 V(IA32MulPair) \ 39 V(IA32ShlPair) \ 40 V(IA32ShrPair) \ 41 V(IA32SarPair) \ 42 V(IA32Ror) \ 43 V(IA32Lzcnt) \ 44 V(IA32Tzcnt) \ 45 V(IA32Popcnt) \ 46 V(SSEFloat32Cmp) \ 47 V(SSEFloat32Add) \ 48 V(SSEFloat32Sub) \ 49 V(SSEFloat32Mul) \ 50 V(SSEFloat32Div) \ 51 V(SSEFloat32Abs) \ 52 V(SSEFloat32Neg) \ 53 V(SSEFloat32Sqrt) \ 54 V(SSEFloat32Round) \ 55 V(SSEFloat64Cmp) \ 56 V(SSEFloat64Add) \ 57 V(SSEFloat64Sub) \ 58 V(SSEFloat64Mul) \ 59 V(SSEFloat64Div) \ 60 V(SSEFloat64Mod) \ 61 V(SSEFloat32Max) \ 62 V(SSEFloat64Max) \ 63 V(SSEFloat32Min) \ 64 V(SSEFloat64Min) \ 65 V(SSEFloat64Abs) \ 66 V(SSEFloat64Neg) \ 67 V(SSEFloat64Sqrt) \ 68 V(SSEFloat64Round) \ 69 V(SSEFloat32ToFloat64) \ 70 V(SSEFloat64ToFloat32) \ 71 V(SSEFloat32ToInt32) \ 72 V(SSEFloat32ToUint32) \ 73 V(SSEFloat64ToInt32) \ 74 V(SSEFloat64ToUint32) \ 75 V(SSEInt32ToFloat32) \ 76 V(SSEUint32ToFloat32) \ 77 V(SSEInt32ToFloat64) \ 78 V(SSEUint32ToFloat64) \ 79 V(SSEFloat64ExtractLowWord32) \ 80 V(SSEFloat64ExtractHighWord32) \ 81 V(SSEFloat64InsertLowWord32) \ 82 V(SSEFloat64InsertHighWord32) \ 83 V(SSEFloat64LoadLowWord32) \ 84 V(SSEFloat64SilenceNaN) \ 85 V(AVXFloat32Add) \ 86 V(AVXFloat32Sub) \ 87 V(AVXFloat32Mul) \ 88 V(AVXFloat32Div) \ 89 V(AVXFloat64Add) \ 90 V(AVXFloat64Sub) \ 91 V(AVXFloat64Mul) \ 92 V(AVXFloat64Div) \ 93 V(AVXFloat64Abs) \ 94 V(AVXFloat64Neg) \ 95 V(AVXFloat32Abs) \ 96 V(AVXFloat32Neg) \ 97 V(IA32Movsxbl) \ 98 V(IA32Movzxbl) \ 99 V(IA32Movb) \ 100 V(IA32Movsxwl) \ 101 V(IA32Movzxwl) \ 102 V(IA32Movw) \ 103 V(IA32Movl) \ 104 V(IA32Movss) \ 105 V(IA32Movsd) \ 106 V(IA32BitcastFI) \ 107 V(IA32BitcastIF) \ 108 V(IA32Lea) \ 109 V(IA32Push) \ 110 V(IA32PushFloat32) \ 111 V(IA32PushFloat64) \ 112 V(IA32Poke) \ 113 V(IA32StackCheck) \ 114 V(IA32Xchgb) \ 115 V(IA32Xchgw) \ 116 V(IA32Xchgl) 117 118 // Addressing modes represent the "shape" of inputs to an instruction. 119 // Many instructions support multiple addressing modes. Addressing modes 120 // are encoded into the InstructionCode of the instruction and tell the 121 // code generator after register allocation which assembler method to call. 122 // 123 // We use the following local notation for addressing modes: 124 // 125 // M = memory operand 126 // R = base register 127 // N = index register * N for N in {1, 2, 4, 8} 128 // I = immediate displacement (int32_t) 129 130 #define TARGET_ADDRESSING_MODE_LIST(V) \ 131 V(MR) /* [%r1 ] */ \ 132 V(MRI) /* [%r1 + K] */ \ 133 V(MR1) /* [%r1 + %r2*1 ] */ \ 134 V(MR2) /* [%r1 + %r2*2 ] */ \ 135 V(MR4) /* [%r1 + %r2*4 ] */ \ 136 V(MR8) /* [%r1 + %r2*8 ] */ \ 137 V(MR1I) /* [%r1 + %r2*1 + K] */ \ 138 V(MR2I) /* [%r1 + %r2*2 + K] */ \ 139 V(MR4I) /* [%r1 + %r2*3 + K] */ \ 140 V(MR8I) /* [%r1 + %r2*4 + K] */ \ 141 V(M1) /* [ %r2*1 ] */ \ 142 V(M2) /* [ %r2*2 ] */ \ 143 V(M4) /* [ %r2*4 ] */ \ 144 V(M8) /* [ %r2*8 ] */ \ 145 V(M1I) /* [ %r2*1 + K] */ \ 146 V(M2I) /* [ %r2*2 + K] */ \ 147 V(M4I) /* [ %r2*4 + K] */ \ 148 V(M8I) /* [ %r2*8 + K] */ \ 149 V(MI) /* [ K] */ 150 151 } // namespace compiler 152 } // namespace internal 153 } // namespace v8 154 155 #endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ 156