1 // Copyright 2014 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_COMPILER_INSTRUCTION_CODES_H_ 6 #define V8_COMPILER_INSTRUCTION_CODES_H_ 7 8 #include <iosfwd> 9 10 #if V8_TARGET_ARCH_ARM 11 #include "src/compiler/arm/instruction-codes-arm.h" 12 #elif V8_TARGET_ARCH_ARM64 13 #include "src/compiler/arm64/instruction-codes-arm64.h" 14 #elif V8_TARGET_ARCH_IA32 15 #include "src/compiler/ia32/instruction-codes-ia32.h" 16 #elif V8_TARGET_ARCH_MIPS 17 #include "src/compiler/mips/instruction-codes-mips.h" 18 #elif V8_TARGET_ARCH_MIPS64 19 #include "src/compiler/mips64/instruction-codes-mips64.h" 20 #elif V8_TARGET_ARCH_X64 21 #include "src/compiler/x64/instruction-codes-x64.h" 22 #elif V8_TARGET_ARCH_PPC 23 #include "src/compiler/ppc/instruction-codes-ppc.h" 24 #elif V8_TARGET_ARCH_S390 25 #include "src/compiler/s390/instruction-codes-s390.h" 26 #elif V8_TARGET_ARCH_X87 27 #include "src/compiler/x87/instruction-codes-x87.h" 28 #else 29 #define TARGET_ARCH_OPCODE_LIST(V) 30 #define TARGET_ADDRESSING_MODE_LIST(V) 31 #endif 32 #include "src/globals.h" 33 #include "src/utils.h" 34 35 namespace v8 { 36 namespace internal { 37 namespace compiler { 38 39 // Modes for ArchStoreWithWriteBarrier below. 40 enum class RecordWriteMode { kValueIsMap, kValueIsPointer, kValueIsAny }; 41 42 43 // Target-specific opcodes that specify which assembly sequence to emit. 44 // Most opcodes specify a single instruction. 45 #define COMMON_ARCH_OPCODE_LIST(V) \ 46 V(ArchCallCodeObject) \ 47 V(ArchTailCallCodeObjectFromJSFunction) \ 48 V(ArchTailCallCodeObject) \ 49 V(ArchCallJSFunction) \ 50 V(ArchTailCallJSFunctionFromJSFunction) \ 51 V(ArchTailCallAddress) \ 52 V(ArchPrepareCallCFunction) \ 53 V(ArchCallCFunction) \ 54 V(ArchPrepareTailCall) \ 55 V(ArchJmp) \ 56 V(ArchLookupSwitch) \ 57 V(ArchTableSwitch) \ 58 V(ArchNop) \ 59 V(ArchDebugBreak) \ 60 V(ArchComment) \ 61 V(ArchThrowTerminator) \ 62 V(ArchDeoptimize) \ 63 V(ArchRet) \ 64 V(ArchStackPointer) \ 65 V(ArchFramePointer) \ 66 V(ArchParentFramePointer) \ 67 V(ArchTruncateDoubleToI) \ 68 V(ArchStoreWithWriteBarrier) \ 69 V(CheckedLoadInt8) \ 70 V(CheckedLoadUint8) \ 71 V(CheckedLoadInt16) \ 72 V(CheckedLoadUint16) \ 73 V(CheckedLoadWord32) \ 74 V(CheckedLoadWord64) \ 75 V(CheckedLoadFloat32) \ 76 V(CheckedLoadFloat64) \ 77 V(CheckedStoreWord8) \ 78 V(CheckedStoreWord16) \ 79 V(CheckedStoreWord32) \ 80 V(CheckedStoreWord64) \ 81 V(CheckedStoreFloat32) \ 82 V(CheckedStoreFloat64) \ 83 V(ArchStackSlot) \ 84 V(AtomicLoadInt8) \ 85 V(AtomicLoadUint8) \ 86 V(AtomicLoadInt16) \ 87 V(AtomicLoadUint16) \ 88 V(AtomicLoadWord32) \ 89 V(AtomicStoreWord8) \ 90 V(AtomicStoreWord16) \ 91 V(AtomicStoreWord32) \ 92 V(Ieee754Float64Acos) \ 93 V(Ieee754Float64Acosh) \ 94 V(Ieee754Float64Asin) \ 95 V(Ieee754Float64Asinh) \ 96 V(Ieee754Float64Atan) \ 97 V(Ieee754Float64Atanh) \ 98 V(Ieee754Float64Atan2) \ 99 V(Ieee754Float64Cbrt) \ 100 V(Ieee754Float64Cos) \ 101 V(Ieee754Float64Cosh) \ 102 V(Ieee754Float64Exp) \ 103 V(Ieee754Float64Expm1) \ 104 V(Ieee754Float64Log) \ 105 V(Ieee754Float64Log1p) \ 106 V(Ieee754Float64Log10) \ 107 V(Ieee754Float64Log2) \ 108 V(Ieee754Float64Pow) \ 109 V(Ieee754Float64Sin) \ 110 V(Ieee754Float64Sinh) \ 111 V(Ieee754Float64Tan) \ 112 V(Ieee754Float64Tanh) 113 114 #define ARCH_OPCODE_LIST(V) \ 115 COMMON_ARCH_OPCODE_LIST(V) \ 116 TARGET_ARCH_OPCODE_LIST(V) 117 118 enum ArchOpcode { 119 #define DECLARE_ARCH_OPCODE(Name) k##Name, 120 ARCH_OPCODE_LIST(DECLARE_ARCH_OPCODE) 121 #undef DECLARE_ARCH_OPCODE 122 #define COUNT_ARCH_OPCODE(Name) +1 123 kLastArchOpcode = -1 ARCH_OPCODE_LIST(COUNT_ARCH_OPCODE) 124 #undef COUNT_ARCH_OPCODE 125 }; 126 127 V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream& os, 128 const ArchOpcode& ao); 129 130 // Addressing modes represent the "shape" of inputs to an instruction. 131 // Many instructions support multiple addressing modes. Addressing modes 132 // are encoded into the InstructionCode of the instruction and tell the 133 // code generator after register allocation which assembler method to call. 134 #define ADDRESSING_MODE_LIST(V) \ 135 V(None) \ 136 TARGET_ADDRESSING_MODE_LIST(V) 137 138 enum AddressingMode { 139 #define DECLARE_ADDRESSING_MODE(Name) kMode_##Name, 140 ADDRESSING_MODE_LIST(DECLARE_ADDRESSING_MODE) 141 #undef DECLARE_ADDRESSING_MODE 142 #define COUNT_ADDRESSING_MODE(Name) +1 143 kLastAddressingMode = -1 ADDRESSING_MODE_LIST(COUNT_ADDRESSING_MODE) 144 #undef COUNT_ADDRESSING_MODE 145 }; 146 147 V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream& os, 148 const AddressingMode& am); 149 150 // The mode of the flags continuation (see below). 151 enum FlagsMode { 152 kFlags_none = 0, 153 kFlags_branch = 1, 154 kFlags_deoptimize = 2, 155 kFlags_set = 3, 156 kFlags_trap = 4 157 }; 158 159 V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream& os, 160 const FlagsMode& fm); 161 162 // The condition of flags continuation (see below). 163 enum FlagsCondition { 164 kEqual, 165 kNotEqual, 166 kSignedLessThan, 167 kSignedGreaterThanOrEqual, 168 kSignedLessThanOrEqual, 169 kSignedGreaterThan, 170 kUnsignedLessThan, 171 kUnsignedGreaterThanOrEqual, 172 kUnsignedLessThanOrEqual, 173 kUnsignedGreaterThan, 174 kFloatLessThanOrUnordered, 175 kFloatGreaterThanOrEqual, 176 kFloatLessThanOrEqual, 177 kFloatGreaterThanOrUnordered, 178 kFloatLessThan, 179 kFloatGreaterThanOrEqualOrUnordered, 180 kFloatLessThanOrEqualOrUnordered, 181 kFloatGreaterThan, 182 kUnorderedEqual, 183 kUnorderedNotEqual, 184 kOverflow, 185 kNotOverflow, 186 kPositiveOrZero, 187 kNegative 188 }; 189 190 inline FlagsCondition NegateFlagsCondition(FlagsCondition condition) { 191 return static_cast<FlagsCondition>(condition ^ 1); 192 } 193 194 FlagsCondition CommuteFlagsCondition(FlagsCondition condition); 195 196 V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream& os, 197 const FlagsCondition& fc); 198 199 // The InstructionCode is an opaque, target-specific integer that encodes 200 // what code to emit for an instruction in the code generator. It is not 201 // interesting to the register allocator, as the inputs and flags on the 202 // instructions specify everything of interest. 203 typedef int32_t InstructionCode; 204 205 // Helpers for encoding / decoding InstructionCode into the fields needed 206 // for code generation. We encode the instruction, addressing mode, and flags 207 // continuation into a single InstructionCode which is stored as part of 208 // the instruction. 209 typedef BitField<ArchOpcode, 0, 9> ArchOpcodeField; 210 typedef BitField<AddressingMode, 9, 5> AddressingModeField; 211 typedef BitField<FlagsMode, 14, 3> FlagsModeField; 212 typedef BitField<FlagsCondition, 17, 5> FlagsConditionField; 213 typedef BitField<int, 22, 10> MiscField; 214 215 } // namespace compiler 216 } // namespace internal 217 } // namespace v8 218 219 #endif // V8_COMPILER_INSTRUCTION_CODES_H_ 220