1 
2 /* To compile:
3    aarch64-linux-gnu-gcc -Wall -g -O0 -o memory none/tests/arm64/memory.c
4 */
5 
6 #include <stdio.h>
7 #include <malloc.h>  // memalign
8 #include <string.h>  // memset
9 #include "tests/malloc.h"
10 #include <assert.h>
11 
12 typedef  unsigned char           UChar;
13 typedef  unsigned short int      UShort;
14 typedef  unsigned int            UInt;
15 typedef  signed int              Int;
16 typedef  unsigned char           UChar;
17 typedef  signed long long int    Long;
18 typedef  unsigned long long int  ULong;
19 
20 typedef  unsigned char           Bool;
21 #define False ((Bool)0)
22 #define True  ((Bool)1)
23 
24 static inline UChar randUChar ( void )
25 {
26    static UInt seed = 80021;
27    seed = 1103515245 * seed + 12345;
28    return (seed >> 17) & 0xFF;
29 }
30 
31 static ULong randULong ( void )
32 {
33    Int i;
34    ULong r = 0;
35    for (i = 0; i < 8; i++) {
36       r = (r << 8) | (ULong)(0xFF & randUChar());
37    }
38    return r;
39 }
40 
41 
42 // Same as TESTINST2 except it doesn't print the RN value, since
43 // that may differ between runs (it's a stack address).  Also,
44 // claim it trashes x28 so that can be used as scratch if needed.
45 #define TESTINST2_hide2(instruction, RNval, RD, RN, carryin) \
46 { \
47    ULong out; \
48    ULong nzcv_out; \
49    ULong nzcv_in = (carryin ? (1<<29) : 0); \
50    __asm__ __volatile__( \
51       "msr nzcv,%3;" \
52       "mov " #RN ",%2;" \
53       instruction ";" \
54       "mov %0," #RD ";" \
55       "mrs %1,nzcv;" \
56       : "=&r" (out), "=&r" (nzcv_out) \
57       : "r" (RNval), "r" (nzcv_in) \
58       : #RD, #RN, "cc", "memory", "x28"  \
59    ); \
60    printf("%s :: rd %016llx rn (hidden), " \
61           "cin %d, nzcv %08llx %c%c%c%c\n",       \
62       instruction, out, \
63       carryin ? 1 : 0, \
64       nzcv_out & 0xffff0000, \
65       ((1<<31) & nzcv_out) ? 'N' : ' ', \
66       ((1<<30) & nzcv_out) ? 'Z' : ' ', \
67       ((1<<29) & nzcv_out) ? 'C' : ' ', \
68       ((1<<28) & nzcv_out) ? 'V' : ' ' \
69       ); \
70 }
71 
72 #define TESTINST3_hide2and3(instruction, RMval, RNval, RD, RM, RN, carryin) \
73 { \
74    ULong out; \
75    ULong nzcv_out; \
76    ULong nzcv_in = (carryin ? (1<<29) : 0); \
77    __asm__ __volatile__( \
78       "msr nzcv,%4;" \
79       "mov " #RM ",%2;" \
80       "mov " #RN ",%3;" \
81       instruction ";" \
82       "mov %0," #RD ";" \
83       "mrs %1,nzcv;" \
84       : "=&r" (out), "=&r" (nzcv_out) \
85       : "r" (RMval), "r" (RNval), "r" (nzcv_in) \
86       : #RD, #RM, #RN, "cc", "memory" \
87    ); \
88    printf("%s :: rd %016llx rm (hidden), rn (hidden), " \
89           "cin %d, nzcv %08llx %c%c%c%c\n",       \
90       instruction, out, \
91       carryin ? 1 : 0, \
92       nzcv_out & 0xffff0000, \
93       ((1<<31) & nzcv_out) ? 'N' : ' ', \
94       ((1<<30) & nzcv_out) ? 'Z' : ' ', \
95       ((1<<29) & nzcv_out) ? 'C' : ' ', \
96       ((1<<28) & nzcv_out) ? 'V' : ' ' \
97       ); \
98 }
99 
100 
101 ////////////////////////////////////////////////////////////////
102 ////////////////////////////////////////////////////////////////
103 ////////////////////////////////////////////////////////////////
104 //                                                            //
105 // test_memory_old                                            //
106 //                                                            //
107 ////////////////////////////////////////////////////////////////
108 ////////////////////////////////////////////////////////////////
109 ////////////////////////////////////////////////////////////////
110 
111 static __attribute((noinline)) void test_memory_old ( void )
112 {
113 printf("Integer loads\n");
114 
115 unsigned char area[512];
116 
117 #define RESET \
118    do { int i; for (i = 0; i < sizeof(area); i++) \
119           area[i] = i | 0x80; \
120    } while (0)
121 
122 #define AREA_MID (((ULong)(&area[(sizeof(area)/2)-1])) & (~(ULong)0xF))
123 
124 RESET;
125 
126 ////////////////////////////////////////////////////////////////
127 printf("LDR,STR (immediate, uimm12) (STR cases are MISSING)");
128 TESTINST2_hide2("ldr  x21, [x22, #24]", AREA_MID, x21,x22,0);
129 TESTINST2_hide2("ldr  w21, [x22, #20]", AREA_MID, x21,x22,0);
130 TESTINST2_hide2("ldrh w21, [x22, #44]", AREA_MID, x21,x22,0);
131 TESTINST2_hide2("ldrb w21, [x22, #56]", AREA_MID, x21,x22,0);
132 
133 ////////////////////////////////////////////////////////////////
134 printf("LDUR,STUR (immediate, simm9) (STR cases and wb check are MISSING)\n");
135 TESTINST2_hide2("ldr x21, [x22], #-24", AREA_MID, x21,x22,0);
136 TESTINST2_hide2("ldr x21, [x22, #-40]!", AREA_MID, x21,x22,0);
137 TESTINST2_hide2("ldr x21, [x22, #-48]", AREA_MID, x21,x22,0);
138 printf("LDUR,STUR (immediate, simm9): STR cases are MISSING");
139 
140 ////////////////////////////////////////////////////////////////
141 // TESTINST2_hide2 allows use of x28 as scratch
142 printf("LDP,STP (immediate, simm7) (STR cases and wb check is MISSING)\n");
143 
144 TESTINST2_hide2("ldp x21, x28, [x22], #-24 ; add x21,x21,x28", AREA_MID, x21,x22,0);
145 TESTINST2_hide2("ldp x21, x28, [x22], #-24 ; eor x21,x21,x28", AREA_MID, x21,x22,0);
146 TESTINST2_hide2("ldp x21, x28, [x22, #-40]! ; add x21,x21,x28", AREA_MID, x21,x22,0);
147 TESTINST2_hide2("ldp x21, x28, [x22, #-40]! ; eor x21,x21,x28", AREA_MID, x21,x22,0);
148 TESTINST2_hide2("ldp x21, x28, [x22, #-40] ; add x21,x21,x28", AREA_MID, x21,x22,0);
149 TESTINST2_hide2("ldp x21, x28, [x22, #-40] ; eor x21,x21,x28", AREA_MID, x21,x22,0);
150 
151 TESTINST2_hide2("ldp w21, w28, [x22], #-24 ; add x21,x21,x28", AREA_MID, x21,x22,0);
152 TESTINST2_hide2("ldp w21, w28, [x22], #-24 ; eor x21,x21,x28", AREA_MID, x21,x22,0);
153 TESTINST2_hide2("ldp w21, w28, [x22, #-40]! ; add x21,x21,x28", AREA_MID, x21,x22,0);
154 TESTINST2_hide2("ldp w21, w28, [x22, #-40]! ; eor x21,x21,x28", AREA_MID, x21,x22,0);
155 TESTINST2_hide2("ldp w21, w28, [x22, #-40] ; add x21,x21,x28", AREA_MID, x21,x22,0);
156 TESTINST2_hide2("ldp w21, w28, [x22, #-40] ; eor x21,x21,x28", AREA_MID, x21,x22,0);
157 
158 ////////////////////////////////////////////////////////////////
159 // This is a bit tricky.  We load the value from just before and
160 // just after the actual instruction.  So we place a couple of
161 // nop insns either side of the test insn, these should "safe"
162 // to check.
163 
164 printf("LDR (literal, int reg)\n");
165 TESTINST2_hide2("nop; nop; nop; xyzzy00: ldr  x21, xyzzy00 - 8; nop; nop; nop", AREA_MID, x21,x22,0);
166 TESTINST2_hide2("nop; nop; nop; xyzzy01: ldr  x21, xyzzy01 + 0; nop; nop; nop", AREA_MID, x21,x22,0);
167 TESTINST2_hide2("nop; nop; nop; xyzzy02: ldr  x21, xyzzy02 + 8; nop; nop; nop", AREA_MID, x21,x22,0);
168 
169 TESTINST2_hide2("nop; nop; nop; xyzzy03: ldr  x21, xyzzy03 - 4; nop; nop; nop", AREA_MID, x21,x22,0);
170 TESTINST2_hide2("nop; nop; nop; xyzzy04: ldr  x21, xyzzy04 + 0; nop; nop; nop", AREA_MID, x21,x22,0);
171 TESTINST2_hide2("nop; nop; nop; xyzzy05: ldr  x21, xyzzy05 + 4; nop; nop; nop", AREA_MID, x21,x22,0);
172 
173 ////////////////////////////////////////////////////////////////
174 printf("{LD,ST}R (integer register) (entirely MISSING)\n");
175 
176 ////////////////////////////////////////////////////////////////
177 printf("LDRS{B,H,W} (uimm12)\n");
178 TESTINST2_hide2("ldrsw x21, [x22, #24]", AREA_MID, x21,x22,0);
179 TESTINST2_hide2("ldrsh x21, [x22, #20]", AREA_MID, x21,x22,0);
180 TESTINST2_hide2("ldrsh w21, [x22, #44]", AREA_MID, x21,x22,0);
181 TESTINST2_hide2("ldrsb x21, [x22, #88]", AREA_MID, x21,x22,0);
182 TESTINST2_hide2("ldrsb w21, [x22, #56]", AREA_MID, x21,x22,0);
183 
184 ////////////////////////////////////////////////////////////////
185 printf("LDRS{B,H,W} (simm9, upd) (upd check is MISSING)\n");
186 TESTINST2_hide2("ldrsw x21, [x22, #-24]!", AREA_MID, x21,x22,0);
187 TESTINST2_hide2("ldrsh x21, [x22, #-20]!", AREA_MID, x21,x22,0);
188 TESTINST2_hide2("ldrsh w21, [x22, #-44]!", AREA_MID, x21,x22,0);
189 TESTINST2_hide2("ldrsb x21, [x22, #-88]!", AREA_MID, x21,x22,0);
190 TESTINST2_hide2("ldrsb w21, [x22, #-56]!", AREA_MID, x21,x22,0);
191 
192 TESTINST2_hide2("ldrsw x21, [x22], #-24", AREA_MID, x21,x22,0);
193 TESTINST2_hide2("ldrsh x21, [x22], #-20", AREA_MID, x21,x22,0);
194 TESTINST2_hide2("ldrsh w21, [x22], #-44", AREA_MID, x21,x22,0);
195 TESTINST2_hide2("ldrsb x21, [x22], #-88", AREA_MID, x21,x22,0);
196 TESTINST2_hide2("ldrsb w21, [x22], #-56", AREA_MID, x21,x22,0);
197 
198 ////////////////////////////////////////////////////////////////
199 printf("LDRS{B,H,W} (simm9, noUpd)\n");
200 TESTINST2_hide2("ldrsw x21, [x22, #-24]", AREA_MID, x21,x22,0);
201 TESTINST2_hide2("ldrsh x21, [x22, #-20]", AREA_MID, x21,x22,0);
202 TESTINST2_hide2("ldrsh w21, [x22, #-44]", AREA_MID, x21,x22,0);
203 TESTINST2_hide2("ldrsb x21, [x22, #-88]", AREA_MID, x21,x22,0);
204 TESTINST2_hide2("ldrsb w21, [x22, #-56]", AREA_MID, x21,x22,0);
205 
206 ////////////////////////////////////////////////////////////////
207 printf("LDP,STP (immediate, simm7) (FP&VEC) (entirely MISSING)\n");
208 
209 ////////////////////////////////////////////////////////////////
210 printf("{LD,ST}R (vector register) (entirely MISSING)\n");
211 
212 ////////////////////////////////////////////////////////////////
213 printf("LDRS{B,H,W} (integer register, SX)\n");
214 
215 TESTINST3_hide2and3("ldrsw x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
216 TESTINST3_hide2and3("ldrsw x21, [x22,x23, lsl #2]", AREA_MID, 5, x21,x22,x23,0);
217 TESTINST3_hide2and3("ldrsw x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
218 TESTINST3_hide2and3("ldrsw x21, [x22,w23,uxtw #2]", AREA_MID, 5, x21,x22,x23,0);
219 TESTINST3_hide2and3("ldrsw x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
220 TESTINST3_hide2and3("ldrsw x21, [x22,w23,sxtw #2]", AREA_MID, -5ULL, x21,x22,x23,0);
221 
222 TESTINST3_hide2and3("ldrsh x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
223 TESTINST3_hide2and3("ldrsh x21, [x22,x23, lsl #1]", AREA_MID, 5, x21,x22,x23,0);
224 TESTINST3_hide2and3("ldrsh x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
225 TESTINST3_hide2and3("ldrsh x21, [x22,w23,uxtw #1]", AREA_MID, 5, x21,x22,x23,0);
226 TESTINST3_hide2and3("ldrsh x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
227 TESTINST3_hide2and3("ldrsh x21, [x22,w23,sxtw #1]", AREA_MID, -5ULL, x21,x22,x23,0);
228 
229 TESTINST3_hide2and3("ldrsh w21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
230 TESTINST3_hide2and3("ldrsh w21, [x22,x23, lsl #1]", AREA_MID, 5, x21,x22,x23,0);
231 TESTINST3_hide2and3("ldrsh w21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
232 TESTINST3_hide2and3("ldrsh w21, [x22,w23,uxtw #1]", AREA_MID, 5, x21,x22,x23,0);
233 TESTINST3_hide2and3("ldrsh w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
234 TESTINST3_hide2and3("ldrsh w21, [x22,w23,sxtw #1]", AREA_MID, -5ULL, x21,x22,x23,0);
235 
236 TESTINST3_hide2and3("ldrsb x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
237 TESTINST3_hide2and3("ldrsb x21, [x22,x23, lsl #0]", AREA_MID, 5, x21,x22,x23,0);
238 TESTINST3_hide2and3("ldrsb x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
239 TESTINST3_hide2and3("ldrsb x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
240 TESTINST3_hide2and3("ldrsb x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
241 TESTINST3_hide2and3("ldrsb x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
242 
243 TESTINST3_hide2and3("ldrsb w21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
244 TESTINST3_hide2and3("ldrsb w21, [x22,x23, lsl #0]", AREA_MID, 5, x21,x22,x23,0);
245 TESTINST3_hide2and3("ldrsb w21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
246 TESTINST3_hide2and3("ldrsb w21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
247 TESTINST3_hide2and3("ldrsb w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
248 TESTINST3_hide2and3("ldrsb w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
249 
250 ////////////////////////////////////////////////////////////////
251 printf("LDR/STR (immediate, SIMD&FP, unsigned offset) (entirely MISSING)\n");
252 
253 ////////////////////////////////////////////////////////////////
254 printf("LDR/STR (immediate, SIMD&FP, pre/post index) (entirely MISSING)\n");
255 
256 ////////////////////////////////////////////////////////////////
257 printf("LDUR/STUR (unscaled offset, SIMD&FP) (entirely MISSING)\n");
258 
259 ////////////////////////////////////////////////////////////////
260 printf("LDR (literal, SIMD&FP) (entirely MISSING)\n");
261 
262 ////////////////////////////////////////////////////////////////
263 printf("LD1/ST1 (single structure, no offset) (entirely MISSING)\n");
264 
265 ////////////////////////////////////////////////////////////////
266 printf("LD1/ST1 (single structure, post index) (entirely MISSING)\n");
267 
268 ////////////////////////////////////////////////////////////////
269 printf("LD{,A}X{R,RH,RB} (entirely MISSING)\n");
270 
271 ////////////////////////////////////////////////////////////////
272 printf("ST{,L}X{R,RH,RB} (entirely MISSING)\n");
273 
274 ////////////////////////////////////////////////////////////////
275 printf("LDA{R,RH,RB}\n");
276 TESTINST2_hide2("ldar  x21, [x22]", AREA_MID, x21,x22,0);
277 TESTINST2_hide2("ldar  w21, [x22]", AREA_MID, x21,x22,0);
278 TESTINST2_hide2("ldarh w21, [x22]", AREA_MID, x21,x22,0);
279 TESTINST2_hide2("ldarb w21, [x22]", AREA_MID, x21,x22,0);
280 
281 ////////////////////////////////////////////////////////////////
282 printf("STL{R,RH,RB} (entirely MISSING)\n");
283 
284 ////////////////////////////////////////////////////////////////
285 // TESTINST2_hide2 allows use of x28 as scratch
286 printf("LDPSW (immediate, simm7)\n");
287 
288 TESTINST2_hide2("ldpsw x21, x28, [x22], #-24 ; add x21,x21,x28", AREA_MID, x21,x22,0);
289 TESTINST2_hide2("ldpsw x21, x28, [x22], #-24 ; eor x21,x21,x28", AREA_MID, x21,x22,0);
290 TESTINST2_hide2("ldpsw x21, x28, [x22, #-40]! ; add x21,x21,x28", AREA_MID, x21,x22,0);
291 TESTINST2_hide2("ldpsw x21, x28, [x22, #-40]! ; eor x21,x21,x28", AREA_MID, x21,x22,0);
292 TESTINST2_hide2("ldpsw x21, x28, [x22, #-40] ; add x21,x21,x28", AREA_MID, x21,x22,0);
293 TESTINST2_hide2("ldpsw x21, x28, [x22, #-40] ; eor x21,x21,x28", AREA_MID, x21,x22,0);
294 
295 } /* end of test_memory_old() */
296 
297 
298 ////////////////////////////////////////////////////////////////
299 ////////////////////////////////////////////////////////////////
300 ////////////////////////////////////////////////////////////////
301 //                                                            //
302 // test_memory_new                                            //
303 //                                                            //
304 ////////////////////////////////////////////////////////////////
305 ////////////////////////////////////////////////////////////////
306 ////////////////////////////////////////////////////////////////
307 
308 static void show_block_xor ( UChar* block1, UChar* block2, Int n )
309 {
310    Int i;
311    printf("  ");
312    for (i = 0; i < n; i++) {
313       if (i > 0 && 0 == (i & 15)) printf("\n  ");
314       if (0 == (i & 15)) printf("[%3d]  ", i);
315       UInt diff = 0xFF & (UInt)(block1[i] - block2[i]);
316       if (diff == 0)
317          printf(".. ");
318       else
319          printf("%02x ", diff);
320    }
321    printf("\n");
322 }
323 
324 
325 // In: rand:
326 //       memory area, xferred vec regs, xferred int regs,
327 //     caller spec:
328 //       addr reg1, addr reg2
329 //
330 // Out: memory area, xferred vec regs, xferred int regs, addr reg1, addr reg2
331 //
332 // INSN may mention the following regs as containing load/store data:
333 //     x13 x23 v17 v18 v19 v20
334 // and
335 //     x5 as containing the base address
336 //     x6 as containing an offset, if required
337 // A memory area is filled with random data, and x13, x23, v17, v18, v19, v20
338 // are loaded with random data too.  INSN is then executed, with
339 // x5 set to the middle of the memory area + AREG1OFF, and x6 set to AREG2VAL.
340 //
341 // What is printed out: the XOR of the new and old versions of the
342 // following:
343 //    the memory area
344 //    x13 x23 v17 v18 v19 v20
345 // and the SUB of the new and old values of the following:
346 //    x5 x6
347 // If the insn modifies its base register then (obviously) the x5 "new - old"
348 // value will be nonzero.
349 
350 #define MEM_TEST(INSN, AREG1OFF, AREG2VAL) { \
351   int i; \
352   const int N = 256; \
353   UChar* area = memalign16(N); \
354   UChar area2[N]; \
355   for (i = 0; i < N; i++) area[i] = area2[i] = randUChar(); \
356   ULong block[12]; \
357   /* 0:x13      1:x23      2:v17.d[0] 3:v17.d[1] 4:v18.d[0] 5:v18.d[1] */ \
358   /* 6:v19.d[0] 7:v19.d[1] 8:v20.d[0] 9:v20.d[1] 10:x5      11:x6 */ \
359   for (i = 0; i < 12; i++) block[i] = randULong(); \
360   block[10] = (ULong)(&area[128]) + (Long)(Int)AREG1OFF; \
361   block[11] = (Long)AREG2VAL; \
362   ULong block2[12]; \
363   for (i = 0; i < 12; i++) block2[i] = block[i]; \
364   __asm__ __volatile__( \
365   "ldr x13, [%0, #0]  ; " \
366   "ldr x23, [%0, #8]  ; " \
367   "ldr q17, [%0, #16] ; " \
368   "ldr q18, [%0, #32] ; " \
369   "ldr q19, [%0, #48] ; " \
370   "ldr q20, [%0, #64] ; " \
371   "ldr x5,  [%0, #80] ; " \
372   "ldr x6,  [%0, #88] ; " \
373   INSN " ; " \
374   "str x13, [%0, #0]  ; " \
375   "str x23, [%0, #8]  ; " \
376   "str q17, [%0, #16] ; " \
377   "str q18, [%0, #32] ; " \
378   "str q19, [%0, #48] ; " \
379   "str q20, [%0, #64] ; " \
380   "str x5,  [%0, #80] ; " \
381   "str x6,  [%0, #88] ; " \
382   : : "r"(&block[0]) : "x5", "x6", "x13", "x23", \
383                        "v17", "v18", "v19", "v20", "memory", "cc" \
384   ); \
385   printf("%s  with  x5 = middle_of_block+%lld,  x6=%lld\n", \
386          INSN, (Long)AREG1OFF, (Long)AREG2VAL); \
387   show_block_xor(&area2[0], area, 256); \
388   printf("  %016llx  x13      (xor, xfer intreg #1)\n", block[0] ^ block2[0]); \
389   printf("  %016llx  x23      (xor, xfer intreg #2)\n", block[1] ^ block2[1]); \
390   printf("  %016llx  v17.d[0] (xor, xfer vecreg #1)\n", block[2] ^ block2[2]); \
391   printf("  %016llx  v17.d[1] (xor, xfer vecreg #1)\n", block[3] ^ block2[3]); \
392   printf("  %016llx  v18.d[0] (xor, xfer vecreg #2)\n", block[4] ^ block2[4]); \
393   printf("  %016llx  v18.d[1] (xor, xfer vecreg #2)\n", block[5] ^ block2[5]); \
394   printf("  %016llx  v19.d[0] (xor, xfer vecreg #3)\n", block[6] ^ block2[6]); \
395   printf("  %016llx  v19.d[1] (xor, xfer vecreg #3)\n", block[7] ^ block2[7]); \
396   printf("  %016llx  v20.d[0] (xor, xfer vecreg #3)\n", block[8] ^ block2[8]); \
397   printf("  %016llx  v20.d[1] (xor, xfer vecreg #3)\n", block[9] ^ block2[9]); \
398   printf("  %16lld  x5       (sub, base reg)\n",     block[10] - block2[10]); \
399   printf("  %16lld  x6       (sub, index reg)\n",    block[11] - block2[11]); \
400   printf("\n"); \
401   free(area); \
402   }
403 
404 
405 static __attribute__((noinline)) void test_memory_new ( void )
406 {
407 ////////////////////////////////////////////////////////////////
408 printf("LDR,STR (immediate, uimm12)");
409 MEM_TEST("ldr  x13, [x5, #24]", -1, 0);
410 MEM_TEST("ldr  w13, [x5, #20]", 1, 0);
411 MEM_TEST("ldrh w13, [x5, #44]", 2, 0);
412 MEM_TEST("ldrb w13, [x5, #56]", 3, 0);
413 MEM_TEST("str  x13, [x5, #24]", -3, 0);
414 MEM_TEST("str  w13, [x5, #20]", 5, 0);
415 MEM_TEST("strh w13, [x5, #44]", 6, 0);
416 MEM_TEST("strb w13, [x5, #56]", 7, 0);
417 
418 ////////////////////////////////////////////////////////////////
419 printf("LDUR,STUR (immediate, simm9)\n");
420 MEM_TEST("ldr x13, [x5], #-24",  0, 0);
421 MEM_TEST("ldr x13, [x5, #-40]!", 0, 0);
422 MEM_TEST("ldr x13, [x5, #-48]",  0, 0);
423 MEM_TEST("str x13, [x5], #-24",  0, 0);
424 MEM_TEST("str x13, [x5, #-40]!", 0, 0);
425 MEM_TEST("str x13, [x5, #-48]",  0, 0);
426 
427 ////////////////////////////////////////////////////////////////
428 printf("LDP,STP (immediate, simm7)\n");
429 MEM_TEST("ldp x13, x23, [x5], #-24",   0, 0);
430 MEM_TEST("ldp x13, x23, [x5, #-40]!",  0, 0);
431 MEM_TEST("ldp x13, x23, [x5, #-40]",   0, 0);
432 MEM_TEST("stp x13, x23, [x5], #-24",   0, 0);
433 MEM_TEST("stp x13, x23, [x5, #-40]!",  0, 0);
434 MEM_TEST("stp x13, x23, [x5, #-40]",   0, 0);
435 
436 MEM_TEST("ldp w13, w23, [x5], #-24",   0, 0);
437 MEM_TEST("ldp w13, w23, [x5, #-40]!",  0, 0);
438 MEM_TEST("ldp w13, w23, [x5, #-40]",   0, 0);
439 MEM_TEST("stp w13, w23, [x5], #-24",   0, 0);
440 MEM_TEST("stp w13, w23, [x5, #-40]!",  0, 0);
441 MEM_TEST("stp w13, w23, [x5, #-40]",   0, 0);
442 
443 ////////////////////////////////////////////////////////////////
444 printf("LDR (literal, int reg) (done above by test_memory_old)\n");
445 
446 ////////////////////////////////////////////////////////////////
447 printf("{LD,ST}R (integer register)\n");
448 MEM_TEST("str x13, [x5, x6]",          12, -4);
449 MEM_TEST("str x13, [x5, x6, lsl #3]",  12, -4);
450 MEM_TEST("str x13, [x5, w6, uxtw]",    12,  4);
451 MEM_TEST("str x13, [x5, w6, uxtw #3]", 12,  4);
452 MEM_TEST("str x13, [x5, w6, sxtw]",    12,  4);
453 MEM_TEST("str x13, [x5, w6, sxtw #3]", 12,  -4);
454 MEM_TEST("ldr x13, [x5, x6]",          12, -4);
455 MEM_TEST("ldr x13, [x5, x6, lsl #3]",  12, -4);
456 MEM_TEST("ldr x13, [x5, w6, uxtw]",    12,  4);
457 MEM_TEST("ldr x13, [x5, w6, uxtw #3]", 12,  4);
458 MEM_TEST("ldr x13, [x5, w6, sxtw]",    12,  4);
459 MEM_TEST("ldr x13, [x5, w6, sxtw #3]", 12,  -4);
460 
461 MEM_TEST("str w13, [x5, x6]",          12, -4);
462 MEM_TEST("str w13, [x5, x6, lsl #2]",  12, -4);
463 MEM_TEST("str w13, [x5, w6, uxtw]",    12,  4);
464 MEM_TEST("str w13, [x5, w6, uxtw #2]", 12,  4);
465 MEM_TEST("str w13, [x5, w6, sxtw]",    12,  4);
466 MEM_TEST("str w13, [x5, w6, sxtw #2]", 12,  -4);
467 MEM_TEST("ldr w13, [x5, x6]",          12, -4);
468 MEM_TEST("ldr w13, [x5, x6, lsl #2]",  12, -4);
469 MEM_TEST("ldr w13, [x5, w6, uxtw]",    12,  4);
470 MEM_TEST("ldr w13, [x5, w6, uxtw #2]", 12,  4);
471 MEM_TEST("ldr w13, [x5, w6, sxtw]",    12,  4);
472 MEM_TEST("ldr w13, [x5, w6, sxtw #2]", 12,  -4);
473 
474 MEM_TEST("strh w13, [x5, x6]",          12, -4);
475 MEM_TEST("strh w13, [x5, x6, lsl #1]",  12, -4);
476 MEM_TEST("strh w13, [x5, w6, uxtw]",    12,  4);
477 MEM_TEST("strh w13, [x5, w6, uxtw #1]", 12,  4);
478 MEM_TEST("strh w13, [x5, w6, sxtw]",    12,  4);
479 MEM_TEST("strh w13, [x5, w6, sxtw #1]", 12,  -4);
480 MEM_TEST("ldrh w13, [x5, x6]",          12, -4);
481 MEM_TEST("ldrh w13, [x5, x6, lsl #1]",  12, -4);
482 MEM_TEST("ldrh w13, [x5, w6, uxtw]",    12,  4);
483 MEM_TEST("ldrh w13, [x5, w6, uxtw #1]", 12,  4);
484 MEM_TEST("ldrh w13, [x5, w6, sxtw]",    12,  4);
485 MEM_TEST("ldrh w13, [x5, w6, sxtw #1]", 12,  -4);
486 
487 MEM_TEST("strb w13, [x5, x6]",          12, -4);
488 MEM_TEST("strb w13, [x5, x6, lsl #0]",  12, -4);
489 MEM_TEST("strb w13, [x5, w6, uxtw]",    12,  4);
490 MEM_TEST("strb w13, [x5, w6, uxtw #0]", 12,  4);
491 MEM_TEST("strb w13, [x5, w6, sxtw]",    12,  4);
492 MEM_TEST("strb w13, [x5, w6, sxtw #0]", 12,  -4);
493 MEM_TEST("ldrb w13, [x5, x6]",          12, -4);
494 MEM_TEST("ldrb w13, [x5, x6, lsl #0]",  12, -4);
495 MEM_TEST("ldrb w13, [x5, w6, uxtw]",    12,  4);
496 MEM_TEST("ldrb w13, [x5, w6, uxtw #0]", 12,  4);
497 MEM_TEST("ldrb w13, [x5, w6, sxtw]",    12,  4);
498 MEM_TEST("ldrb w13, [x5, w6, sxtw #0]", 12,  -4);
499 
500 ////////////////////////////////////////////////////////////////
501 printf("LDRS{B,H,W} (uimm12)\n");
502 MEM_TEST("ldrsw x13, [x5, #24]", -16, 4);
503 MEM_TEST("ldrsh x13, [x5, #20]", -16, 4);
504 MEM_TEST("ldrsh w13, [x5, #44]", -16, 4);
505 MEM_TEST("ldrsb x13, [x5, #72]", -16, 4);
506 MEM_TEST("ldrsb w13, [x5, #56]", -16, 4);
507 
508 ////////////////////////////////////////////////////////////////
509 printf("LDRS{B,H,W} (simm9, upd)\n");
510 MEM_TEST("ldrsw x13, [x5, #-24]!", -16, 4);
511 MEM_TEST("ldrsh x13, [x5, #-20]!", -16, 4);
512 MEM_TEST("ldrsh w13, [x5, #-44]!", -16, 4);
513 MEM_TEST("ldrsb x13, [x5, #-72]!", -16, 4);
514 MEM_TEST("ldrsb w13, [x5, #-56]!", -16, 4);
515 
516 MEM_TEST("ldrsw x13, [x5], #-24", -16, 4);
517 MEM_TEST("ldrsh x13, [x5], #-20", -16, 4);
518 MEM_TEST("ldrsh w13, [x5], #-44", -16, 4);
519 MEM_TEST("ldrsb x13, [x5], #-72", -16, 4);
520 MEM_TEST("ldrsb w13, [x5], #-56", -16, 4);
521 
522 ////////////////////////////////////////////////////////////////
523 printf("LDRS{B,H,W} (simm9, noUpd)\n");
524 MEM_TEST("ldrsw x13, [x5, #-24]", -16, 4);
525 MEM_TEST("ldrsh x13, [x5, #-20]", -16, 4);
526 MEM_TEST("ldrsh w13, [x5, #-44]", -16, 4);
527 MEM_TEST("ldrsb x13, [x5, #-72]", -16, 4);
528 MEM_TEST("ldrsb w13, [x5, #-56]", -16, 4);
529 
530 ////////////////////////////////////////////////////////////////
531 printf("LDP,STP (immediate, simm7) (FP&VEC)\n");
532 
533 MEM_TEST("stp q17, q18, [x5, 16]",  -15, 4);
534 MEM_TEST("stp q19, q18, [x5, 32]!", -11, 4);
535 MEM_TEST("stp q20, q17, [x5], -48",  -7, 4);
536 
537 MEM_TEST("stp d18, d17, [x5, 16]",  -15, 4);
538 MEM_TEST("stp d17, d19, [x5, 32]!", -11, 4);
539 MEM_TEST("stp d20, d18, [x5], -48",  -7, 4);
540 
541 MEM_TEST("stp s17, s18, [x5, 16]",  -15, 4);
542 MEM_TEST("stp s19, s18, [x5, 32]!", -11, 4);
543 MEM_TEST("stp s20, s17, [x5], -48", -7, 4);
544 
545 MEM_TEST("ldp q17, q18, [x5, 16]",  -15, 4);
546 MEM_TEST("ldp q18, q19, [x5, 32]!", -11, 4);
547 MEM_TEST("ldp q19, q20, [x5], -48",  -7, 4);
548 
549 MEM_TEST("ldp d20, d17, [x5, 16]",  -15, 4);
550 MEM_TEST("ldp d17, d18, [x5, 32]!", -11, 4);
551 MEM_TEST("ldp d18, d19, [x5], -48", -7, 4);
552 
553 MEM_TEST("ldp s19, s20, [x5, 16]",  -15, 4);
554 MEM_TEST("ldp s20, s17, [x5, 32]!", -11, 4);
555 MEM_TEST("ldp s17, s18, [x5], -48", -7, 4);
556 
557 ////////////////////////////////////////////////////////////////
558 printf("LDNP,STNP (immediate, simm7) (FP&VEC, w/ nontemporal hint)\n");
559 
560 MEM_TEST("stnp q18, q17, [x5, 16]",  -15, 4);
561 MEM_TEST("stnp d20, d19, [x5, 40]",  -15, 4);
562 MEM_TEST("stnp s19, s18, [x5, 68]",  -15, 4);
563 
564 MEM_TEST("ldnp q18, q17, [x5, 16]",  -15, 4);
565 MEM_TEST("ldnp d17, d20, [x5, 40]",  -15, 4);
566 MEM_TEST("ldnp s20, s19, [x5, 68]",  -15, 4);
567 
568 ////////////////////////////////////////////////////////////////
569 printf("{LD,ST}R (vector register)\n");
570 
571 MEM_TEST("str q17, [x5, x6]",          12, -4);
572 MEM_TEST("str q17, [x5, x6, lsl #4]",  12, -4);
573 MEM_TEST("str q17, [x5, w6, uxtw]",    12,  4);
574 MEM_TEST("str q17, [x5, w6, uxtw #4]", 12,  4);
575 MEM_TEST("str q17, [x5, w6, sxtw]",    12,  4);
576 MEM_TEST("str q17, [x5, w6, sxtw #4]", 12,  -4);
577 MEM_TEST("ldr q17, [x5, x6]",          12, -4);
578 MEM_TEST("ldr q17, [x5, x6, lsl #4]",  12, -4);
579 MEM_TEST("ldr q17, [x5, w6, uxtw]",    12,  4);
580 MEM_TEST("ldr q17, [x5, w6, uxtw #4]", 12,  4);
581 MEM_TEST("ldr q17, [x5, w6, sxtw]",    12,  4);
582 MEM_TEST("ldr q17, [x5, w6, sxtw #4]", 12,  -4);
583 
584 MEM_TEST("str d17, [x5, x6]",          12, -4);
585 MEM_TEST("str d17, [x5, x6, lsl #3]",  12, -4);
586 MEM_TEST("str d17, [x5, w6, uxtw]",    12,  4);
587 MEM_TEST("str d17, [x5, w6, uxtw #3]", 12,  4);
588 MEM_TEST("str d17, [x5, w6, sxtw]",    12,  4);
589 MEM_TEST("str d17, [x5, w6, sxtw #3]", 12,  -4);
590 MEM_TEST("ldr d17, [x5, x6]",          12, -4);
591 MEM_TEST("ldr d17, [x5, x6, lsl #3]",  12, -4);
592 MEM_TEST("ldr d17, [x5, w6, uxtw]",    12,  4);
593 MEM_TEST("ldr d17, [x5, w6, uxtw #3]", 12,  4);
594 MEM_TEST("ldr d17, [x5, w6, sxtw]",    12,  4);
595 MEM_TEST("ldr d17, [x5, w6, sxtw #3]", 12,  -4);
596 
597 MEM_TEST("str s17, [x5, x6]",          12, -4);
598 MEM_TEST("str s17, [x5, x6, lsl #2]",  12, -4);
599 MEM_TEST("str s17, [x5, w6, uxtw]",    12,  4);
600 MEM_TEST("str s17, [x5, w6, uxtw #2]", 12,  4);
601 MEM_TEST("str s17, [x5, w6, sxtw]",    12,  4);
602 MEM_TEST("str s17, [x5, w6, sxtw #2]", 12,  -4);
603 MEM_TEST("ldr s17, [x5, x6]",          12, -4);
604 MEM_TEST("ldr s17, [x5, x6, lsl #2]",  12, -4);
605 MEM_TEST("ldr s17, [x5, w6, uxtw]",    12,  4);
606 MEM_TEST("ldr s17, [x5, w6, uxtw #2]", 12,  4);
607 MEM_TEST("ldr s17, [x5, w6, sxtw]",    12,  4);
608 MEM_TEST("ldr s17, [x5, w6, sxtw #2]", 12,  -4);
609 
610 MEM_TEST("str h17, [x5, x6]",          12, -4);
611 MEM_TEST("str h17, [x5, x6, lsl #1]",  12, -4);
612 MEM_TEST("str h17, [x5, w6, uxtw]",    12,  4);
613 MEM_TEST("str h17, [x5, w6, uxtw #1]", 12,  4);
614 MEM_TEST("str h17, [x5, w6, sxtw]",    12,  4);
615 MEM_TEST("str h17, [x5, w6, sxtw #1]", 12,  -4);
616 MEM_TEST("ldr h17, [x5, x6]",          12, -4);
617 MEM_TEST("ldr h17, [x5, x6, lsl #1]",  12, -4);
618 MEM_TEST("ldr h17, [x5, w6, uxtw]",    12,  4);
619 MEM_TEST("ldr h17, [x5, w6, uxtw #1]", 12,  4);
620 MEM_TEST("ldr h17, [x5, w6, sxtw]",    12,  4);
621 MEM_TEST("ldr h17, [x5, w6, sxtw #1]", 12,  -4);
622 
623 MEM_TEST("str b17, [x5, x6]",          12, -4);
624 MEM_TEST("str b17, [x5, x6, lsl #0]",  12, -4);
625 MEM_TEST("str b17, [x5, w6, uxtw]",    12,  4);
626 MEM_TEST("str b17, [x5, w6, uxtw #0]", 12,  4);
627 MEM_TEST("str b17, [x5, w6, sxtw]",    12,  4);
628 MEM_TEST("str b17, [x5, w6, sxtw #0]", 12,  -4);
629 MEM_TEST("ldr b17, [x5, x6]",          12, -4);
630 MEM_TEST("ldr b17, [x5, x6, lsl #0]",  12, -4);
631 MEM_TEST("ldr b17, [x5, w6, uxtw]",    12,  4);
632 MEM_TEST("ldr b17, [x5, w6, uxtw #0]", 12,  4);
633 MEM_TEST("ldr b17, [x5, w6, sxtw]",    12,  4);
634 MEM_TEST("ldr b17, [x5, w6, sxtw #0]", 12,  -4);
635 
636 ////////////////////////////////////////////////////////////////
637 printf("LDRS{B,H,W} (integer register, SX)\n");
638 
639 MEM_TEST("ldrsw x13, [x5,x6]", 12, -4);
640 MEM_TEST("ldrsw x13, [x5,x6, lsl #2]", 12, -4);
641 MEM_TEST("ldrsw x13, [x5,w6,uxtw #0]", 12, 4);
642 MEM_TEST("ldrsw x13, [x5,w6,uxtw #2]", 12, 4);
643 MEM_TEST("ldrsw x13, [x5,w6,sxtw #0]", 12, 4);
644 MEM_TEST("ldrsw x13, [x5,w6,sxtw #2]", 12, -4);
645 
646 MEM_TEST("ldrsh x13, [x5,x6]",  12, -4);
647 MEM_TEST("ldrsh x13, [x5,x6, lsl #1]",  12, -4);
648 MEM_TEST("ldrsh x13, [x5,w6,uxtw #0]", 12, 4);
649 MEM_TEST("ldrsh x13, [x5,w6,uxtw #1]", 12, 4);
650 MEM_TEST("ldrsh x13, [x5,w6,sxtw #0]", 12, 4);
651 MEM_TEST("ldrsh x13, [x5,w6,sxtw #1]",  12, -4);
652 
653 MEM_TEST("ldrsh w13, [x5,x6]",  12, -4);
654 MEM_TEST("ldrsh w13, [x5,x6, lsl #1]",  12, -4);
655 MEM_TEST("ldrsh w13, [x5,w6,uxtw #0]", 12, 4);
656 MEM_TEST("ldrsh w13, [x5,w6,uxtw #1]", 12, 4);
657 MEM_TEST("ldrsh w13, [x5,w6,sxtw #0]", 12, 4);
658 MEM_TEST("ldrsh w13, [x5,w6,sxtw #1]",  12, -4);
659 
660 MEM_TEST("ldrsb x13, [x5,x6]",  12, -4);
661 MEM_TEST("ldrsb x13, [x5,x6, lsl #0]",  12, -4);
662 MEM_TEST("ldrsb x13, [x5,w6,uxtw #0]", 12, 4);
663 MEM_TEST("ldrsb x13, [x5,w6,uxtw #0]", 12, 4);
664 MEM_TEST("ldrsb x13, [x5,w6,sxtw #0]", 12, 4);
665 MEM_TEST("ldrsb x13, [x5,w6,sxtw #0]",  12, -4);
666 
667 MEM_TEST("ldrsb w13, [x5,x6]",  12, -4);
668 MEM_TEST("ldrsb w13, [x5,x6, lsl #0]",  12, -4);
669 MEM_TEST("ldrsb w13, [x5,w6,uxtw #0]", 12, 4);
670 MEM_TEST("ldrsb w13, [x5,w6,uxtw #0]", 12, 4);
671 MEM_TEST("ldrsb w13, [x5,w6,sxtw #0]", 12, 4);
672 MEM_TEST("ldrsb w13, [x5,w6,sxtw #0]",  12, -4);
673 
674 ////////////////////////////////////////////////////////////////
675 printf("LDR/STR (immediate, SIMD&FP, unsigned offset)\n");
676 
677 MEM_TEST("str q17, [x5, #-32]", 16, 0);
678 MEM_TEST("str d17, [x5, #-32]", 16, 0);
679 MEM_TEST("str s17, [x5, #-32]", 16, 0);
680 MEM_TEST("str h17, [x5, #-32]", 16, 0);
681 MEM_TEST("str b17, [x5, #-32]", 16, 0);
682 MEM_TEST("ldr q17, [x5, #-32]", 16, 0);
683 MEM_TEST("ldr d17, [x5, #-32]", 16, 0);
684 MEM_TEST("ldr s17, [x5, #-32]", 16, 0);
685 MEM_TEST("ldr h17, [x5, #-32]", 16, 0);
686 MEM_TEST("ldr b17, [x5, #-32]", 16, 0);
687 
688 ////////////////////////////////////////////////////////////////
689 printf("LDR/STR (immediate, SIMD&FP, pre/post index)\n");
690 
691 MEM_TEST("str q17, [x5], #-32", 16, 0);
692 MEM_TEST("str d17, [x5], #-32", 16, 0);
693 MEM_TEST("str s17, [x5], #-32", 16, 0);
694 MEM_TEST("str h17, [x5], #-32", 16, 0);
695 MEM_TEST("str b17, [x5], #-32", 16, 0);
696 MEM_TEST("ldr q17, [x5], #-32", 16, 0);
697 MEM_TEST("ldr d17, [x5], #-32", 16, 0);
698 MEM_TEST("ldr s17, [x5], #-32", 16, 0);
699 MEM_TEST("ldr h17, [x5], #-32", 16, 0);
700 MEM_TEST("ldr b17, [x5], #-32", 16, 0);
701 
702 MEM_TEST("str q17, [x5, #-32]!", 16, 0);
703 MEM_TEST("str d17, [x5, #-32]!", 16, 0);
704 MEM_TEST("str s17, [x5, #-32]!", 16, 0);
705 MEM_TEST("str h17, [x5, #-32]!", 16, 0);
706 MEM_TEST("str b17, [x5, #-32]!", 16, 0);
707 MEM_TEST("ldr q17, [x5, #-32]!", 16, 0);
708 MEM_TEST("ldr d17, [x5, #-32]!", 16, 0);
709 MEM_TEST("ldr s17, [x5, #-32]!", 16, 0);
710 MEM_TEST("ldr h17, [x5, #-32]!", 16, 0);
711 MEM_TEST("ldr b17, [x5, #-32]!", 16, 0);
712 
713 ////////////////////////////////////////////////////////////////
714 printf("LDUR/STUR (unscaled offset, SIMD&FP)\n");
715 
716 MEM_TEST("str q17, [x5, #-13]", 16, 0);
717 MEM_TEST("str d17, [x5, #-13]", 16, 0);
718 MEM_TEST("str s17, [x5, #-13]", 16, 0);
719 MEM_TEST("str h17, [x5, #-13]", 16, 0);
720 MEM_TEST("str b17, [x5, #-13]", 16, 0);
721 MEM_TEST("ldr q17, [x5, #-13]", 16, 0);
722 MEM_TEST("ldr d17, [x5, #-13]", 16, 0);
723 MEM_TEST("ldr s17, [x5, #-13]", 16, 0);
724 MEM_TEST("ldr h17, [x5, #-13]", 16, 0);
725 MEM_TEST("ldr b17, [x5, #-13]", 16, 0);
726 
727 ////////////////////////////////////////////////////////////////
728 printf("LDR (literal, SIMD&FP) (entirely MISSING)\n");
729 
730 MEM_TEST("xyzzy10: ldr s17, xyzzy10 - 8", 0, 0)
731 MEM_TEST("xyzzy11: ldr d17, xyzzy11 + 8", 0, 0)
732 MEM_TEST("xyzzy12: ldr q17, xyzzy12 + 4", 0, 0)
733 
734 ////////////////////////////////////////////////////////////////
735 printf("LD1/ST1 (multiple 1-elem structs to/from 1 reg\n");
736 
737 MEM_TEST("st1 {v18.2d}, [x5]",       17, 7)
738 MEM_TEST("st1 {v18.2d}, [x5], #16",  9, 9)
739 MEM_TEST("st1 {v18.2d}, [x5], x6",   -13, -5)
740 
741 MEM_TEST("st1 {v18.1d}, [x5]",       17, 7)
742 MEM_TEST("st1 {v18.1d}, [x5], #8",   9, 9)
743 MEM_TEST("st1 {v18.1d}, [x5], x6",   -13, -5)
744 
745 MEM_TEST("st1 {v18.4s}, [x5]",       17, 7)
746 MEM_TEST("st1 {v18.4s}, [x5], #16",  9, 9)
747 MEM_TEST("st1 {v18.4s}, [x5], x6",   -13, -5)
748 
749 MEM_TEST("st1 {v18.2s}, [x5]",       17, 7)
750 MEM_TEST("st1 {v18.2s}, [x5], #8",   9, 9)
751 MEM_TEST("st1 {v18.2s}, [x5], x6",   -13, -5)
752 
753 MEM_TEST("st1 {v18.8h}, [x5]",       17, 7)
754 MEM_TEST("st1 {v18.8h}, [x5], #16",  9, 9)
755 MEM_TEST("st1 {v18.8h}, [x5], x6",   -13, -5)
756 
757 MEM_TEST("st1 {v18.4h}, [x5]",       17, 7)
758 MEM_TEST("st1 {v18.4h}, [x5], #8",   9, 9)
759 MEM_TEST("st1 {v18.4h}, [x5], x6",   -13, -5)
760 
761 MEM_TEST("st1 {v18.16b}, [x5]",      17, 7)
762 MEM_TEST("st1 {v18.16b}, [x5], #16", 9, 9)
763 MEM_TEST("st1 {v18.16b}, [x5], x6",  -13, -5)
764 
765 MEM_TEST("st1 {v18.8b}, [x5]",       17, 7)
766 MEM_TEST("st1 {v18.8b}, [x5], #8",   9, 9)
767 MEM_TEST("st1 {v18.8b}, [x5], x6",   -13, -5)
768 
769 MEM_TEST("ld1 {v18.2d}, [x5]",       17, 7)
770 MEM_TEST("ld1 {v18.2d}, [x5], #16",  9, 9)
771 MEM_TEST("ld1 {v18.2d}, [x5], x6",   -13, -5)
772 
773 MEM_TEST("ld1 {v18.1d}, [x5]",       17, 7)
774 MEM_TEST("ld1 {v18.1d}, [x5], #8",   9, 9)
775 MEM_TEST("ld1 {v18.1d}, [x5], x6",   -13, -5)
776 
777 MEM_TEST("ld1 {v18.4s}, [x5]",       17, 7)
778 MEM_TEST("ld1 {v18.4s}, [x5], #16",  9, 9)
779 MEM_TEST("ld1 {v18.4s}, [x5], x6",   -13, -5)
780 
781 MEM_TEST("ld1 {v18.2s}, [x5]",       17, 7)
782 MEM_TEST("ld1 {v18.2s}, [x5], #8",   9, 9)
783 MEM_TEST("ld1 {v18.2s}, [x5], x6",   -13, -5)
784 
785 MEM_TEST("ld1 {v18.8h}, [x5]",       17, 7)
786 MEM_TEST("ld1 {v18.8h}, [x5], #16",  9, 9)
787 MEM_TEST("ld1 {v18.8h}, [x5], x6",   -13, -5)
788 
789 MEM_TEST("ld1 {v18.4h}, [x5]",       17, 7)
790 MEM_TEST("ld1 {v18.4h}, [x5], #8",   9, 9)
791 MEM_TEST("ld1 {v18.4h}, [x5], x6",   -13, -5)
792 
793 MEM_TEST("ld1 {v18.16b}, [x5]",      17, 7)
794 MEM_TEST("ld1 {v18.16b}, [x5], #16", 9, 9)
795 MEM_TEST("ld1 {v18.16b}, [x5], x6",  -13, -5)
796 
797 MEM_TEST("ld1 {v18.8b}, [x5]",       17, 7)
798 MEM_TEST("ld1 {v18.8b}, [x5], #8",   9, 9)
799 MEM_TEST("ld1 {v18.8b}, [x5], x6",   -13, -5)
800 
801 ////////////////////////////////////////////////////////////////
802 printf("LD2/ST2 (multiple 2-elem structs to/from 2 regs\n");
803 
804 MEM_TEST("st2 {v18.2d, v19.2d}, [x5]",         17, 7)
805 MEM_TEST("st2 {v18.2d, v19.2d}, [x5], #32",    9, 9)
806 MEM_TEST("st2 {v18.2d, v19.2d}, [x5], x6",     -13, -5)
807 
808 /* no 1d case */
809 
810 MEM_TEST("st2 {v18.4s, v19.4s}, [x5]",         17, 7)
811 MEM_TEST("st2 {v18.4s, v19.4s}, [x5], #32",    9, 9)
812 MEM_TEST("st2 {v18.4s, v19.4s}, [x5], x6",     -13, -5)
813 
814 MEM_TEST("st2 {v18.2s, v19.2s}, [x5]",         17, 7)
815 MEM_TEST("st2 {v18.2s, v19.2s}, [x5], #16",    9, 9)
816 MEM_TEST("st2 {v18.2s, v19.2s}, [x5], x6",     -13, -5)
817 
818 MEM_TEST("st2 {v18.8h, v19.8h}, [x5]",         17, 7)
819 MEM_TEST("st2 {v18.8h, v19.8h}, [x5], #32",    9, 9)
820 MEM_TEST("st2 {v18.8h, v19.8h}, [x5], x6",     -13, -5)
821 
822 MEM_TEST("st2 {v18.4h, v19.4h}, [x5]",         17, 7)
823 MEM_TEST("st2 {v18.4h, v19.4h}, [x5], #16",    9, 9)
824 MEM_TEST("st2 {v18.4h, v19.4h}, [x5], x6",     -13, -5)
825 
826 MEM_TEST("st2 {v18.16b, v19.16b}, [x5]",       17, 7)
827 MEM_TEST("st2 {v18.16b, v19.16b}, [x5], #32",  9, 9)
828 MEM_TEST("st2 {v18.16b, v19.16b}, [x5], x6",   -13, -5)
829 
830 MEM_TEST("st2 {v18.8b, v19.8b}, [x5]",         17, 7)
831 MEM_TEST("st2 {v18.8b, v19.8b}, [x5], #16",    9, 9)
832 MEM_TEST("st2 {v18.8b, v19.8b}, [x5], x6",     -13, -5)
833 
834 MEM_TEST("ld2 {v18.2d, v19.2d}, [x5]",         17, 7)
835 MEM_TEST("ld2 {v18.2d, v19.2d}, [x5], #32",    9, 9)
836 MEM_TEST("ld2 {v18.2d, v19.2d}, [x5], x6",     -13, -5)
837 
838 /* no 1d case */
839 
840 MEM_TEST("ld2 {v18.4s, v19.4s}, [x5]",         17, 7)
841 MEM_TEST("ld2 {v18.4s, v19.4s}, [x5], #32",    9, 9)
842 MEM_TEST("ld2 {v18.4s, v19.4s}, [x5], x6",     -13, -5)
843 
844 MEM_TEST("ld2 {v18.2s, v19.2s}, [x5]",         17, 7)
845 MEM_TEST("ld2 {v18.2s, v19.2s}, [x5], #16",    9, 9)
846 MEM_TEST("ld2 {v18.2s, v19.2s}, [x5], x6",     -13, -5)
847 
848 MEM_TEST("ld2 {v18.8h, v19.8h}, [x5]",         17, 7)
849 MEM_TEST("ld2 {v18.8h, v19.8h}, [x5], #32",    9, 9)
850 MEM_TEST("ld2 {v18.8h, v19.8h}, [x5], x6",     -13, -5)
851 
852 MEM_TEST("ld2 {v18.4h, v19.4h}, [x5]",         17, 7)
853 MEM_TEST("ld2 {v18.4h, v19.4h}, [x5], #16",    9, 9)
854 MEM_TEST("ld2 {v18.4h, v19.4h}, [x5], x6",     -13, -5)
855 
856 MEM_TEST("ld2 {v18.16b, v19.16b}, [x5]",       17, 7)
857 MEM_TEST("ld2 {v18.16b, v19.16b}, [x5], #32",  9, 9)
858 MEM_TEST("ld2 {v18.16b, v19.16b}, [x5], x6",   -13, -5)
859 
860 MEM_TEST("ld2 {v18.8b, v19.8b}, [x5]",         17, 7)
861 MEM_TEST("ld2 {v18.8b, v19.8b}, [x5], #16",    9, 9)
862 MEM_TEST("ld2 {v18.8b, v19.8b}, [x5], x6",     -13, -5)
863 
864 ////////////////////////////////////////////////////////////////
865 printf("LD3/ST3 (multiple 3-elem structs to/from 3 regs\n");
866 
867 MEM_TEST("st3 {v17.2d, v18.2d, v19.2d}, [x5]",       17,  7)
868 MEM_TEST("st3 {v17.2d, v18.2d, v19.2d}, [x5], #48",  9,   9)
869 MEM_TEST("st3 {v17.2d, v18.2d, v19.2d}, [x5], x6",   -13, -5)
870 
871 /* no 1d case */
872 
873 MEM_TEST("st3 {v17.4s, v18.4s, v19.4s}, [x5]",          17, 7)
874 MEM_TEST("st3 {v17.4s, v18.4s, v19.4s}, [x5], #48",     9, 9)
875 MEM_TEST("st3 {v17.4s, v18.4s, v19.4s}, [x5], x6",      -13, -5)
876 
877 MEM_TEST("st3 {v17.2s, v18.2s, v19.2s}, [x5]",          17, 7)
878 MEM_TEST("st3 {v17.2s, v18.2s, v19.2s}, [x5], #24",     9, 9)
879 MEM_TEST("st3 {v17.2s, v18.2s, v19.2s}, [x5], x6",      -13, -5)
880 
881 MEM_TEST("st3 {v17.8h, v18.8h, v19.8h}, [x5]",          17, 7)
882 MEM_TEST("st3 {v17.8h, v18.8h, v19.8h}, [x5], #48",     9, 9)
883 MEM_TEST("st3 {v17.8h, v18.8h, v19.8h}, [x5], x6",      -13, -5)
884 
885 MEM_TEST("st3 {v17.4h, v18.4h, v19.4h}, [x5]",          17, 7)
886 MEM_TEST("st3 {v17.4h, v18.4h, v19.4h}, [x5], #24",     9, 9)
887 MEM_TEST("st3 {v17.4h, v18.4h, v19.4h}, [x5], x6",      -13, -5)
888 
889 MEM_TEST("st3 {v17.16b, v18.16b, v19.16b}, [x5]",       17, 7)
890 MEM_TEST("st3 {v17.16b, v18.16b, v19.16b}, [x5], #48",  9, 9)
891 MEM_TEST("st3 {v17.16b, v18.16b, v19.16b}, [x5], x6",   -13, -5)
892 
893 MEM_TEST("st3 {v17.8b, v18.8b, v19.8b}, [x5]",          17, 7)
894 MEM_TEST("st3 {v17.8b, v18.8b, v19.8b}, [x5], #24",     9, 9)
895 MEM_TEST("st3 {v17.8b, v18.8b, v19.8b}, [x5], x6",      -13, -5)
896 
897 MEM_TEST("ld3 {v17.2d, v18.2d, v19.2d}, [x5]",       17,  7)
898 MEM_TEST("ld3 {v17.2d, v18.2d, v19.2d}, [x5], #48",  9,   9)
899 MEM_TEST("ld3 {v17.2d, v18.2d, v19.2d}, [x5], x6",   -13, -5)
900 
901 /* no 1d case */
902 
903 MEM_TEST("ld3 {v17.4s, v18.4s, v19.4s}, [x5]",          17, 7)
904 MEM_TEST("ld3 {v17.4s, v18.4s, v19.4s}, [x5], #48",     9, 9)
905 MEM_TEST("ld3 {v17.4s, v18.4s, v19.4s}, [x5], x6",      -13, -5)
906 
907 MEM_TEST("ld3 {v17.2s, v18.2s, v19.2s}, [x5]",          17, 7)
908 MEM_TEST("ld3 {v17.2s, v18.2s, v19.2s}, [x5], #24",     9, 9)
909 MEM_TEST("ld3 {v17.2s, v18.2s, v19.2s}, [x5], x6",      -13, -5)
910 
911 MEM_TEST("ld3 {v17.8h, v18.8h, v19.8h}, [x5]",          17, 7)
912 MEM_TEST("ld3 {v17.8h, v18.8h, v19.8h}, [x5], #48",     9, 9)
913 MEM_TEST("ld3 {v17.8h, v18.8h, v19.8h}, [x5], x6",      -13, -5)
914 
915 MEM_TEST("ld3 {v17.4h, v18.4h, v19.4h}, [x5]",          17, 7)
916 MEM_TEST("ld3 {v17.4h, v18.4h, v19.4h}, [x5], #24",     9, 9)
917 MEM_TEST("ld3 {v17.4h, v18.4h, v19.4h}, [x5], x6",      -13, -5)
918 
919 MEM_TEST("ld3 {v17.16b, v18.16b, v19.16b}, [x5]",       17, 7)
920 MEM_TEST("ld3 {v17.16b, v18.16b, v19.16b}, [x5], #48",  9, 9)
921 MEM_TEST("ld3 {v17.16b, v18.16b, v19.16b}, [x5], x6",   -13, -5)
922 
923 MEM_TEST("ld3 {v17.8b, v18.8b, v19.8b}, [x5]",          17, 7)
924 MEM_TEST("ld3 {v17.8b, v18.8b, v19.8b}, [x5], #24",     9, 9)
925 MEM_TEST("ld3 {v17.8b, v18.8b, v19.8b}, [x5], x6",      -13, -5)
926 
927 ////////////////////////////////////////////////////////////////
928 printf("LD4/ST4 (multiple 4-elem structs to/from 4 regs\n");
929 
930 MEM_TEST("st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5]",           17, 7)
931 MEM_TEST("st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64",      9, 9)
932 MEM_TEST("st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6",       -13, -5)
933 
934 /* no 1d case */
935 
936 MEM_TEST("st4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5]",           17, 7)
937 MEM_TEST("st4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64",      9, 9)
938 MEM_TEST("st4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6",       -13, -5)
939 
940 MEM_TEST("st4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5]",           17, 7)
941 MEM_TEST("st4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32",      9, 9)
942 MEM_TEST("st4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6",       -13, -5)
943 
944 MEM_TEST("st4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5]",           17, 7)
945 MEM_TEST("st4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64",      9, 9)
946 MEM_TEST("st4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6",       -13, -5)
947 
948 MEM_TEST("st4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5]",           17, 7)
949 MEM_TEST("st4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32",      9, 9)
950 MEM_TEST("st4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6",       -13, -5)
951 
952 MEM_TEST("st4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]",       17, 7)
953 MEM_TEST("st4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64",  9, 9)
954 MEM_TEST("st4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6",   -13, -5)
955 
956 MEM_TEST("st4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5]",           17, 7)
957 MEM_TEST("st4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32",      9, 9)
958 MEM_TEST("st4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6",       -13, -5)
959 
960 MEM_TEST("ld4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5]",           17, 7)
961 MEM_TEST("ld4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64",      9, 9)
962 MEM_TEST("ld4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6",       -13, -5)
963 
964 /* no 1d case */
965 
966 MEM_TEST("ld4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5]",           17, 7)
967 MEM_TEST("ld4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64",      9, 9)
968 MEM_TEST("ld4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6",       -13, -5)
969 
970 MEM_TEST("ld4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5]",           17, 7)
971 MEM_TEST("ld4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32",      9, 9)
972 MEM_TEST("ld4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6",       -13, -5)
973 
974 MEM_TEST("ld4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5]",           17, 7)
975 MEM_TEST("ld4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64",      9, 9)
976 MEM_TEST("ld4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6",       -13, -5)
977 
978 MEM_TEST("ld4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5]",           17, 7)
979 MEM_TEST("ld4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32",      9, 9)
980 MEM_TEST("ld4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6",       -13, -5)
981 
982 MEM_TEST("ld4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]",       17, 7)
983 MEM_TEST("ld4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64",  9, 9)
984 MEM_TEST("ld4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6",   -13, -5)
985 
986 MEM_TEST("ld4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5]",           17, 7)
987 MEM_TEST("ld4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32",      9, 9)
988 MEM_TEST("ld4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6",       -13, -5)
989 
990 ////////////////////////////////////////////////////////////////
991 printf("LD1/ST1 (multiple 1-elem structs to/from 2/3/4 regs\n");
992 
993 MEM_TEST("st1 {v19.2d, v20.2d},                     [x5]", 17, 7)
994 MEM_TEST("st1 {v19.2d, v20.2d},                     [x5], #32", 9, 9)
995 MEM_TEST("st1 {v19.2d, v20.2d},                     [x5], x6", -13, -5)
996 
997 MEM_TEST("st1 {v17.2d, v18.2d, v19.2d},             [x5]", 17, 7)
998 MEM_TEST("st1 {v17.2d, v18.2d, v19.2d},             [x5], #48", 9, 9)
999 MEM_TEST("st1 {v17.2d, v18.2d, v19.2d},             [x5], x6", -13, -5)
1000 
1001 MEM_TEST("st1 {v17.2d, v18.2d, v19.2d, v20.2d},     [x5]", 17, 7)
1002 MEM_TEST("st1 {v17.2d, v18.2d, v19.2d, v20.2d},     [x5], #64", 9, 9)
1003 MEM_TEST("st1 {v17.2d, v18.2d, v19.2d, v20.2d},     [x5], x6", -13, -5)
1004 
1005 
1006 MEM_TEST("st1 {v19.1d, v20.1d},                     [x5]", 17, 7)
1007 MEM_TEST("st1 {v19.1d, v20.1d},                     [x5], #16", 9, 9)
1008 MEM_TEST("st1 {v19.1d, v20.1d},                     [x5], x6", -13, -5)
1009 
1010 MEM_TEST("st1 {v17.1d, v18.1d, v19.1d},             [x5]", 17, 7)
1011 MEM_TEST("st1 {v17.1d, v18.1d, v19.1d},             [x5], #24", 9, 9)
1012 MEM_TEST("st1 {v17.1d, v18.1d, v19.1d},             [x5], x6", -13, -5)
1013 
1014 MEM_TEST("st1 {v17.1d, v18.1d, v19.1d, v20.1d},     [x5]", 17, 7)
1015 MEM_TEST("st1 {v17.1d, v18.1d, v19.1d, v20.1d},     [x5], #32", 9, 9)
1016 MEM_TEST("st1 {v17.1d, v18.1d, v19.1d, v20.1d},     [x5], x6", -13, -5)
1017 
1018 
1019 MEM_TEST("st1 {v19.4s, v20.4s},                     [x5]", 17, 7)
1020 MEM_TEST("st1 {v19.4s, v20.4s},                     [x5], #32", 9, 9)
1021 MEM_TEST("st1 {v19.4s, v20.4s},                     [x5], x6", -13, -5)
1022 
1023 MEM_TEST("st1 {v17.4s, v18.4s, v19.4s},             [x5]", 17, 7)
1024 MEM_TEST("st1 {v17.4s, v18.4s, v19.4s},             [x5], #48", 9, 9)
1025 MEM_TEST("st1 {v17.4s, v18.4s, v19.4s},             [x5], x6", -13, -5)
1026 
1027 MEM_TEST("st1 {v17.4s, v18.4s, v19.4s, v20.4s},     [x5]", 17, 7)
1028 MEM_TEST("st1 {v17.4s, v18.4s, v19.4s, v20.4s},     [x5], #64", 9, 9)
1029 MEM_TEST("st1 {v17.4s, v18.4s, v19.4s, v20.4s},     [x5], x6", -13, -5)
1030 
1031 
1032 MEM_TEST("st1 {v19.2s, v20.2s},                     [x5]", 17, 7)
1033 MEM_TEST("st1 {v19.2s, v20.2s},                     [x5], #16", 9, 9)
1034 MEM_TEST("st1 {v19.2s, v20.2s},                     [x5], x6", -13, -5)
1035 
1036 MEM_TEST("st1 {v17.2s, v18.2s, v19.2s},             [x5]", 17, 7)
1037 MEM_TEST("st1 {v17.2s, v18.2s, v19.2s},             [x5], #24", 9, 9)
1038 MEM_TEST("st1 {v17.2s, v18.2s, v19.2s},             [x5], x6", -13, -5)
1039 
1040 MEM_TEST("st1 {v17.2s, v18.2s, v19.2s, v20.2s},     [x5]", 17, 7)
1041 MEM_TEST("st1 {v17.2s, v18.2s, v19.2s, v20.2s},     [x5], #32", 9, 9)
1042 MEM_TEST("st1 {v17.2s, v18.2s, v19.2s, v20.2s},     [x5], x6", -13, -5)
1043 
1044 
1045 MEM_TEST("st1 {v19.8h, v20.8h},                     [x5]", 17, 7)
1046 MEM_TEST("st1 {v19.8h, v20.8h},                     [x5], #32", 9, 9)
1047 MEM_TEST("st1 {v19.8h, v20.8h},                     [x5], x6", -13, -5)
1048 
1049 MEM_TEST("st1 {v17.8h, v18.8h, v19.8h},             [x5]", 17, 7)
1050 MEM_TEST("st1 {v17.8h, v18.8h, v19.8h},             [x5], #48", 9, 9)
1051 MEM_TEST("st1 {v17.8h, v18.8h, v19.8h},             [x5], x6", -13, -5)
1052 
1053 MEM_TEST("st1 {v17.8h, v18.8h, v19.8h, v20.8h},     [x5]", 17, 7)
1054 MEM_TEST("st1 {v17.8h, v18.8h, v19.8h, v20.8h},     [x5], #64", 9, 9)
1055 MEM_TEST("st1 {v17.8h, v18.8h, v19.8h, v20.8h},     [x5], x6", -13, -5)
1056 
1057 
1058 MEM_TEST("st1 {v19.4h, v20.4h},                     [x5]", 17, 7)
1059 MEM_TEST("st1 {v19.4h, v20.4h},                     [x5], #16", 9, 9)
1060 MEM_TEST("st1 {v19.4h, v20.4h},                     [x5], x6", -13, -5)
1061 
1062 MEM_TEST("st1 {v17.4h, v18.4h, v19.4h},             [x5]", 17, 7)
1063 MEM_TEST("st1 {v17.4h, v18.4h, v19.4h},             [x5], #24", 9, 9)
1064 MEM_TEST("st1 {v17.4h, v18.4h, v19.4h},             [x5], x6", -13, -5)
1065 
1066 MEM_TEST("st1 {v17.4h, v18.4h, v19.4h, v20.4h},     [x5]", 17, 7)
1067 MEM_TEST("st1 {v17.4h, v18.4h, v19.4h, v20.4h},     [x5], #32", 9, 9)
1068 MEM_TEST("st1 {v17.4h, v18.4h, v19.4h, v20.4h},     [x5], x6", -13, -5)
1069 
1070 
1071 MEM_TEST("st1 {v19.16b, v20.16b},                   [x5]", 17, 7)
1072 MEM_TEST("st1 {v19.16b, v20.16b},                   [x5], #32", 9, 9)
1073 MEM_TEST("st1 {v19.16b, v20.16b},                   [x5], x6", -13, -5)
1074 
1075 MEM_TEST("st1 {v17.16b, v18.16b, v19.16b},          [x5]", 17, 7)
1076 MEM_TEST("st1 {v17.16b, v18.16b, v19.16b},          [x5], #48", 9, 9)
1077 MEM_TEST("st1 {v17.16b, v18.16b, v19.16b},          [x5], x6", -13, -5)
1078 
1079 MEM_TEST("st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 17, 7)
1080 MEM_TEST("st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64", 9, 9)
1081 MEM_TEST("st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", -13, -5)
1082 
1083 
1084 MEM_TEST("st1 {v19.8b, v20.8b},                     [x5]", 17, 7)
1085 MEM_TEST("st1 {v19.8b, v20.8b},                     [x5], #16", 9, 9)
1086 MEM_TEST("st1 {v19.8b, v20.8b},                     [x5], x6", -13, -5)
1087 
1088 MEM_TEST("st1 {v17.8b, v18.8b, v19.8b},             [x5]", 17, 7)
1089 MEM_TEST("st1 {v17.8b, v18.8b, v19.8b},             [x5], #24", 9, 9)
1090 MEM_TEST("st1 {v17.8b, v18.8b, v19.8b},             [x5], x6", -13, -5)
1091 
1092 MEM_TEST("st1 {v17.8b, v18.8b, v19.8b, v20.8b},     [x5]", 17, 7)
1093 MEM_TEST("st1 {v17.8b, v18.8b, v19.8b, v20.8b},     [x5], #32", 9, 9)
1094 MEM_TEST("st1 {v17.8b, v18.8b, v19.8b, v20.8b},     [x5], x6", -13, -5)
1095 
1096 
1097 MEM_TEST("ld1 {v19.2d, v20.2d},                     [x5]", 17, 7)
1098 MEM_TEST("ld1 {v19.2d, v20.2d},                     [x5], #32", 9, 9)
1099 MEM_TEST("ld1 {v19.2d, v20.2d},                     [x5], x6", -13, -5)
1100 
1101 MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d},             [x5]", 17, 7)
1102 MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d},             [x5], #48", 9, 9)
1103 MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d},             [x5], x6", -13, -5)
1104 
1105 MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d, v20.2d},     [x5]", 17, 7)
1106 MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d, v20.2d},     [x5], #64", 9, 9)
1107 MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d, v20.2d},     [x5], x6", -13, -5)
1108 
1109 
1110 MEM_TEST("ld1 {v19.1d, v20.1d},                     [x5]", 17, 7)
1111 MEM_TEST("ld1 {v19.1d, v20.1d},                     [x5], #16", 9, 9)
1112 MEM_TEST("ld1 {v19.1d, v20.1d},                     [x5], x6", -13, -5)
1113 
1114 MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d},             [x5]", 17, 7)
1115 MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d},             [x5], #24", 9, 9)
1116 MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d},             [x5], x6", -13, -5)
1117 
1118 MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d, v20.1d},     [x5]", 17, 7)
1119 MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d, v20.1d},     [x5], #32", 9, 9)
1120 MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d, v20.1d},     [x5], x6", -13, -5)
1121 
1122 
1123 MEM_TEST("ld1 {v19.4s, v20.4s},                     [x5]", 17, 7)
1124 MEM_TEST("ld1 {v19.4s, v20.4s},                     [x5], #32", 9, 9)
1125 MEM_TEST("ld1 {v19.4s, v20.4s},                     [x5], x6", -13, -5)
1126 
1127 MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s},             [x5]", 17, 7)
1128 MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s},             [x5], #48", 9, 9)
1129 MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s},             [x5], x6", -13, -5)
1130 
1131 MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s, v20.4s},     [x5]", 17, 7)
1132 MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s, v20.4s},     [x5], #64", 9, 9)
1133 MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s, v20.4s},     [x5], x6", -13, -5)
1134 
1135 
1136 MEM_TEST("ld1 {v19.2s, v20.2s},                     [x5]", 17, 7)
1137 MEM_TEST("ld1 {v19.2s, v20.2s},                     [x5], #16", 9, 9)
1138 MEM_TEST("ld1 {v19.2s, v20.2s},                     [x5], x6", -13, -5)
1139 
1140 MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s},             [x5]", 17, 7)
1141 MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s},             [x5], #24", 9, 9)
1142 MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s},             [x5], x6", -13, -5)
1143 
1144 MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s, v20.2s},     [x5]", 17, 7)
1145 MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s, v20.2s},     [x5], #32", 9, 9)
1146 MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s, v20.2s},     [x5], x6", -13, -5)
1147 
1148 
1149 MEM_TEST("ld1 {v19.8h, v20.8h},                     [x5]", 17, 7)
1150 MEM_TEST("ld1 {v19.8h, v20.8h},                     [x5], #32", 9, 9)
1151 MEM_TEST("ld1 {v19.8h, v20.8h},                     [x5], x6", -13, -5)
1152 
1153 MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h},             [x5]", 17, 7)
1154 MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h},             [x5], #48", 9, 9)
1155 MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h},             [x5], x6", -13, -5)
1156 
1157 MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h, v20.8h},     [x5]", 17, 7)
1158 MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h, v20.8h},     [x5], #64", 9, 9)
1159 MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h, v20.8h},     [x5], x6", -13, -5)
1160 
1161 
1162 MEM_TEST("ld1 {v19.4h, v20.4h},                     [x5]", 17, 7)
1163 MEM_TEST("ld1 {v19.4h, v20.4h},                     [x5], #16", 9, 9)
1164 MEM_TEST("ld1 {v19.4h, v20.4h},                     [x5], x6", -13, -5)
1165 
1166 MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h},             [x5]", 17, 7)
1167 MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h},             [x5], #24", 9, 9)
1168 MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h},             [x5], x6", -13, -5)
1169 
1170 MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h, v20.4h},     [x5]", 17, 7)
1171 MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h, v20.4h},     [x5], #32", 9, 9)
1172 MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h, v20.4h},     [x5], x6", -13, -5)
1173 
1174 
1175 MEM_TEST("ld1 {v19.16b, v20.16b},                   [x5]", 17, 7)
1176 MEM_TEST("ld1 {v19.16b, v20.16b},                   [x5], #32", 9, 9)
1177 MEM_TEST("ld1 {v19.16b, v20.16b},                   [x5], x6", -13, -5)
1178 
1179 MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b},          [x5]", 17, 7)
1180 MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b},          [x5], #48", 9, 9)
1181 MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b},          [x5], x6", -13, -5)
1182 
1183 MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 17, 7)
1184 MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64", 9, 9)
1185 MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", -13, -5)
1186 
1187 
1188 MEM_TEST("ld1 {v19.8b, v20.8b},                     [x5]", 17, 7)
1189 MEM_TEST("ld1 {v19.8b, v20.8b},                     [x5], #16", 9, 9)
1190 MEM_TEST("ld1 {v19.8b, v20.8b},                     [x5], x6", -13, -5)
1191 
1192 MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b},             [x5]", 17, 7)
1193 MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b},             [x5], #24", 9, 9)
1194 MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b},             [x5], x6", -13, -5)
1195 
1196 MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b, v20.8b},     [x5]", 17, 7)
1197 MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b, v20.8b},     [x5], #32", 9, 9)
1198 MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b, v20.8b},     [x5], x6", -13, -5)
1199 
1200 
1201 ////////////////////////////////////////////////////////////////
1202 printf("LD1R (single structure, replicate)\n");
1203 
1204 MEM_TEST("ld1r {v17.2d},  [x5]", 3, -5)
1205 MEM_TEST("ld1r {v17.1d},  [x5]", 3, -4)
1206 MEM_TEST("ld1r {v17.4s},  [x5]", 3, -3)
1207 MEM_TEST("ld1r {v17.2s},  [x5]", 3, -2)
1208 MEM_TEST("ld1r {v17.8h},  [x5]", 3, -1)
1209 MEM_TEST("ld1r {v17.4h},  [x5]", 3, 1)
1210 MEM_TEST("ld1r {v17.16b}, [x5]", 3, 2)
1211 MEM_TEST("ld1r {v17.8b},  [x5]", 3, 3)
1212 
1213 MEM_TEST("ld1r {v17.2d},  [x5], #8", 3, -5)
1214 MEM_TEST("ld1r {v17.1d},  [x5], #8", 3, -4)
1215 MEM_TEST("ld1r {v17.4s},  [x5], #4", 3, -3)
1216 MEM_TEST("ld1r {v17.2s},  [x5], #4", 3, -2)
1217 MEM_TEST("ld1r {v17.8h},  [x5], #2", 3, -1)
1218 MEM_TEST("ld1r {v17.4h},  [x5], #2", 3, 1)
1219 MEM_TEST("ld1r {v17.16b}, [x5], #1", 3, 2)
1220 MEM_TEST("ld1r {v17.8b},  [x5], #1", 3, 3)
1221 
1222 MEM_TEST("ld1r {v17.2d},  [x5], x6", 3, -5)
1223 MEM_TEST("ld1r {v17.1d},  [x5], x6", 3, -4)
1224 MEM_TEST("ld1r {v17.4s},  [x5], x6", 3, -3)
1225 MEM_TEST("ld1r {v17.2s},  [x5], x6", 3, -2)
1226 MEM_TEST("ld1r {v17.8h},  [x5], x6", 3, -1)
1227 MEM_TEST("ld1r {v17.4h},  [x5], x6", 3, 1)
1228 MEM_TEST("ld1r {v17.16b}, [x5], x6", 3, 2)
1229 MEM_TEST("ld1r {v17.8b},  [x5], x6", 3, 3)
1230 
1231 
1232 ////////////////////////////////////////////////////////////////
1233 printf("LD2R (single structure, replicate)\n");
1234 
1235 MEM_TEST("ld2r {v17.2d , v18.2d },  [x5]", 3, -5)
1236 MEM_TEST("ld2r {v18.1d , v19.1d },  [x5]", 3, -4)
1237 MEM_TEST("ld2r {v19.4s , v20.4s },  [x5]", 3, -3)
1238 MEM_TEST("ld2r {v17.2s , v18.2s },  [x5]", 3, -2)
1239 MEM_TEST("ld2r {v18.8h , v19.8h },  [x5]", 3, -1)
1240 MEM_TEST("ld2r {v19.4h , v20.4h },  [x5]", 3, 1)
1241 MEM_TEST("ld2r {v17.16b, v18.16b},  [x5]", 3, 2)
1242 MEM_TEST("ld2r {v18.8b , v19.8b },  [x5]", 3, 3)
1243 
1244 MEM_TEST("ld2r {v19.2d , v20.2d },  [x5], #16", 3, -5)
1245 MEM_TEST("ld2r {v17.1d , v18.1d },  [x5], #16", 3, -4)
1246 MEM_TEST("ld2r {v18.4s , v19.4s },  [x5], #8", 3, -3)
1247 MEM_TEST("ld2r {v19.2s , v20.2s },  [x5], #8", 3, -2)
1248 MEM_TEST("ld2r {v17.8h , v18.8h },  [x5], #4", 3, -1)
1249 MEM_TEST("ld2r {v18.4h , v19.4h },  [x5], #4", 3, 1)
1250 MEM_TEST("ld2r {v19.16b, v20.16b},  [x5], #2", 3, 2)
1251 MEM_TEST("ld2r {v17.8b , v18.8b },  [x5], #2", 3, 3)
1252 
1253 MEM_TEST("ld2r {v18.2d , v19.2d },  [x5], x6", 3, -5)
1254 MEM_TEST("ld2r {v19.1d , v20.1d },  [x5], x6", 3, -4)
1255 MEM_TEST("ld2r {v17.4s , v18.4s },  [x5], x6", 3, -3)
1256 MEM_TEST("ld2r {v18.2s , v19.2s },  [x5], x6", 3, -2)
1257 MEM_TEST("ld2r {v19.8h , v20.8h },  [x5], x6", 3, -1)
1258 MEM_TEST("ld2r {v17.4h , v18.4h },  [x5], x6", 3, 1)
1259 MEM_TEST("ld2r {v18.16b, v19.16b},  [x5], x6", 3, 2)
1260 MEM_TEST("ld2r {v19.8b , v20.8b },  [x5], x6", 3, 3)
1261 
1262 
1263 //////////////////////////////////////////////////////////////////
1264 printf("LD3R (single structure, replicate)\n");
1265 
1266 MEM_TEST("ld3r {v17.2d , v18.2d , v19.2d },  [x5]", 3, -5)
1267 MEM_TEST("ld3r {v18.1d , v19.1d , v20.1d },  [x5]", 3, -4)
1268 MEM_TEST("ld3r {v17.4s , v18.4s , v19.4s },  [x5]", 3, -3)
1269 MEM_TEST("ld3r {v18.2s , v19.2s , v20.2s },  [x5]", 3, -2)
1270 MEM_TEST("ld3r {v17.8h , v18.8h , v19.8h },  [x5]", 3, -5)
1271 MEM_TEST("ld3r {v18.4h , v19.4h , v20.4h },  [x5]", 3, -4)
1272 MEM_TEST("ld3r {v17.16b, v18.16b, v19.16b},  [x5]", 3, -3)
1273 MEM_TEST("ld3r {v18.8b , v19.8b , v20.8b },  [x5]", 3, -2)
1274 
1275 MEM_TEST("ld3r {v17.2d , v18.2d , v19.2d },  [x5], #24", 3, -5)
1276 MEM_TEST("ld3r {v18.1d , v19.1d , v20.1d },  [x5], #24", 3, -4)
1277 MEM_TEST("ld3r {v17.4s , v18.4s , v19.4s },  [x5], #12", 3, -3)
1278 MEM_TEST("ld3r {v18.2s , v19.2s , v20.2s },  [x5], #12", 3, -2)
1279 MEM_TEST("ld3r {v17.8h , v18.8h , v19.8h },  [x5], #6", 3, -5)
1280 MEM_TEST("ld3r {v18.4h , v19.4h , v20.4h },  [x5], #6", 3, -4)
1281 MEM_TEST("ld3r {v17.16b, v18.16b, v19.16b},  [x5], #3", 3, -3)
1282 MEM_TEST("ld3r {v18.8b , v19.8b , v20.8b },  [x5], #3", 3, -2)
1283 
1284 MEM_TEST("ld3r {v17.2d , v18.2d , v19.2d },  [x5], x6", 3, -5)
1285 MEM_TEST("ld3r {v18.1d , v19.1d , v20.1d },  [x5], x6", 3, -4)
1286 MEM_TEST("ld3r {v17.4s , v18.4s , v19.4s },  [x5], x6", 3, -3)
1287 MEM_TEST("ld3r {v18.2s , v19.2s , v20.2s },  [x5], x6", 3, -2)
1288 MEM_TEST("ld3r {v17.8h , v18.8h , v19.8h },  [x5], x6", 3, -5)
1289 MEM_TEST("ld3r {v18.4h , v19.4h , v20.4h },  [x5], x6", 3, -4)
1290 MEM_TEST("ld3r {v17.16b, v18.16b, v19.16b},  [x5], x6", 3, -3)
1291 MEM_TEST("ld3r {v18.8b , v19.8b , v20.8b },  [x5], x6", 3, -2)
1292 
1293 
1294 ////////////////////////////////////////////////////////////////
1295 printf("LD4R (single structure, replicate)\n");
1296 
1297 MEM_TEST("ld4r {v17.2d , v18.2d , v19.2d , v20.2d },  [x5]", 3, -5)
1298 MEM_TEST("ld4r {v17.1d , v18.1d , v19.1d , v20.1d },  [x5]", 3, -4)
1299 MEM_TEST("ld4r {v17.4s , v18.4s , v19.4s , v20.4s },  [x5]", 3, -3)
1300 MEM_TEST("ld4r {v17.2s , v18.2s , v19.2s , v20.2s },  [x5]", 3, -2)
1301 MEM_TEST("ld4r {v17.8h , v18.8h , v19.8h , v20.8h },  [x5]", 3, -5)
1302 MEM_TEST("ld4r {v17.4h , v18.4h , v19.4h , v20.4h },  [x5]", 3, -4)
1303 MEM_TEST("ld4r {v17.16b, v18.16b, v19.16b, v20.16b},  [x5]", 3, -3)
1304 MEM_TEST("ld4r {v17.8b , v18.8b , v19.8b , v20.8b },  [x5]", 3, -2)
1305 
1306 MEM_TEST("ld4r {v17.2d , v18.2d , v19.2d , v20.2d },  [x5], #32", 3, -5)
1307 MEM_TEST("ld4r {v17.1d , v18.1d , v19.1d , v20.1d },  [x5], #32", 3, -4)
1308 MEM_TEST("ld4r {v17.4s , v18.4s , v19.4s , v20.4s },  [x5], #16", 3, -3)
1309 MEM_TEST("ld4r {v17.2s , v18.2s , v19.2s , v20.2s },  [x5], #16", 3, -2)
1310 MEM_TEST("ld4r {v17.8h , v18.8h , v19.8h , v20.8h },  [x5], #8", 3, -5)
1311 MEM_TEST("ld4r {v17.4h , v18.4h , v19.4h , v20.4h },  [x5], #8", 3, -4)
1312 MEM_TEST("ld4r {v17.16b, v18.16b, v19.16b, v20.16b},  [x5], #4", 3, -3)
1313 MEM_TEST("ld4r {v17.8b , v18.8b , v19.8b , v20.8b },  [x5], #4", 3, -2)
1314 
1315 MEM_TEST("ld4r {v17.2d , v18.2d , v19.2d , v20.2d },  [x5], x6", 3, -5)
1316 MEM_TEST("ld4r {v17.1d , v18.1d , v19.1d , v20.1d },  [x5], x6", 3, -4)
1317 MEM_TEST("ld4r {v17.4s , v18.4s , v19.4s , v20.4s },  [x5], x6", 3, -3)
1318 MEM_TEST("ld4r {v17.2s , v18.2s , v19.2s , v20.2s },  [x5], x6", 3, -2)
1319 MEM_TEST("ld4r {v17.8h , v18.8h , v19.8h , v20.8h },  [x5], x6", 3, -5)
1320 MEM_TEST("ld4r {v17.4h , v18.4h , v19.4h , v20.4h },  [x5], x6", 3, -4)
1321 MEM_TEST("ld4r {v17.16b, v18.16b, v19.16b, v20.16b},  [x5], x6", 3, -3)
1322 MEM_TEST("ld4r {v17.8b , v18.8b , v19.8b , v20.8b },  [x5], x6", 3, -2)
1323 
1324 
1325 ////////////////////////////////////////////////////////////////
1326 printf("LD1/ST1 (single 1-elem struct to/from one lane of 1 reg\n");
1327 
1328 MEM_TEST("st1 {v19.d}[0], [x5]",       17,  7)
1329 MEM_TEST("st1 {v19.d}[0], [x5], #8",   -9, 12)
1330 MEM_TEST("st1 {v19.d}[0], [x5], x6",   9, 13)
1331 
1332 MEM_TEST("st1 {v19.d}[1], [x5]",       17,  7)
1333 MEM_TEST("st1 {v19.d}[1], [x5], #8",   -9, 12)
1334 MEM_TEST("st1 {v19.d}[1], [x5], x6",   9, 13)
1335 
1336 MEM_TEST("st1 {v19.s}[0], [x5]",       17,  7)
1337 MEM_TEST("st1 {v19.s}[0], [x5], #4",   -9, 12)
1338 MEM_TEST("st1 {v19.s}[0], [x5], x6",   9, 13)
1339 
1340 MEM_TEST("st1 {v19.s}[3], [x5]",       17,  7)
1341 MEM_TEST("st1 {v19.s}[3], [x5], #4",   -9, 12)
1342 MEM_TEST("st1 {v19.s}[3], [x5], x6",   9, 13)
1343 
1344 MEM_TEST("st1 {v19.h}[0], [x5]",       17,  7)
1345 MEM_TEST("st1 {v19.h}[0], [x5], #2",   -9, 12)
1346 MEM_TEST("st1 {v19.h}[0], [x5], x6",   9, 13)
1347 
1348 MEM_TEST("st1 {v19.h}[6], [x5]",       17,  7)
1349 MEM_TEST("st1 {v19.h}[6], [x5], #2",   -9, 12)
1350 MEM_TEST("st1 {v19.h}[6], [x5], x6",   9, 13)
1351 
1352 MEM_TEST("st1 {v19.b}[0], [x5]",       17,  7)
1353 MEM_TEST("st1 {v19.b}[0], [x5], #1",   -9, 12)
1354 MEM_TEST("st1 {v19.b}[0], [x5], x6",   9, 13)
1355 
1356 MEM_TEST("st1 {v19.b}[13], [x5]",      17,  7)
1357 MEM_TEST("st1 {v19.b}[13], [x5], #1",  -9, 12)
1358 MEM_TEST("st1 {v19.b}[13], [x5], x6",  9, 13)
1359 
1360 
1361 MEM_TEST("ld1 {v19.d}[0], [x5]",       17,  7)
1362 MEM_TEST("ld1 {v19.d}[0], [x5], #8",   -9, 12)
1363 MEM_TEST("ld1 {v19.d}[0], [x5], x6",   9, 13)
1364 
1365 MEM_TEST("ld1 {v19.d}[1], [x5]",       17,  7)
1366 MEM_TEST("ld1 {v19.d}[1], [x5], #8",   -9, 12)
1367 MEM_TEST("ld1 {v19.d}[1], [x5], x6",   9, 13)
1368 
1369 MEM_TEST("ld1 {v19.s}[0], [x5]",       17,  7)
1370 MEM_TEST("ld1 {v19.s}[0], [x5], #4",   -9, 12)
1371 MEM_TEST("ld1 {v19.s}[0], [x5], x6",   9, 13)
1372 
1373 MEM_TEST("ld1 {v19.s}[3], [x5]",       17,  7)
1374 MEM_TEST("ld1 {v19.s}[3], [x5], #4",   -9, 12)
1375 MEM_TEST("ld1 {v19.s}[3], [x5], x6",   9, 13)
1376 
1377 MEM_TEST("ld1 {v19.h}[0], [x5]",       17,  7)
1378 MEM_TEST("ld1 {v19.h}[0], [x5], #2",   -9, 12)
1379 MEM_TEST("ld1 {v19.h}[0], [x5], x6",   9, 13)
1380 
1381 MEM_TEST("ld1 {v19.h}[6], [x5]",       17,  7)
1382 MEM_TEST("ld1 {v19.h}[6], [x5], #2",   -9, 12)
1383 MEM_TEST("ld1 {v19.h}[6], [x5], x6",   9, 13)
1384 
1385 MEM_TEST("ld1 {v19.b}[0], [x5]",       17,  7)
1386 MEM_TEST("ld1 {v19.b}[0], [x5], #1",   -9, 12)
1387 MEM_TEST("ld1 {v19.b}[0], [x5], x6",   9, 13)
1388 
1389 MEM_TEST("ld1 {v19.b}[13], [x5]",      17,  7)
1390 MEM_TEST("ld1 {v19.b}[13], [x5], #1",  -9, 12)
1391 MEM_TEST("ld1 {v19.b}[13], [x5], x6",  9, 13)
1392 
1393 
1394 ////////////////////////////////////////////////////////////////
1395 printf("LD2/ST2 (single 2-elem struct to/from one lane of 2 regs\n");
1396 
1397 MEM_TEST("st2 {v18.d, v19.d}[0], [x5]",       17,  7)
1398 MEM_TEST("st2 {v18.d, v19.d}[0], [x5], #16",  -9, 12)
1399 MEM_TEST("st2 {v18.d, v19.d}[0], [x5], x6",   9, 13)
1400 
1401 MEM_TEST("st2 {v18.d, v19.d}[1], [x5]",       17,  7)
1402 MEM_TEST("st2 {v18.d, v19.d}[1], [x5], #16",  -9, 12)
1403 MEM_TEST("st2 {v18.d, v19.d}[1], [x5], x6",   9, 13)
1404 
1405 MEM_TEST("st2 {v18.s, v19.s}[0], [x5]",       17,  7)
1406 MEM_TEST("st2 {v18.s, v19.s}[0], [x5], #8",   -9, 12)
1407 MEM_TEST("st2 {v18.s, v19.s}[0], [x5], x6",   9, 13)
1408 
1409 MEM_TEST("st2 {v18.s, v19.s}[3], [x5]",       17,  7)
1410 MEM_TEST("st2 {v18.s, v19.s}[3], [x5], #8",   -9, 12)
1411 MEM_TEST("st2 {v18.s, v19.s}[3], [x5], x6",   9, 13)
1412 
1413 MEM_TEST("st2 {v18.h, v19.h}[0], [x5]",       17,  7)
1414 MEM_TEST("st2 {v18.h, v19.h}[0], [x5], #4",   -9, 12)
1415 MEM_TEST("st2 {v18.h, v19.h}[0], [x5], x6",   9, 13)
1416 
1417 MEM_TEST("st2 {v18.h, v19.h}[6], [x5]",       17,  7)
1418 MEM_TEST("st2 {v18.h, v19.h}[6], [x5], #4",   -9, 12)
1419 MEM_TEST("st2 {v18.h, v19.h}[6], [x5], x6",   9, 13)
1420 
1421 MEM_TEST("st2 {v18.b, v19.b}[0], [x5]",       17,  7)
1422 MEM_TEST("st2 {v18.b, v19.b}[0], [x5], #2",   -9, 12)
1423 MEM_TEST("st2 {v18.b, v19.b}[0], [x5], x6",   9, 13)
1424 
1425 MEM_TEST("st2 {v18.b, v19.b}[13], [x5]",      17,  7)
1426 MEM_TEST("st2 {v18.b, v19.b}[13], [x5], #2",  -9, 12)
1427 MEM_TEST("st2 {v18.b, v19.b}[13], [x5], x6",  9, 13)
1428 
1429 
1430 MEM_TEST("ld2 {v18.d, v19.d}[0], [x5]",       17,  7)
1431 MEM_TEST("ld2 {v18.d, v19.d}[0], [x5], #16",  -9, 12)
1432 MEM_TEST("ld2 {v18.d, v19.d}[0], [x5], x6",   9, 13)
1433 
1434 MEM_TEST("ld2 {v18.d, v19.d}[1], [x5]",       17,  7)
1435 MEM_TEST("ld2 {v18.d, v19.d}[1], [x5], #16",  -9, 12)
1436 MEM_TEST("ld2 {v18.d, v19.d}[1], [x5], x6",   9, 13)
1437 
1438 MEM_TEST("ld2 {v18.s, v19.s}[0], [x5]",       17,  7)
1439 MEM_TEST("ld2 {v18.s, v19.s}[0], [x5], #8",   -9, 12)
1440 MEM_TEST("ld2 {v18.s, v19.s}[0], [x5], x6",   9, 13)
1441 
1442 MEM_TEST("ld2 {v18.s, v19.s}[3], [x5]",       17,  7)
1443 MEM_TEST("ld2 {v18.s, v19.s}[3], [x5], #8",   -9, 12)
1444 MEM_TEST("ld2 {v18.s, v19.s}[3], [x5], x6",   9, 13)
1445 
1446 MEM_TEST("ld2 {v18.h, v19.h}[0], [x5]",       17,  7)
1447 MEM_TEST("ld2 {v18.h, v19.h}[0], [x5], #4",   -9, 12)
1448 MEM_TEST("ld2 {v18.h, v19.h}[0], [x5], x6",   9, 13)
1449 
1450 MEM_TEST("ld2 {v18.h, v19.h}[6], [x5]",       17,  7)
1451 MEM_TEST("ld2 {v18.h, v19.h}[6], [x5], #4",   -9, 12)
1452 MEM_TEST("ld2 {v18.h, v19.h}[6], [x5], x6",   9, 13)
1453 
1454 MEM_TEST("ld2 {v18.b, v19.b}[0], [x5]",       17,  7)
1455 MEM_TEST("ld2 {v18.b, v19.b}[0], [x5], #2",   -9, 12)
1456 MEM_TEST("ld2 {v18.b, v19.b}[0], [x5], x6",   9, 13)
1457 
1458 MEM_TEST("ld2 {v18.b, v19.b}[13], [x5]",      17,  7)
1459 MEM_TEST("ld2 {v18.b, v19.b}[13], [x5], #2",  -9, 12)
1460 MEM_TEST("ld2 {v18.b, v19.b}[13], [x5], x6",  9, 13)
1461 
1462 
1463 ////////////////////////////////////////////////////////////////
1464 printf("LD3/ST3 (single 3-elem struct to/from one lane of 3 regs\n");
1465 
1466 MEM_TEST("st3 {v17.d, v18.d, v19.d}[0], [x5]",       17,  7)
1467 MEM_TEST("st3 {v17.d, v18.d, v19.d}[0], [x5], #24",  -9, 12)
1468 MEM_TEST("st3 {v17.d, v18.d, v19.d}[0], [x5], x6",   9, 13)
1469 
1470 MEM_TEST("st3 {v17.d, v18.d, v19.d}[1], [x5]",       17,  7)
1471 MEM_TEST("st3 {v17.d, v18.d, v19.d}[1], [x5], #24",  -9, 12)
1472 MEM_TEST("st3 {v17.d, v18.d, v19.d}[1], [x5], x6",   9, 13)
1473 
1474 MEM_TEST("st3 {v17.s, v18.s, v19.s}[0], [x5]",       17,  7)
1475 MEM_TEST("st3 {v17.s, v18.s, v19.s}[0], [x5], #12",  -9, 12)
1476 MEM_TEST("st3 {v17.s, v18.s, v19.s}[0], [x5], x6",   9, 13)
1477 
1478 MEM_TEST("st3 {v17.s, v18.s, v19.s}[3], [x5]",       17,  7)
1479 MEM_TEST("st3 {v17.s, v18.s, v19.s}[3], [x5], #12",  -9, 12)
1480 MEM_TEST("st3 {v17.s, v18.s, v19.s}[3], [x5], x6",   9, 13)
1481 
1482 MEM_TEST("st3 {v17.h, v18.h, v19.h}[0], [x5]",       17,  7)
1483 MEM_TEST("st3 {v17.h, v18.h, v19.h}[0], [x5], #6",   -9, 12)
1484 MEM_TEST("st3 {v17.h, v18.h, v19.h}[0], [x5], x6",   9, 13)
1485 
1486 MEM_TEST("st3 {v17.h, v18.h, v19.h}[6], [x5]",       17,  7)
1487 MEM_TEST("st3 {v17.h, v18.h, v19.h}[6], [x5], #6",   -9, 12)
1488 MEM_TEST("st3 {v17.h, v18.h, v19.h}[6], [x5], x6",   9, 13)
1489 
1490 MEM_TEST("st3 {v17.b, v18.b, v19.b}[0], [x5]",       17,  7)
1491 MEM_TEST("st3 {v17.b, v18.b, v19.b}[0], [x5], #3",   -9, 12)
1492 MEM_TEST("st3 {v17.b, v18.b, v19.b}[0], [x5], x6",   9, 13)
1493 
1494 MEM_TEST("st3 {v17.b, v18.b, v19.b}[13], [x5]",      17,  7)
1495 MEM_TEST("st3 {v17.b, v18.b, v19.b}[13], [x5], #3",  -9, 12)
1496 MEM_TEST("st3 {v17.b, v18.b, v19.b}[13], [x5], x6",  9, 13)
1497 
1498 
1499 MEM_TEST("ld3 {v17.d, v18.d, v19.d}[0], [x5]",       17,  7)
1500 MEM_TEST("ld3 {v17.d, v18.d, v19.d}[0], [x5], #24",  -9, 12)
1501 MEM_TEST("ld3 {v17.d, v18.d, v19.d}[0], [x5], x6",   9, 13)
1502 
1503 MEM_TEST("ld3 {v17.d, v18.d, v19.d}[1], [x5]",       17,  7)
1504 MEM_TEST("ld3 {v17.d, v18.d, v19.d}[1], [x5], #24",  -9, 12)
1505 MEM_TEST("ld3 {v17.d, v18.d, v19.d}[1], [x5], x6",   9, 13)
1506 
1507 MEM_TEST("ld3 {v17.s, v18.s, v19.s}[0], [x5]",       17,  7)
1508 MEM_TEST("ld3 {v17.s, v18.s, v19.s}[0], [x5], #12",  -9, 12)
1509 MEM_TEST("ld3 {v17.s, v18.s, v19.s}[0], [x5], x6",   9, 13)
1510 
1511 MEM_TEST("ld3 {v17.s, v18.s, v19.s}[3], [x5]",       17,  7)
1512 MEM_TEST("ld3 {v17.s, v18.s, v19.s}[3], [x5], #12",  -9, 12)
1513 MEM_TEST("ld3 {v17.s, v18.s, v19.s}[3], [x5], x6",   9, 13)
1514 
1515 MEM_TEST("ld3 {v17.h, v18.h, v19.h}[0], [x5]",       17,  7)
1516 MEM_TEST("ld3 {v17.h, v18.h, v19.h}[0], [x5], #6",   -9, 12)
1517 MEM_TEST("ld3 {v17.h, v18.h, v19.h}[0], [x5], x6",   9, 13)
1518 
1519 MEM_TEST("ld3 {v17.h, v18.h, v19.h}[6], [x5]",       17,  7)
1520 MEM_TEST("ld3 {v17.h, v18.h, v19.h}[6], [x5], #6",   -9, 12)
1521 MEM_TEST("ld3 {v17.h, v18.h, v19.h}[6], [x5], x6",   9, 13)
1522 
1523 MEM_TEST("ld3 {v17.b, v18.b, v19.b}[0], [x5]",       17,  7)
1524 MEM_TEST("ld3 {v17.b, v18.b, v19.b}[0], [x5], #3",   -9, 12)
1525 MEM_TEST("ld3 {v17.b, v18.b, v19.b}[0], [x5], x6",   9, 13)
1526 
1527 MEM_TEST("ld3 {v17.b, v18.b, v19.b}[13], [x5]",      17,  7)
1528 MEM_TEST("ld3 {v17.b, v18.b, v19.b}[13], [x5], #3",  -9, 12)
1529 MEM_TEST("ld3 {v17.b, v18.b, v19.b}[13], [x5], x6",  9, 13)
1530 
1531 
1532 ////////////////////////////////////////////////////////////////
1533 printf("LD4/ST4 (single 4-elem struct to/from one lane of 4 regs\n");
1534 
1535 MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5]",       17,  7)
1536 MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], #32",  -9, 12)
1537 MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], x6",   9, 13)
1538 
1539 MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5]",       17,  7)
1540 MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], #32",  -9, 12)
1541 MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], x6",   9, 13)
1542 
1543 MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5]",       17,  7)
1544 MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], #16",  -9, 12)
1545 MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], x6",   9, 13)
1546 
1547 MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5]",       17,  7)
1548 MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], #16",  -9, 12)
1549 MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], x6",   9, 13)
1550 
1551 MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5]",       17,  7)
1552 MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], #8",   -9, 12)
1553 MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], x6",   9, 13)
1554 
1555 MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5]",       17,  7)
1556 MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], #8",   -9, 12)
1557 MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], x6",   9, 13)
1558 
1559 MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5]",       17,  7)
1560 MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], #4",   -9, 12)
1561 MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], x6",   9, 13)
1562 
1563 MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5]",      17,  7)
1564 MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], #4",  -9, 12)
1565 MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], x6",  9, 13)
1566 
1567 
1568 MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5]",       17,  7)
1569 MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], #32",  -9, 12)
1570 MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], x6",   9, 13)
1571 
1572 MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5]",       17,  7)
1573 MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], #32",  -9, 12)
1574 MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], x6",   9, 13)
1575 
1576 MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5]",       17,  7)
1577 MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], #16",  -9, 12)
1578 MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], x6",   9, 13)
1579 
1580 MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5]",       17,  7)
1581 MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], #16",  -9, 12)
1582 MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], x6",   9, 13)
1583 
1584 MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5]",       17,  7)
1585 MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], #8",   -9, 12)
1586 MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], x6",   9, 13)
1587 
1588 MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5]",       17,  7)
1589 MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], #8",   -9, 12)
1590 MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], x6",   9, 13)
1591 
1592 MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5]",       17,  7)
1593 MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], #4",   -9, 12)
1594 MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], x6",   9, 13)
1595 
1596 MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5]",      17,  7)
1597 MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], #4",  -9, 12)
1598 MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], x6",  9, 13)
1599 
1600 ////////////////////////////////////////////////////////////////
1601 printf("PRFM (immediate)\n");
1602 
1603 MEM_TEST("prfm pldl1keep, [x5, #40]",  12, -4);
1604 MEM_TEST("prfm pstl3strm, [x5, #56]",  12, -4);
1605 
1606 ////////////////////////////////////////////////////////////////
1607 printf("PRFM (register)\n");
1608 
1609 MEM_TEST("prfm pldl1keep, [x5,x6]",  12, -4);
1610 MEM_TEST("prfm pldl1strm, [x5,x6, lsl #3]",  12, -4);
1611 MEM_TEST("prfm pldl2keep, [x5,w6,uxtw #0]", 12, 4);
1612 MEM_TEST("prfm pldl2strm, [x5,w6,uxtw #3]", 12, 4);
1613 MEM_TEST("prfm pldl3keep, [x5,w6,sxtw #0]", 12, 4);
1614 MEM_TEST("prfm pldl3strm, [x5,w6,sxtw #3]",  12, -4);
1615 
1616 MEM_TEST("prfm pstl1keep, [x5,x6]",  12, -4);
1617 MEM_TEST("prfm pstl1strm, [x5,x6, lsl #3]",  12, -4);
1618 MEM_TEST("prfm pstl2keep, [x5,w6,uxtw #0]", 12, 4);
1619 MEM_TEST("prfm pstl2strm, [x5,w6,uxtw #3]", 12, 4);
1620 MEM_TEST("prfm pstl3keep, [x5,w6,sxtw #0]", 12, 4);
1621 MEM_TEST("prfm pstl3strm, [x5,w6,sxtw #3]",  12, -4);
1622 
1623 ////////////////////////////////////////////////////////////////
1624 printf("LDPSW (immediate, simm7)\n");
1625 MEM_TEST("ldpsw x13, x23, [x5], #-24",   0, 0);
1626 MEM_TEST("ldpsw x13, x23, [x5, #-40]!",  0, 0);
1627 MEM_TEST("ldpsw x13, x23, [x5, #-40]",   0, 0);
1628 
1629 } /* end of test_memory2() */
1630 
1631 ////////////////////////////////////////////////////////////////
1632 ////////////////////////////////////////////////////////////////
1633 ////////////////////////////////////////////////////////////////
1634 ////////////////////////////////////////////////////////////////
1635 ////////////////////////////////////////////////////////////////
1636 ////////////////////////////////////////////////////////////////
1637 
1638 int main ( void )
1639 {
1640   if (1) test_memory_old();
1641   if (1) test_memory_new();
1642   return 0;
1643 }
1644