| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsExpandPseudo.cpp | 89 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in ExpandBuildPairF64() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCopyToCombine.cpp | 783 unsigned HiReg = HiOperand.getReg(); in emitCombineRI() local
834 unsigned HiReg = HiOperand.getReg(); in emitCombineRR() local
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| D | HexagonFrameLowering.cpp | 826 unsigned HiReg = HRI.getSubReg(Reg, Hexagon::subreg_hireg); in insertCFIInstructionsAt() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonCopyToCombine.cpp | 812 unsigned HiReg = HiOperand.getReg(); in emitCombineRI() local
863 unsigned HiReg = HiOperand.getReg(); in emitCombineRR() local
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| D | HexagonFrameLowering.cpp | 946 unsigned HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi); in insertCFIInstructionsAt() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 651 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| D | MipsSEFrameLowering.cpp | 285 unsigned HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 813 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| D | MipsSEFrameLowering.cpp | 310 unsigned HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 363 unsigned HiReg = MRI.createVirtualRegister(RC); in selectG_CONSTANT() local
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 1884 unsigned LoReg, HiReg; in Select() local
1984 unsigned LoReg, HiReg, ClrReg; in Select() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 497 unsigned HiReg = MI.getOperand(1).getReg(); in emitSplitF64Pseudo() local
530 unsigned HiReg = MI.getOperand(2).getReg(); in emitBuildPairF64Pseudo() local
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2184 unsigned SrcReg, LoReg, HiReg; in Select() local
2341 unsigned LoReg, HiReg, ClrReg; in Select() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2967 unsigned SrcReg, LoReg, HiReg; in Select() local
3096 unsigned LoReg, HiReg, ClrReg; in Select() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 3965 unsigned HiReg, bool &containsReg) { in checkLowRegisterList()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 6102 unsigned Reg, unsigned HiReg, in checkLowRegisterList()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 6287 unsigned Reg, unsigned HiReg, in checkLowRegisterList()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 9054 unsigned HiReg = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 10386 unsigned HiReg = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
|