| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-operand-rn-ror-amount-a32.cc | 74 ShiftType ror; member
1345 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
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| D | test-assembler-cond-rd-operand-rn-ror-amount-t32.cc | 74 ShiftType ror; member
1233 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
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| D | test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc | 75 ShiftType ror; member
5135 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
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| D | test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc | 75 ShiftType ror; member
5135 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
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| D | test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 139 ShiftType ror; member
597 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
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| D | test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 139 ShiftType ror; member
597 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
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| D | test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc | 140 ShiftType ror; member
1131 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
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| D | test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc | 140 ShiftType ror; member
1131 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
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| /external/capstone/arch/AArch64/ |
| D | AArch64AddressingModes.h | 119 static inline uint64_t ror(uint64_t elt, unsigned size) in ror() function
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| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.cc | 639 static inline uint32_t ror(uint32_t x, int i) { in ror() function
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| D | assembler-aarch32.h | 2889 void ror(Register rd, Register rm, const Operand& operand) { in ror() function
2892 void ror(Condition cond, Register rd, Register rm, const Operand& operand) { in ror() function
2895 void ror(EncodingSize size, in ror() function
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| D | assembler-aarch32.cc | 8927 void Assembler::ror(Condition cond, in ror() function in vixl::aarch32::Assembler
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| D | disasm-aarch32.cc | 2288 void Disassembler::ror(Condition cond, in ror() function in vixl::aarch32::Disassembler
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 31 ror, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 32 ror, enumerator
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 32 ror, enumerator
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 205 static inline uint64_t ror(uint64_t elt, unsigned size) { in ror() function
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | intel_tiled_memcpy.c | 62 ror(uint32_t n, uint32_t d) in ror() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 205 static inline uint64_t ror(uint64_t elt, unsigned size) { in ror() function
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 902 void ror(const Register& rd, const Register& rs, unsigned shift) { in ror() function
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| /external/v8/src/arm64/ |
| D | assembler-arm64.h | 1510 void ror(const Register& rd, const Register& rs, unsigned shift) { in ror() function
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| /external/v8/src/ia32/ |
| D | assembler-ia32.h | 735 void ror(Register dst, uint8_t imm8) { ror(Operand(dst), imm8); } in ror() function
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| D | assembler-ia32.cc | 1144 void Assembler::ror(Operand dst, uint8_t imm8) { in ror() function in v8::internal::Assembler
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| /external/v8/src/compiler/ia32/ |
| D | code-generator-ia32.cc | 1176 __ ror(i.OutputOperand(), i.InputInt5(1)); in AssembleArchInstruction() local
|