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/external/libxml2/VxWorks/
Dbuild.sh17 rm -fR src
24 find . -name '*.in' -exec rm -fR {} +
25 find . -name '*.am' -exec rm -fR {} +
26 rm -fR *.m4
27 rm -fR *.pc
28 rm -fR *.pl
29 rm -fR *.py
30 rm -fR *.spec
31 rm -fR .deps
32 rm -fR AUTHORS
[all …]
/external/vixl/src/aarch32/
Dassembler-aarch32.h264 QRegister rm);
277 typedef void (Assembler::*InstructionCondR)(Condition cond, Register rm);
282 Register rm);
290 Register rm);
325 Condition cond, Register rd, Register rn, Register rm, Register ra);
332 Condition cond, EncodingSize size, Register rd, Register rn, Register rm);
346 Register rm);
350 QRegister rm);
368 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
370 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
[all …]
Dmacro-assembler-aarch32.h997 // ADC<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 in Adc()
1074 // ADD<c>{<q>} <Rd>, <Rn>, <Rm> in Add()
1077 // ADD<c>{<q>} <Rdn>, <Rm> ; T2 in Add()
1171 // AND<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 in And()
1229 void Asr(Condition cond, Register rd, Register rm, const Operand& operand) { in Asr() argument
1231 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); in Asr()
1237 // ASR<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2 in Asr()
1239 (operand.GetImmediate() <= 32) && rd.IsLow() && rm.IsLow()) || in Asr()
1241 (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() && in Asr()
1244 asr(cond, rd, rm, operand); in Asr()
[all …]
Ddisasm-aarch32.h657 Register rm,
663 Register rm,
691 void blx(Condition cond, Register rm);
693 void bx(Condition cond, Register rm);
695 void bxj(Condition cond, Register rm);
703 void clz(Condition cond, Register rd, Register rm);
715 void crc32b(Condition cond, Register rd, Register rn, Register rm);
717 void crc32cb(Condition cond, Register rd, Register rn, Register rm);
719 void crc32ch(Condition cond, Register rd, Register rn, Register rm);
721 void crc32cw(Condition cond, Register rd, Register rn, Register rm);
[all …]
Dassembler-aarch32.cc1956 Register rm = operand.GetBaseRegister(); in adc() local
1959 // ADC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 in adc()
1961 rm.IsLow()) { in adc()
1962 EmitT32_16(0x4140 | rd.GetCode() | (rm.GetCode() << 3)); in adc()
1971 // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 in adc()
1973 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in adc()
1976 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) | in adc()
1982 // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 in adc()
1986 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in adc()
1993 Register rm = operand.GetBaseRegister(); in adc() local
[all …]
/external/vixl/test/aarch32/config/
Dcond-rd-rn-rm-a32.json28 // MNEMONIC<c> <rd>, <rn>, <rm>
35 "Mul", // MUL{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; A1
36 "Muls", // MULS{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; A1
37 "Qadd16", // QADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
38 "Qadd8", // QADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
39 "Qasx", // QASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
40 "Qsax", // QSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
41 "Qsub16", // QSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
42 "Qsub8", // QSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
43 "Sdiv", // SDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
[all …]
Dcond-rd-rn-rm-t32.json28 // MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>
35 "Mul", // MUL{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; T2
36 "Qadd16", // QADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
37 "Qadd8", // QADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
38 "Qasx", // QASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
39 "Qsax", // QSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
40 "Qsub16", // QSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
41 "Qsub8", // QSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
42 "Sdiv", // SDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
43 "Shadd16", // SHADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
[all …]
Dcond-rd-rn-operand-rm-t32.json28 // MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>
29 // MNEMONIC{<c>}.W <Rd>, SP, <Rm>
30 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> }
31 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> }
34 // MNEMONIC{<c>}.N SP, SP, <Rm>
35 // MNEMONIC{<c>}.N <Rd>, <Rn>, <Rm>
36 // MNEMONIC{<c>}.N <Rdn>, <Rdn>, <Rm> ; rm is not SP
37 // MNEMONIC{<c>}.N <Rdn>, <Rdn>, <Rm> ; low registers
41 // "cond-rd-rn-operand-rm-shift-amount-*-t32.json".
45 "Adc", // ADC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
[all …]
Dcond-rd-memop-rs-a32.json29 "Ldr", // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
30 // LDR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
31 // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
32 "Ldrb", // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
33 // LDRB{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
34 // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
35 "Ldrh", // LDRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1
36 // LDRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<Rm> ; A1
37 // LDRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>]! ; A1
38 "Ldrsb", // LDRSB{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1
[all …]
Dcond-rd-rn-operand-rm-a32.json28 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rm>, <Rs>
29 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> }
30 // MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> }
34 // "cond-rd-rn-operand-rm-shift-amount-*-a32.json".
38 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
39 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
40 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
41 // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
42 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
43 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
[all …]
Dcond-rd-memop-rs-shift-amount-1to31-a32.json29 "Ldr", // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
30 // LDR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
31 // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
32 "Ldrb", // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
33 // LDRB{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
34 // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
35 "Str", // STR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
36 // STR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
37 // STR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
38 "Strb" // STRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
[all …]
Dcond-rd-rn-operand-rm-shift-rs-a32.json29 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
31 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
32 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
33 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
34 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
35 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
36 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
37 "Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
38 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
[all …]
Dcond-rd-rn-operand-rm-shift-amount-1to32-t32.json28 // MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>, ASR|LSR #<amount>
29 // MNEMONIC{<c>}.W <Rd>, SP, <Rm>, ASR|LSR #<amount>
33 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
34 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
35 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
36 // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
37 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
38 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
39 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
40 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
[all …]
Dcond-rd-rn-operand-rm-shift-amount-1to31-t32.json28 // MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>, LSL|ROR #<amount>
29 // MNEMONIC{<c>}.W <Rd>, SP, <Rm>, LSL|ROR #<amount>
33 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
34 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
35 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
36 // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
37 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
38 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
39 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
40 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
[all …]
Dcond-rd-rn-operand-rm-shift-amount-1to32-a32.json29 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
31 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
32 // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
33 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
34 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
35 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
36 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
37 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
38 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
[all …]
Dcond-rd-rn-operand-rm-shift-amount-1to31-a32.json29 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
31 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
32 // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
33 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
34 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
35 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
36 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
37 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
38 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
[all …]
Dcond-rd-memop-rs-shift-amount-1to32-a32.json57 "name": "rm",
85 "name": "rm",
101 "cond", "rd", "rn", "rm"
108 "rn", "sign", "rm", "shift", "amount", "addr_mode"
116 "rd", "rn", "sign", "rm", "shift", "amount", "addr_mode"
131 "cond", "rd", "rn", "rm"
133 "operand-filter": "rd == 'r0' and rn == 'r1' and rm == 'r8'",
141 "rd", "rn", "sign", "rm", "shift", "amount", "addr_mode"
143 …operand-filter": "sign == 'plus' and addr_mode == 'Offset' and rd != rm and rd != rn and rn != rm",
146 "memop", "rm"
[all …]
Drd-rn-rm.json28 // MNEMONIC <Rd>, <Rn>, <Rm>
32 "Crc32b", // CRC32B{<q>} <Rd>, <Rn>, <Rm> ; A1
33 // CRC32B{<q>} <Rd>, <Rn>, <Rm> ; T1
34 "Crc32cb", // CRC32CB{<q>} <Rd>, <Rn>, <Rm> ; A1
35 // CRC32CB{<q>} <Rd>, <Rn>, <Rm> ; T1
36 "Crc32ch", // CRC32CH{<q>} <Rd>, <Rn>, <Rm> ; A1
37 // CRC32CH{<q>} <Rd>, <Rn>, <Rm> ; T1
38 "Crc32cw", // CRC32CW{<q>} <Rd>, <Rn>, <Rm> ; A1
39 // CRC32CW{<q>} <Rd>, <Rn>, <Rm> ; T1
40 "Crc32h", // CRC32H{<q>} <Rd>, <Rn>, <Rm> ; A1
[all …]
Dcond-rd-rn-operand-rm-ror-amount-t32.json28 // MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>, ROR #<amount>
32 "Sxtab", // SXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
33 "Sxtab16", // SXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
34 "Sxtah", // SXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
35 "Uxtab", // UXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
36 "Uxtab16", // UXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
37 "Uxtah" // UXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
58 "name": "rm",
86 "name": "rm",
98 "cond", "rd", "rn", "rm", "ror", "amount"
[all …]
/external/python/cpython3/Tools/unicode/
DMakefile12 RM = /bin/rm macro
32 $(RM) build/atarist.*
33 $(RM) build/us_ascii_quotes.*
34 $(RM) build/ibmgraph.*
35 $(RM) build/sgml.*
36 $(RM) -f build/readme.*
43 $(RM) build/cp9*
44 $(RM) -f build/readme.*
48 $(RM) -f build/isoreadme.*
52 $(RM) build/mac_dingbats.*
[all …]
/external/python/cpython2/Tools/unicode/
DMakefile12 RM = /bin/rm macro
32 $(RM) build/atarist.*
33 $(RM) build/us_ascii_quotes.*
34 $(RM) build/ibmgraph.*
35 $(RM) build/sgml.*
36 $(RM) -f build/readme.*
43 $(RM) build/cp9*
44 $(RM) -f build/readme.*
48 $(RM) -f build/isoreadme.*
52 $(RM) build/mac_dingbats.*
[all …]
/external/syzkaller/pkg/ifuzz/generated/
Dinsns.go10 …{Name: "FADD", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: -3, Rm: -1, Mem…
11 …{Name: "FMUL", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: -3, Reg: 1, Rm:…
12 …{Name: "FCOMP", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: -3, Reg: 3, Rm…
13 …{Name: "FSUB", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: -3, Reg: 4, Rm:…
14 …{Name: "FSUBR", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: -3, Reg: 5, Rm…
15 …{Name: "FDIV", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: -3, Reg: 6, Rm:…
16 …{Name: "FDIVR", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: -3, Reg: 7, Rm…
17 …{Name: "FADD", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: 3, Rm: -1, VexP…
18 …{Name: "FMUL", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: 3, Reg: 1, Rm: …
19 …{Name: "FCOM", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: -3, Reg: 2, Rm:…
[all …]
/external/syzkaller/pkg/ifuzz/gen/
Dall-enc-instructions.txt32 PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
42 PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
52 PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
62 PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
72 PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
82 PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
92 PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
102 PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
112 PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
122 PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
[all …]
/external/toybox/tests/
Drm.test11 testing "text-file" "rm file.txt && [ ! -e file.txt ] && echo 'yes'" "yes\n" "" ""
12 rm -f file*
15 testing "empty directory" "rm -r dir && [ ! -d dir ] && echo 'yes'" "yes\n" "" ""
16 rm -rf dir
19 testing "text file(mode 000)" "rm -f file.txt && [ ! -e file.txt ] && echo 'yes'" \
21 rm -f file*
26 "rm -r file1.txt file2.txt dir1 dir2 2>/dev/null &&
29 rm -rf file* dir*
34 "rm -rf file1.txt file2.txt file3.txt dir1 dir2 dir3 2>/dev/null &&
37 rm -rf file* dir*
[all …]
Dchmod.test36 rm -rf "./$type" && mkdir $type
40 rm -f "./$type" && touch $type
50 rm -rf dir file && mkdir dir && touch file
55 rm -rf dir file && mkdir dir && touch file
60 rm -rf dir file && mkdir dir && touch file
65 rm -rf dir file && mkdir dir && touch file
69 rm -rf dir file && mkdir dir && touch file
73 rm -rf dir file && mkdir dir && touch file
77 rm -rf dir file && mkdir dir && touch file
81 rm -rf dir file && mkdir dir && touch file
[all …]

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