| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenCallingConv.inc | 54 if (unsigned Reg = State.AllocateReg(ARM::R12)) {
82 if (unsigned Reg = State.AllocateReg(ARM::R10)) {
91 if (unsigned Reg = State.AllocateReg(ARM::R8)) {
140 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
152 if (unsigned Reg = State.AllocateReg(RegList3)) {
252 if (unsigned Reg = State.AllocateReg(ARM::R10)) {
261 if (unsigned Reg = State.AllocateReg(ARM::R8)) {
277 if (unsigned Reg = State.AllocateReg(RegList1)) {
287 if (unsigned Reg = State.AllocateReg(RegList2)) {
297 if (unsigned Reg = State.AllocateReg(RegList3)) {
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86GenCallingConv.inc | 134 if (unsigned Reg = State.AllocateReg(X86::ECX)) {
146 if (unsigned Reg = State.AllocateReg(RegList1, 3)) {
178 if (unsigned Reg = State.AllocateReg(RegList1, 3)) {
192 if (unsigned Reg = State.AllocateReg(RegList2, 3)) {
229 if (unsigned Reg = State.AllocateReg(RegList6, 4)) {
247 if (unsigned Reg = State.AllocateReg(RegList7, 4)) {
308 if (unsigned Reg = State.AllocateReg(X86::EAX)) {
318 if (unsigned Reg = State.AllocateReg(RegList1, 2)) {
331 if (unsigned Reg = State.AllocateReg(RegList2, 3)) {
368 if (unsigned Reg = State.AllocateReg(X86::EAX)) {
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenCallingConv.inc | 179 if (unsigned Reg = State.AllocateReg(RegList1)) {
191 if (unsigned Reg = State.AllocateReg(RegList2)) {
203 if (unsigned Reg = State.AllocateReg(RegList3)) {
215 if (unsigned Reg = State.AllocateReg(RegList4)) {
237 if (unsigned Reg = State.AllocateReg(RegList6)) {
250 if (unsigned Reg = State.AllocateReg(RegList7)) {
263 if (unsigned Reg = State.AllocateReg(RegList8)) {
271 if (unsigned Reg = State.AllocateReg(X86::K1)) {
389 if (unsigned Reg = State.AllocateReg(X86::ECX)) {
401 if (unsigned Reg = State.AllocateReg(RegList1)) {
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenCallingConv.inc | 81 if (unsigned Reg = State.AllocateReg(AArch64::X8, AArch64::W8)) {
94 if (unsigned Reg = State.AllocateReg(AArch64::X18)) {
102 if (unsigned Reg = State.AllocateReg(AArch64::X20, AArch64::W20)) {
111 if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
142 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
156 if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
181 if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
194 if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
207 if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
220 if (unsigned Reg = State.AllocateReg(RegList13, RegList14)) {
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.h | 34 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
49 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList); in f64AssignAAPCS()
83 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
102 unsigned T = State.AllocateReg(LoRegList[i]); in f64AssignAAPCS()
129 unsigned Reg = State.AllocateReg(HiRegList, LoRegList); in f64RetAssign()
216 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
256 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); in CC_ARM_AAPCS_Custom_Aggregate()
267 State.AllocateReg(Reg); in CC_ARM_AAPCS_Custom_Aggregate()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.h | 34 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
49 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList); in f64AssignAAPCS()
83 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
102 unsigned T = State.AllocateReg(LoRegList[i]); in f64AssignAAPCS()
129 unsigned Reg = State.AllocateReg(HiRegList, LoRegList); in f64RetAssign()
216 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
259 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); in CC_ARM_AAPCS_Custom_Aggregate()
270 State.AllocateReg(Reg); in CC_ARM_AAPCS_Custom_Aggregate()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86CallingConv.cpp | 47 unsigned Reg = State.AllocateReg(AvailableRegs[I]); in CC_X86_32_RegCall_Assign2Regs()
98 unsigned AssigedReg = State.AllocateReg(Reg); in CC_X86_VectorCallAssignRegister()
137 (void)State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT)); in CC_X86_64_VectorCall()
145 (void)State.AllocateReg(CC_X86_64_VectorCallGetGPRs()); in CC_X86_64_VectorCall()
148 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) { in CC_X86_64_VectorCall()
191 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) { in CC_X86_32_VectorCall()
|
| D | X86CallingConv.h | 86 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_X86_32_MCUInReg()
107 It.convertToReg(State.AllocateReg(RegList[FirstFree++])); in CC_X86_32_MCUInReg()
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMCallingConv.h | 35 if (unsigned Reg = State.AllocateReg(RegList, 4)) in f64AssignAPCS()
50 if (unsigned Reg = State.AllocateReg(RegList, 4)) in f64AssignAPCS()
79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2); in f64AssignAAPCS()
97 unsigned T = State.AllocateReg(LoRegList[i]); in f64AssignAAPCS()
124 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); in f64RetAssign()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenCallingConv.inc | 99 if (unsigned Reg = State.AllocateReg(RegList1)) {
158 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
171 if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
184 if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
215 if (unsigned Reg = State.AllocateReg(RegList1)) {
225 if (unsigned Reg = State.AllocateReg(RegList2)) {
252 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
302 if (unsigned Reg = State.AllocateReg(RegList1)) {
313 if (unsigned Reg = State.AllocateReg(RegList2)) {
396 if (unsigned Reg = State.AllocateReg(RegList1)) {
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 111 CCInfo.AllocateReg(PrivateSegmentBufferReg); in lowerFormalArguments()
117 CCInfo.AllocateReg(DispatchPtrReg); in lowerFormalArguments()
123 CCInfo.AllocateReg(QueuePtrReg); in lowerFormalArguments()
133 CCInfo.AllocateReg(InputPtrReg); in lowerFormalArguments()
139 CCInfo.AllocateReg(DispatchIDReg); in lowerFormalArguments()
145 CCInfo.AllocateReg(FlatScratchInitReg); in lowerFormalArguments()
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 242 unsigned AllocateReg(unsigned Reg) { in AllocateReg() function
249 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { in AllocateReg() function
259 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { in AllocateReg() function
271 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, in AllocateReg() function
|
| /external/llvm/lib/Target/X86/ |
| D | X86CallingConv.h | 72 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_X86_32_MCUInReg()
93 It.convertToReg(State.AllocateReg(RegList[FirstFree++])); in CC_X86_32_MCUInReg()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 342 unsigned AllocateReg(unsigned Reg) { in AllocateReg() function
349 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { in AllocateReg() function
359 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() function
400 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg() function
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 353 unsigned AllocateReg(unsigned Reg) { in AllocateReg() function
360 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { in AllocateReg() function
370 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() function
411 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg() function
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZCallingConv.h | 111 unsigned Reg = State.AllocateReg(SystemZ::ArgGPRs); in CC_SystemZ_I128Indirect()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZCallingConv.h | 111 unsigned Reg = State.AllocateReg(SystemZ::ArgGPRs); in CC_SystemZ_I128Indirect()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 678 CCInfo.AllocateReg(AMDGPU::VGPR0); in LowerFormalArguments()
679 CCInfo.AllocateReg(AMDGPU::VGPR1); in LowerFormalArguments()
702 CCInfo.AllocateReg(PrivateSegmentBufferReg); in LowerFormalArguments()
708 CCInfo.AllocateReg(DispatchPtrReg); in LowerFormalArguments()
714 CCInfo.AllocateReg(QueuePtrReg); in LowerFormalArguments()
720 CCInfo.AllocateReg(InputPtrReg); in LowerFormalArguments()
726 CCInfo.AllocateReg(FlatScratchInitReg); in LowerFormalArguments()
823 CCInfo.AllocateReg(Reg); in LowerFormalArguments()
829 CCInfo.AllocateReg(Reg); in LowerFormalArguments()
835 CCInfo.AllocateReg(Reg); in LowerFormalArguments()
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1746 State.AllocateReg(IntRegs[r]); in CC_MipsO32()
1772 Reg = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
1776 Reg = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
1781 Reg = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
1783 Reg = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
1784 State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
1789 Reg = State.AllocateReg(F32Regs, FloatRegsSize); in CC_MipsO32()
1791 State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
1793 Reg = State.AllocateReg(F64Regs, FloatRegsSize); in CC_MipsO32()
1795 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.h | 128 State.AllocateReg(Reg); in CC_AArch64_Custom_Block()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.h | 128 State.AllocateReg(Reg); in CC_AArch64_Custom_Block()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 2696 Reg = State.AllocateReg(FloatVectorIntRegs); in CC_MipsO32()
2698 State.AllocateReg(Mips::A1); in CC_MipsO32()
2700 State.AllocateReg(Mips::A3); in CC_MipsO32()
2704 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2707 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2711 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2716 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2718 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2719 State.AllocateReg(IntRegs); in CC_MipsO32()
2724 Reg = State.AllocateReg(F32Regs); in CC_MipsO32()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 664 if (unsigned Reg = State.AllocateReg(ArgGPRs)) { in CC_RISCVAssign2XLen()
681 if (unsigned Reg = State.AllocateReg(ArgGPRs)) { in CC_RISCVAssign2XLen()
725 State.AllocateReg(ArgGPRs); in CC_RISCV()
743 unsigned Reg = State.AllocateReg(ArgGPRs); in CC_RISCV()
751 if (!State.AllocateReg(ArgGPRs)) in CC_RISCV()
785 unsigned Reg = State.AllocateReg(ArgGPRs); in CC_RISCV()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 280 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_Hexagon32()
294 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { in CC_Hexagon64()
305 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) { in CC_Hexagon64()
339 if (unsigned Reg = State.AllocateReg(VecLstS)) { in CC_HexagonVector()
350 if (unsigned Reg = State.AllocateReg(VecLstD)) { in CC_HexagonVector()
362 if (unsigned Reg = State.AllocateReg(VecLstD)) { in CC_HexagonVector()
373 if (unsigned Reg = State.AllocateReg(VecLstS)) { in CC_HexagonVector()
450 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) { in RetCC_Hexagon32()
465 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { in RetCC_Hexagon64()
486 if (unsigned Reg = State.AllocateReg(Hexagon::V0)) { in RetCC_HexagonVector()
[all …]
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 2498 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2502 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2507 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2509 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2510 State.AllocateReg(IntRegs); in CC_MipsO32()
2515 Reg = State.AllocateReg(F32Regs); in CC_MipsO32()
2517 State.AllocateReg(IntRegs); in CC_MipsO32()
2519 Reg = State.AllocateReg(F64Regs); in CC_MipsO32()
2521 unsigned Reg2 = State.AllocateReg(IntRegs); in CC_MipsO32()
2523 State.AllocateReg(IntRegs); in CC_MipsO32()
[all …]
|