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Searched refs:AltOrders (Results 1 – 16 of 16) sorted by relevance

/external/llvm/lib/Target/ARM/
DARMRegisterInfo.td200 let AltOrders = [(add LR, GPR), (trunc GPR, 8)];
210 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
220 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
238 let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
256 let AltOrders = [(and tcGPR, tGPR)];
273 let AltOrders = [(add (decimate SPR, 2), SPR),
295 let AltOrders = [(rotl DPR, 16),
316 let AltOrders = [(rotl QPR, 8)];
342 let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16))];
377 let AltOrders = [(rotl QQPR, 8)];
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMRegisterInfo.td212 let AltOrders = [(add LR, GPR), (trunc GPR, 8)];
223 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
234 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
255 let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
282 let AltOrders = [(and tcGPR, tGPR)];
299 let AltOrders = [(add (decimate SPR, 2), SPR),
311 let AltOrders = [(add (decimate HPR, 2), SPR),
336 let AltOrders = [(rotl DPR, 16),
362 let AltOrders = [(rotl QPR, 8)];
393 let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16))];
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMRegisterInfo.td212 let AltOrders = [(add LR, GPR), (trunc GPR, 8)];
222 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
240 let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
258 let AltOrders = [(and tcGPR, tGPR)];
278 let AltOrders = [(rotl DPR, 16)];
301 let AltOrders = [(rotl QPR, 8)];
325 let AltOrders = [(rotl QQPR, 4)];
344 let AltOrders = [(rotl QQQQPR, 2)];
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td238 let AltOrders = [(add (sub GPRC, R2), R2)];
250 let AltOrders = [(add (sub G8RC, X2), X2)];
263 let AltOrders = [(add (sub GPRC_NOR0, R2), R2)];
273 let AltOrders = [(add (sub G8RC_NOX0, X2), X2)];
/external/swiftshader/third_party/LLVM/utils/TableGen/
DCodeGenRegisters.cpp278 ListInit *AltOrders = R->getValueAsListInit("AltOrders"); in CodeGenRegisterClass() local
279 Orders.resize(1 + AltOrders->size()); in CodeGenRegisterClass()
289 for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) { in CodeGenRegisterClass()
290 RegBank.getSets().evaluate(AltOrders->getElement(i), Order); in CodeGenRegisterClass()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td256 let AltOrders = [(add (sub GPRC, R2), R2)];
268 let AltOrders = [(add (sub G8RC, X2), X2)];
281 let AltOrders = [(add (sub GPRC_NOR0, R2), R2)];
291 let AltOrders = [(add (sub G8RC_NOX0, X2), X2)];
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td131 let AltOrders = [(rotl GPR32common, 8)];
136 let AltOrders = [(rotl GPR64common, 8)];
141 let AltOrders = [(rotl GPR32, 8)];
145 let AltOrders = [(rotl GPR64, 8)];
151 let AltOrders = [(rotl GPR32sp, 8)];
155 let AltOrders = [(rotl GPR64sp, 8)];
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td140 let AltOrders = [(rotl GPR32common, 8)];
145 let AltOrders = [(rotl GPR64common, 8)];
150 let AltOrders = [(rotl GPR32, 8)];
154 let AltOrders = [(rotl GPR64, 8)];
160 let AltOrders = [(rotl GPR32sp, 8)];
164 let AltOrders = [(rotl GPR64sp, 8)];
/external/llvm/utils/TableGen/
DCodeGenRegisters.cpp677 ListInit *AltOrders = R->getValueAsListInit("AltOrders"); in CodeGenRegisterClass() local
678 Orders.resize(1 + AltOrders->size()); in CodeGenRegisterClass()
691 for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) { in CodeGenRegisterClass()
692 RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc()); in CodeGenRegisterClass()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenRegisters.cpp750 ListInit *AltOrders = R->getValueAsListInit("AltOrders"); in CodeGenRegisterClass() local
751 Orders.resize(1 + AltOrders->size()); in CodeGenRegisterClass()
766 for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) { in CodeGenRegisterClass()
767 RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc()); in CodeGenRegisterClass()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86RegisterInfo.td291 let AltOrders = [(sub GR8, AH, BH, CH, DH)];
369 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td331 let AltOrders = [(sub GR8, AH, BH, CH, DH)];
383 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTarget.td153 // AltOrders - List of alternative allocation orders. The default order is
157 list<dag> AltOrders = [];
166 // MemberList, 1 to select the first AltOrders entry and so on.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86RegisterInfo.td383 let AltOrders = [(sub GR8, AH, BH, CH, DH)];
448 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
/external/llvm/include/llvm/Target/
DTarget.td195 // AltOrders - List of alternative allocation orders. The default order is
199 list<dag> AltOrders = [];
208 // MemberList, 1 to select the first AltOrders entry and so on.
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTarget.td253 // AltOrders - List of alternative allocation orders. The default order is
257 list<dag> AltOrders = [];
266 // MemberList, 1 to select the first AltOrders entry and so on.