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Searched refs:DoubleRegs (Results 1 – 25 of 25) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td101 def : Pat<(i64 (selectcc DoubleRegs:$lhs, DoubleRegs:$rhs, DoubleRegs:$tval,
102 DoubleRegs:$fval, SETGT)),
103 (COMBINE_rr (MUX_rr (CMPGT64rr DoubleRegs:$lhs, DoubleRegs:$rhs),
104 (EXTRACT_SUBREG DoubleRegs:$tval, subreg_hireg),
105 (EXTRACT_SUBREG DoubleRegs:$fval, subreg_hireg)),
106 (MUX_rr (CMPGT64rr DoubleRegs:$lhs, DoubleRegs:$rhs),
107 (EXTRACT_SUBREG DoubleRegs:$tval, subreg_loreg),
108 (EXTRACT_SUBREG DoubleRegs:$fval, subreg_loreg)))>;
112 def : Pat<(i64 (selectcc DoubleRegs:$lhs, DoubleRegs:$rhs, DoubleRegs:$tval,
113 DoubleRegs:$fval, SETLT)),
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DHexagonIntrinsicsDerived.td14 def : Pat <(mul DoubleRegs:$src1, DoubleRegs:$src2),
22 (M2_dpmpyuu_s0 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
24 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
27 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
28 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))),
29 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)),
30 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg))),
35 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
36 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
DHexagonInstrInfoV3.td107 def A2_addsp : ALU64_rr<(outs DoubleRegs:$Rd),
108 (ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)",
109 [(set (i64 DoubleRegs:$Rd), (i64 (add (i64 (sext (i32 IntRegs:$Rs))),
110 (i64 DoubleRegs:$Rt))))],
116 : ALU64Inst<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rt, DoubleRegs:$Rs),
141 defm: T_MinMax_pats<Op, DoubleRegs, i64, Inst, SwapInst>;
200 MInst<(outs DoubleRegs:$Rdd),
201 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
223 : MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
229 MInst <(outs DoubleRegs:$Rxx),
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DHexagonInstrInfoVector.td19 def V8I8: PatLeaf<(v8i8 DoubleRegs:$R)>;
20 def V4I16: PatLeaf<(v4i16 DoubleRegs:$R)>;
21 def V2I32: PatLeaf<(v2i32 DoubleRegs:$R)>;
32 def : Pat <(b (bitconvert (a DoubleRegs:$src))),
33 (b DoubleRegs:$src)>;
34 def : Pat <(a (bitconvert (b DoubleRegs:$src))),
35 (a DoubleRegs:$src)>;
55 [(set (v4i16 DoubleRegs:$dst),
56 (Op (v4i16 DoubleRegs:$src1), u4ImmPred:$src2))]> {
63 [(set (v2i32 DoubleRegs:$dst),
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DHexagonInstrInfo.td24 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
26 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
239 let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0 in {
330 def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
332 [(set (i64 DoubleRegs:$Rdd),
568 : ALU32_rr <(outs DoubleRegs:$dst),
569 (ins PredRegs:$src1, DoubleRegs:$src2),
579 class T_tfrp : ALU32Inst <(outs DoubleRegs:$dst),
580 (ins DoubleRegs:$src),
649 def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
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DHexagonInstrAlias.td28 (S2_storerdgp u16_3Imm:$addr, DoubleRegs:$Nt)>;
41 (L2_loadrdgp DoubleRegs:$Nt, u16_3Imm:$addr)>;
75 (S2_storerd_io IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>;
112 (L2_loadrd_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
118 (L2_loadbzw4_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
124 (L2_loadbsw4_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
127 (L2_loadalignb_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
130 (L2_loadalignh_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
150 (L2_ploadrdt_io DoubleRegs:$Rdd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
167 (S2_pstorerdt_io PredRegs:$Pt, IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>;
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DHexagonInstrInfoV5.td57 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
82 def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1),
127 def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
259 : T_fcmp <mnemonic, DoubleRegs, MinOp,
291 // DoubleRegs
310 // DoubleRegs
340 // DoubleRegs
375 // DoubleRegs
532 : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
551 : SInst <(outs DoubleRegs:$Rdd), (ins IntRegs:$Rs),
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DHexagonIntrinsicsV4.td169 def : Pat <(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2,
171 (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2ImmPred:$src3)>;
175 def : Pat <(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
177 (S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
DHexagonInstrInfoV4.td296 : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
330 def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
432 def L4_loadbzw4_ap : T_LD_abs_set <"memubh", DoubleRegs, 0b0101>;
433 def L4_loadbsw4_ap : T_LD_abs_set <"membh", DoubleRegs, 0b0111>;
437 def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
440 def L4_loadalignb_ap : T_LD_abs_set <"memb_fifo", DoubleRegs, 0b0100>;
443 def L4_loadalignh_ap : T_LD_abs_set <"memh_fifo", DoubleRegs, 0b0010>;
458 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
476 DoubleRegs, 0b0100>;
485 DoubleRegs, 0b0010>;
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DHexagonIsetDx.td17 (outs DoubleRegs:$Rdd),
65 (outs DoubleRegs:$Rdd),
196 (outs DoubleRegs:$Rdd),
289 (outs DoubleRegs:$Rdd),
364 (outs DoubleRegs:$Rdd),
380 (outs DoubleRegs:$Rdd),
454 (outs DoubleRegs:$Rdd),
511 (ins s6_3Imm:$s6_3, DoubleRegs:$Rtt),
DHexagonSplitDouble.cpp203 BitVector DoubleRegs(NumRegs); in partitionRegisters() local
207 DoubleRegs.set(i); in partitionRegisters()
211 for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) { in partitionRegisters()
222 for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) { in partitionRegisters()
261 for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) { in partitionRegisters()
DHexagonSystemInst.td73 def Y5_l2fetch: ST_MISC_CACHEOP_SYS<(outs), (ins IntRegs:$Rs, DoubleRegs:$Rt),
DHexagonInstrInfoV60.td2100 : T_HVX_rol <asmString, DoubleRegs, u6Imm>;
2112 : T_HVX_rol_acc <asmString, DoubleRegs, u6Imm>;
2164 class T_sys1op_P <string asmString> : T_sys1op <asmString, DoubleRegs>;
2185 def A5_ACS : MInst2 <(outs DoubleRegs:$dst1, PredRegs:$dst2),
2186 (ins DoubleRegs:$_src_, DoubleRegs:$src1, DoubleRegs:$src2),
2276 : SInst2<(outs DoubleRegs:$dst),
2277 (ins DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3),
DHexagonRegisterInfo.td222 def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64,
DHexagonOperands.td599 def is_sext_i32 : PatLeaf<(i64 DoubleRegs:$src1), [{
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonMapAsm2IntrinV65.gen.td10 …at<(int_hexagon_A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2), (A6_vcmpbeq_notany DoubleRe…
33 def: Pat<(int_hexagon_V6_vlut4 HvxVR:$src1, DoubleRegs:$src2), (V6_vlut4 HvxVR:$src1, DoubleRegs:$s…
34 def: Pat<(int_hexagon_V6_vlut4_128B HvxVR:$src1, DoubleRegs:$src2), (V6_vlut4 HvxVR:$src1, DoubleRe…
41 …on_V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpahhsat HvxVR:$src1, HvxVR:$src…
42 …_vmpahhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpahhsat HvxVR:$src1, HvxVR:$src…
43 …V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$sr…
44 …pauhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$sr…
45 …V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$sr…
46 …psuhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$sr…
59 …: Pat<(int_hexagon_V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2), (V6_vrmpyub_rtt HvxVR:$src1, Dou…
[all …]
DHexagonDepInstrInfo.td25 (outs DoubleRegs:$Rdd32),
26 (ins DoubleRegs:$Rss32),
231 (outs DoubleRegs:$Rdd32),
232 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
242 (outs DoubleRegs:$Rdd32),
243 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
269 (outs DoubleRegs:$Rdd32),
270 (ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
276 (outs DoubleRegs:$Rdd32),
277 (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
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DHexagonPseudo.td15 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
17 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
35 def TFRI64_V2_ext : InstHexagon<(outs DoubleRegs:$dst),
68 def CONST64 : CONSTLDInst<(outs DoubleRegs:$Rd), (ins i64imm:$v),
332 def PS_pselect: InstHexagon<(outs DoubleRegs:$Rd),
333 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
483 def TFRI64_V4 : InstHexagon<(outs DoubleRegs:$dst),
493 def PS_vmulw : PseudoM<(outs DoubleRegs:$Rd),
494 (ins DoubleRegs:$Rs, DoubleRegs:$Rt), "", []>;
497 def PS_vmulw_acc : PseudoM<(outs DoubleRegs:$Rd),
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DHexagonIntrinsicsV4.td169 def : Pat <(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2,
171 (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred:$src3)>;
175 def : Pat <(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
177 (S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
DHexagonDepMappings.td19 …stAlias<"$Rdd32 = vaddb($Rss32,$Rtt32)", (A2_vaddub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRe…
20 …stAlias<"$Rdd32 = vsubb($Rss32,$Rtt32)", (A2_vsubub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRe…
30 def L2_loadalignb_zomapAlias : InstAlias<"$Ryy32 = memb_fifo($Rs32)", (L2_loadalignb_io DoubleRegs:…
31 def L2_loadalignh_zomapAlias : InstAlias<"$Ryy32 = memh_fifo($Rs32)", (L2_loadalignh_io DoubleRegs:…
33 def L2_loadbsw4_zomapAlias : InstAlias<"$Rdd32 = membh($Rs32)", (L2_loadbsw4_io DoubleRegs:$Rdd32, …
35 def L2_loadbzw4_zomapAlias : InstAlias<"$Rdd32 = memubh($Rs32)", (L2_loadbzw4_io DoubleRegs:$Rdd32,…
37 def L2_loadrd_zomapAlias : InstAlias<"$Rdd32 = memd($Rs32)", (L2_loadrd_io DoubleRegs:$Rdd32, IntRe…
46 …apAlias : InstAlias<"if (!$Pt4) $Rdd32 = memd($Rs32)", (L2_ploadrdf_io DoubleRegs:$Rdd32, PredRegs…
47 … : InstAlias<"if (!$Pt4.new) $Rdd32 = memd($Rs32)", (L2_ploadrdfnew_io DoubleRegs:$Rdd32, PredRegs…
48 def L2_ploadrdt_zomapAlias : InstAlias<"if ($Pt4) $Rdd32 = memd($Rs32)", (L2_ploadrdt_io DoubleRegs…
[all …]
DHexagonSplitDouble.cpp226 BitVector DoubleRegs(NumRegs); in partitionRegisters() local
230 DoubleRegs.set(i); in partitionRegisters()
234 for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) { in partitionRegisters()
245 for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) { in partitionRegisters()
284 for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) { in partitionRegisters()
DHexagonPatterns.td87 def V8I8: PatLeaf<(v8i8 DoubleRegs:$R)>;
88 def V4I16: PatLeaf<(v4i16 DoubleRegs:$R)>;
89 def V2I32: PatLeaf<(v2i32 DoubleRegs:$R)>;
223 (REG_SEQUENCE DoubleRegs, $Rs, isub_hi, $Rt, isub_lo)>;
392 defm: Cast_pat<v8i8, i64, DoubleRegs>;
393 defm: Cast_pat<v4i16, i64, DoubleRegs>;
394 defm: Cast_pat<v2i32, i64, DoubleRegs>;
1623 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>;
DHexagonRegisterInfo.td315 def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp146 static const MCPhysReg DoubleRegs[32] = { variable
422 Op.Reg.RegNum = DoubleRegs[regIdx / 2]; in MorphToDoubleReg()
1075 RegNo = DoubleRegs[intVal/2]; in matchRegisterName()
/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp121 static const MCPhysReg DoubleRegs[32] = { variable
394 Op.Reg.RegNum = DoubleRegs[regIdx / 2]; in MorphToDoubleReg()
1085 RegNo = DoubleRegs[intVal/2]; in matchRegisterName()