| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 150 bool IsStore; in EmitInstruction() local
152 &IsStore); in EmitInstruction()
158 bool MaskAfter = IsSPFirstOperand && !IsStore; in EmitInstruction()
203 bool *IsStore) { in isBasePlusOffsetMemoryAccess() argument
204 if (IsStore) in isBasePlusOffsetMemoryAccess()
205 *IsStore = false; in isBasePlusOffsetMemoryAccess()
235 if (IsStore) in isBasePlusOffsetMemoryAccess()
236 *IsStore = true; in isBasePlusOffsetMemoryAccess()
243 if (IsStore) in isBasePlusOffsetMemoryAccess()
244 *IsStore = true; in isBasePlusOffsetMemoryAccess()
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| D | MipsMCNaCl.h | 21 bool *IsStore = nullptr);
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 159 bool IsStore; in EmitInstruction() local
161 &IsStore); in EmitInstruction()
167 bool MaskAfter = IsSPFirstOperand && !IsStore; in EmitInstruction()
212 bool *IsStore) { in isBasePlusOffsetMemoryAccess() argument
213 if (IsStore) in isBasePlusOffsetMemoryAccess()
214 *IsStore = false; in isBasePlusOffsetMemoryAccess()
244 if (IsStore) in isBasePlusOffsetMemoryAccess()
245 *IsStore = true; in isBasePlusOffsetMemoryAccess()
252 if (IsStore) in isBasePlusOffsetMemoryAccess()
253 *IsStore = true; in isBasePlusOffsetMemoryAccess()
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| D | MipsMCNaCl.h | 21 bool *IsStore = nullptr);
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| /external/llvm/lib/Transforms/Instrumentation/ |
| D | EfficiencySanitizer.cpp | 196 bool instrumentFastpath(Instruction *I, const DataLayout &DL, bool IsStore,
650 bool IsStore; in instrumentLoadOrStore() local
654 IsStore = false; in instrumentLoadOrStore()
658 IsStore = true; in instrumentLoadOrStore()
662 IsStore = true; in instrumentLoadOrStore()
666 IsStore = true; in instrumentLoadOrStore()
680 if (IsStore) in instrumentLoadOrStore()
686 OnAccessFunc = IsStore ? EsanUnalignedStoreN : EsanUnalignedLoadN; in instrumentLoadOrStore()
692 instrumentFastpath(I, DL, IsStore, Addr, Alignment)) { in instrumentLoadOrStore()
697 OnAccessFunc = IsStore ? EsanAlignedStore[Idx] : EsanAlignedLoad[Idx]; in instrumentLoadOrStore()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Instrumentation/ |
| D | EfficiencySanitizer.cpp | 207 bool instrumentFastpath(Instruction *I, const DataLayout &DL, bool IsStore,
664 bool IsStore; in instrumentLoadOrStore() local
668 IsStore = false; in instrumentLoadOrStore()
672 IsStore = true; in instrumentLoadOrStore()
676 IsStore = true; in instrumentLoadOrStore()
680 IsStore = true; in instrumentLoadOrStore()
694 if (IsStore) in instrumentLoadOrStore()
700 OnAccessFunc = IsStore ? EsanUnalignedStoreN : EsanUnalignedLoadN; in instrumentLoadOrStore()
706 instrumentFastpath(I, DL, IsStore, Addr, Alignment)) { in instrumentLoadOrStore()
711 OnAccessFunc = IsStore ? EsanAlignedStore[Idx] : EsanAlignedLoad[Idx]; in instrumentLoadOrStore()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 79 unsigned int IsStore : 1; member
366 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
372 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
675 SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
691 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in recordUnoptimizableWebs()
699 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
764 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in markSwapsForRemoval()
969 if (SwapVector[EntryIdx].IsStore) in dumpSwapVector()
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| D | PPCISelLowering.h | 578 bool IsStore, bool IsLoad) const override;
580 bool IsStore, bool IsLoad) const override;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 80 unsigned int IsStore : 1; member
371 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
377 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
684 SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
700 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in recordUnoptimizableWebs()
708 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
774 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in markSwapsForRemoval()
986 if (SwapVector[EntryIdx].IsStore) in dumpSwapVector()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrFormats.td | 37 bit IsStore = 0;
53 let TSFlags{6-6} = IsStore;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrFormats.td | 37 bit IsStore = 0;
53 let TSFlags{6-6} = IsStore;
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 641 bit IsStore = ?;
925 let IsStore = 1;
930 let IsStore = 1;
937 let IsStore = 1;
942 let IsStore = 1;
947 let IsStore = 1;
952 let IsStore = 1;
957 let IsStore = 1;
962 let IsStore = 1;
968 let IsStore = 1;
[all …]
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| /external/llvm/lib/CodeGen/ |
| D | AtomicExpandPass.cpp | 51 bool IsStore, bool IsLoad);
227 bool IsStore, IsLoad; in runOnFunction() local
231 IsStore = false; in runOnFunction()
236 IsStore = true; in runOnFunction()
242 IsStore = IsLoad = true; in runOnFunction()
253 IsStore = IsLoad = true; in runOnFunction()
257 MadeChange |= bracketInstWithFences(I, FenceOrdering, IsStore, IsLoad); in runOnFunction()
324 bool IsStore, bool IsLoad) { in bracketInstWithFences() argument
327 auto LeadingFence = TLI->emitLeadingFence(Builder, Order, IsStore, IsLoad); in bracketInstWithFences()
329 auto TrailingFence = TLI->emitTrailingFence(Builder, Order, IsStore, IsLoad); in bracketInstWithFences()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | X86FoldTablesEmitter.cpp | 101 bool IsStore = false; member in __anon67ff85150111::X86FoldTablesEmitter::X86FoldTableEntry
116 if (E.IsStore) in operator <<()
462 Result.IsStore = true; in addEntryWithFlags()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 436 bool IsStore = Entry.WideOpc == ARM::t2STR_POST; in ReduceLoadStore() local
437 unsigned Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); in ReduceLoadStore()
438 unsigned Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore()
455 .addReg(Rt, IsStore ? 0 : RegState::Define); in ReduceLoadStore()
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| D | ARMISelLowering.h | 448 bool IsStore, bool IsLoad) const override;
450 bool IsStore, bool IsLoad) const override;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 466 bool IsStore = Entry.WideOpc == ARM::t2STR_POST; in ReduceLoadStore() local
467 unsigned Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); in ReduceLoadStore()
468 unsigned Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore()
485 .addReg(Rt, IsStore ? 0 : RegState::Define); in ReduceLoadStore()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 489 bool IsStore = MI->mayStore(); in buildMUBUFOffsetLoadStore() local
492 int LoadStoreOp = IsStore ? in buildMUBUFOffsetLoadStore()
533 bool IsStore = Desc.mayStore(); in buildSpillLoadStore() local
589 unsigned SrcDstRegState = getDefRegState(!IsStore); in buildSpillLoadStore()
602 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)) in buildSpillLoadStore()
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| /external/clang/lib/CodeGen/ |
| D | CGAtomic.cpp | 1020 bool IsStore = E->getOp() == AtomicExpr::AO__c11_atomic_store || in EmitAtomicExpr() local
1039 if (IsStore) in EmitAtomicExpr()
1051 if (IsLoad || IsStore) in EmitAtomicExpr()
1076 if (!IsStore) in EmitAtomicExpr()
1080 if (!IsLoad && !IsStore) in EmitAtomicExpr()
1097 if (!IsStore) { in EmitAtomicExpr()
1115 if (!IsLoad && !IsStore) { in EmitAtomicExpr()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 426 bool IsStore = MI->mayStore(); in buildScratchLoadStore() local
469 unsigned SrcDstRegState = getDefRegState(!IsStore); in buildScratchLoadStore()
477 .addReg(SubReg, getDefRegState(!IsStore)) in buildScratchLoadStore()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 258 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); in SimplifyShortMoveForm() local
259 unsigned AddrBase = IsStore; in SimplifyShortMoveForm()
260 unsigned RegOp = IsStore ? 0 : 5; in SimplifyShortMoveForm()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 821 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore(); in canMoveMemTo() local
822 if (!IsLoad && !IsStore) in canMoveMemTo()
844 bool Conflict = (L && IsStore) || S; in canMoveMemTo()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 822 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore(); in canMoveMemTo() local
823 if (!IsLoad && !IsStore) in canMoveMemTo()
845 bool Conflict = (L && IsStore) || S; in canMoveMemTo()
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| /external/vixl/src/aarch64/ |
| D | instructions-aarch64.cc | 79 bool Instruction::IsStore() const { in IsStore() function in vixl::aarch64::Instruction
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| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 1199 AtomicOrdering Ord, bool IsStore, in emitLeadingFence() argument
1201 if (isReleaseOrStronger(Ord) && IsStore) in emitLeadingFence()
1208 AtomicOrdering Ord, bool IsStore, in emitTrailingFence() argument
|