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Searched refs:Late (Results 1 – 25 of 37) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonLoopIdiomRecognition.cpp581 ValueSeq &Late);
582 bool classifyInst(Instruction *UseI, ValueSeq &Early, ValueSeq &Late);
1145 ValueSeq &Cycle, ValueSeq &Early, ValueSeq &Late) { in classifyCycle() argument
1163 ValueSeq &First = !IsE ? Early : Late; in classifyCycle()
1167 ValueSeq &Second = IsE ? Early : Late; in classifyCycle()
1181 ValueSeq &Early, ValueSeq &Late) { in classifyInst() argument
1188 if (Late.count(TV) || Late.count(FV)) in classifyInst()
1191 } else if (Late.count(TV) || Late.count(FV)) { in classifyInst()
1194 Late.insert(UseI); in classifyInst()
1208 else if (Late.count(&*I)) in classifyInst()
[all …]
DHexagonInstrFormats.td92 let TSFlags{12} = isPredicateLate; // Late predicate producer insn.
/external/libcxx/
DTODO.TXT66 * INCOMPLETE - Late 36: permissions() error_code overload should be noexcept
67 * INCOMPLETE - Late 37: permissions() actions should be separate parameter
68 * INCOMPLETE - Late 42: resize_file() Postcondition missing argument
/external/snakeyaml/src/test/resources/pyyaml/
Dspec-02-27.data27 Late afternoon is best.
/external/swiftshader/third_party/llvm-7.0/llvm/test/YAMLParser/
Dspec-02-27.test29 Late afternoon is best.
/external/llvm/test/YAMLParser/
Dspec-02-27.test29 Late afternoon is best.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DSplitKit.h420 bool Late, unsigned RegIdx);
424 unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex Def);
DSplitKit.cpp515 unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex Def) { in buildSingleSubRegCopy() argument
526 Def = Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot(); in buildSingleSubRegCopy()
540 MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) { in buildCopy() argument
547 return Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot(); in buildCopy()
590 BestIdx, DestLI, Late, SlotIndex()); in buildCopy()
620 DestLI, Late, Def); in buildCopy()
637 bool Late = RegIdx != 0; in defFromParent() local
650 Def = Edit->rematerializeAt(MBB, I, Reg, RM, TRI, Late); in defFromParent()
666 Def = buildCopy(Edit->getReg(), Reg, LaneMask, MBB, I, Late, RegIdx); in defFromParent()
DLiveRangeEdit.cpp170 bool Late) { in rematerializeAt() argument
178 return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot(); in rematerializeAt()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DLiveRangeEdit.cpp149 bool Late) { in rematerializeAt() argument
153 return lis.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late) in rematerializeAt()
DLiveRangeEdit.h174 bool Late = false);
DSplitKit.cpp412 bool Late = RegIdx != 0; in defFromParent() local
417 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI, Late); in defFromParent()
423 Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late) in defFromParent()
/external/llvm/lib/CodeGen/
DLiveRangeEdit.cpp148 bool Late) { in rematerializeAt() argument
156 return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot(); in rematerializeAt()
DSplitKit.cpp452 bool Late = RegIdx != 0; in defFromParent() local
462 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, TRI, Late); in defFromParent()
469 ->insertMachineInstrInMaps(*CopyMI, Late) in defFromParent()
/external/llvm/include/llvm/CodeGen/
DLiveRangeEdit.h216 bool Late = false);
DSlotIndexes.h580 SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late = false) {
592 if (Late) {
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DLiveRangeEdit.h223 bool Late = false);
DSlotIndexes.h577 SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late = false) {
589 if (Late) {
/external/hyphenation-patterns/hr/
Dhyph-hr.lic.txt41 % - Late 1994 first version
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DSlotIndexes.h647 SlotIndex insertMachineInstrInMaps(MachineInstr *mi, bool Late = false) {
657 if (Late) {
/external/apache-commons-bcel/docs/
Dmanual.bib90 title = {\protect{Type Inference for Late Binding. The
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
DO3-pipeline.ll144 ; CHECK-NEXT: Falkor HW Prefetch Fix Late Phase
/external/python/cpython2/Mac/Modules/cg/
DCFMLateImport.c118 #pragma mark ----- Late Import Engine -----
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMScheduleR52.td61 // ALU - Write occurs in Late EX2 (independent of whether shift was required)
79 // Branches - LR written in Late EX2
/external/llvm/lib/Target/Hexagon/
DHexagonInstrFormats.td122 let TSFlags{11} = isPredicateLate; // Late predicate producer insn.

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