| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.h | 220 const TargetLowering *Lowering) { in ldr() argument
221 const TargetInfo TInfo(Lowering); in ldr()
229 CondARM32::Cond Cond, const TargetLowering *Lowering) { in ldrex() argument
230 const TargetInfo TInfo(Lowering); in ldrex()
292 const TargetLowering *Lowering) { in str() argument
293 const TargetInfo TInfo(Lowering); in str()
301 CondARM32::Cond Cond, const TargetLowering *Lowering) { in strex() argument
302 const TargetInfo TInfo(Lowering); in strex()
429 CondARM32::Cond Cond, const TargetLowering *Lowering) { in vldrd() argument
430 const TargetInfo TInfo(Lowering); in vldrd()
[all …]
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| D | IceTargetLoweringX86Base.h | 1063 ScopedIacaMark(TargetX86Base *Lowering) : Lowering(Lowering) { in ScopedIacaMark() argument
1064 Lowering->_iaca_start(); in ScopedIacaMark()
1068 if (!Lowering) in end()
1070 Lowering->_iaca_end(); in end()
1071 Lowering = nullptr; in end()
1075 TargetX86Base *Lowering;
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| /external/llvm/lib/Target/X86/ |
| D | X86WinAllocaExpander.cpp | 44 enum Lowering { TouchAndSub, Sub, Probe }; enum in __anonf218f6140111::X86WinAllocaExpander
47 typedef MapVector<MachineInstr*, Lowering> LoweringMap;
53 Lowering getLowering(int64_t CurrentOffset, int64_t AllocaAmount);
56 void lower(MachineInstr* MI, Lowering L);
99 X86WinAllocaExpander::Lowering
163 Lowering L = getLowering(Offset, Amount); in computeLowerings()
201 void X86WinAllocaExpander::lower(MachineInstr* MI, Lowering L) { in lower()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86WinAllocaExpander.cpp | 44 enum Lowering { TouchAndSub, Sub, Probe }; enum in __anonedc1c54c0111::X86WinAllocaExpander
47 typedef MapVector<MachineInstr*, Lowering> LoweringMap;
53 Lowering getLowering(int64_t CurrentOffset, int64_t AllocaAmount);
56 void lower(MachineInstr* MI, Lowering L);
100 X86WinAllocaExpander::Lowering
164 Lowering L = getLowering(Offset, Amount); in computeLowerings()
202 void X86WinAllocaExpander::lower(MachineInstr* MI, Lowering L) { in lower()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/LTO/ |
| D | UpdateCompilerUsed.cpp | 75 const TargetLowering *Lowering = in initializeLibCalls() local
78 if (Lowering && TLSet.insert(Lowering).second) in initializeLibCalls()
84 Lowering->getLibcallName(static_cast<RTLIB::Libcall>(I))) in initializeLibCalls()
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| /external/llvm/lib/LTO/ |
| D | UpdateCompilerUsed.cpp | 75 const TargetLowering *Lowering = in initializeLibCalls() local
78 if (Lowering && TLSet.insert(Lowering).second) in initializeLibCalls()
84 Lowering->getLibcallName(static_cast<RTLIB::Libcall>(I))) in initializeLibCalls()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | O0-pipeline.ll | 16 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
23 ; CHECK-NEXT: Shadow Stack GC Lowering
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| D | O3-pipeline.ll | 17 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
38 ; CHECK-NEXT: Shadow Stack GC Lowering
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| D | mul_pow2.ll | 6 ; Lowering other positive constants are not supported yet.
243 ; Lowering other negative constants are not supported yet.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | O0-pipeline.ll | 16 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
23 ; CHECK-NEXT: Shadow Stack GC Lowering
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| D | O3-pipeline.ll | 17 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
32 ; CHECK-NEXT: Shadow Stack GC Lowering
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 224 const SITargetLowering& Lowering = in glueCopyToM0() local
229 SDValue M0 = Lowering.copyToM0(*CurDAG, CurDAG->getEntryNode(), SDLoc(N), in glueCopyToM0()
458 const SITargetLowering& Lowering = in Select() local
460 Lowering.legalizeTargetIndependentNode(N, *CurDAG); in Select()
886 const SITargetLowering& Lowering = in SelectMUBUFAddr64() local
889 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); in SelectMUBUFAddr64()
956 const SITargetLowering& Lowering = in SelectMUBUFOffset() local
959 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); in SelectMUBUFOffset()
1551 const AMDGPUTargetLowering& Lowering = in PostprocessISelDAG() local
1562 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG); in PostprocessISelDAG()
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| D | EvergreenInstructions.td | 618 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
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| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| D | XCoreISelDAGToDAG.cpp | 40 const XCoreTargetLowering &Lowering; member in __anon2b157bcd0111::XCoreDAGToDAGISel
46 Lowering(*TM.getTargetLowering()), in XCoreDAGToDAGISel()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 357 const SITargetLowering& Lowering = in glueCopyToM0() local
362 SDValue M0 = Lowering.copyToM0(*CurDAG, CurDAG->getEntryNode(), SDLoc(N), in glueCopyToM0()
620 const SITargetLowering& Lowering = in Select() local
622 N = Lowering.legalizeTargetIndependentNode(N, *CurDAG); in Select()
1073 const SITargetLowering& Lowering = in SelectMUBUFAddr64() local
1076 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); in SelectMUBUFAddr64()
1231 const SITargetLowering& Lowering = in SelectMUBUFOffset() local
1234 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); in SelectMUBUFOffset()
2121 const AMDGPUTargetLowering& Lowering = in PostprocessISelDAG() local
2135 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG); in PostprocessISelDAG()
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| D | EvergreenInstructions.td | 687 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelDAGToDAG.cpp | 93 const MSP430TargetLowering &Lowering; member in __anon4a0096d90411::MSP430DAGToDAGISel
99 Lowering(*TM.getTargetLowering()), in MSP430DAGToDAGISel()
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 82 const SystemZTargetLowering &Lowering; member in __anondb4f7e890411::SystemZDAGToDAGISel
94 Lowering(*TM.getTargetLowering()), in SystemZDAGToDAGISel()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/ |
| D | debuginfo.ll | 50 ; Lowering dbg.declare in instcombine doesn't handle this case very well.
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | vector-DAGCombine.ll | 211 ; Lowering to build vector was breaking the single use property of the load of
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| /external/llvm/test/CodeGen/ARM/ |
| D | vector-DAGCombine.ll | 211 ; Lowering to build vector was breaking the single use property of the load of
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| /external/swiftshader/third_party/subzero/docs/ |
| D | REGALLOC.rst | 40 - Basic lowering is done before register allocation. Lowering is the process of
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.td | 775 // Lowering for atomic load and store is defined in RISCVInstrInfoA.td.
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 810 // Coroutine Lowering Intrinsics. Used internally by coroutine passes.
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| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | GlobalISel.rst | 267 Constant Lowering
|