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Searched refs:MIPS_SIMD (Results 1 – 9 of 9) sorted by relevance

/external/v8/src/compiler/mips/
Dcode-generator-mips.cc1616 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
1705 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
1711 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
1716 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
1722 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
1732 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
1738 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
1744 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
1750 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
1756 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
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/external/v8/src/compiler/mips64/
Dcode-generator-mips64.cc1815 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
1915 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
1921 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
1926 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
1932 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
1942 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
1948 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
1954 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
1960 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
1966 CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); in AssembleArchInstruction()
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/external/v8/src/mips/
Dassembler-mips.cc84 supported_ |= 1u << MIPS_SIMD; in ProbeImpl()
100 supported_ |= 1u << MIPS_SIMD; in ProbeImpl()
102 if (cpu.has_msa()) supported_ |= 1u << MIPS_SIMD; in ProbeImpl()
1339 DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsaI8()
1348 DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsaI5()
1362 DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsaBit()
1371 DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsaI10()
1381 DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsa3R()
1391 DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsaElm()
1401 DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsa3RF()
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Dassembler-mips-inl.h51 bool CpuFeatures::SupportsWasmSimd128() { return IsSupported(MIPS_SIMD); } in SupportsWasmSimd128()
Dsimulator-mips.cc4327 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsaI8()
4477 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsaI5()
4513 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsaI10()
4550 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsaELM()
4782 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsaBIT()
4823 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsaMI10()
5205 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsa3R()
5523 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsa3RF()
5724 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsaVec()
5767 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsa2R()
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/external/v8/src/mips64/
Dassembler-mips64.cc81 supported_ |= 1u << MIPS_SIMD; in ProbeImpl()
89 supported_ |= 1u << MIPS_SIMD; in ProbeImpl()
91 if (cpu.has_msa()) supported_ |= 1u << MIPS_SIMD; in ProbeImpl()
1303 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsaI8()
1312 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsaI5()
1326 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsaBit()
1335 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsaI10()
1345 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsa3R()
1355 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsaElm()
1365 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); in GenInstrMsa3RF()
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Dassembler-mips64-inl.h50 bool CpuFeatures::SupportsWasmSimd128() { return IsSupported(MIPS_SIMD); } in SupportsWasmSimd128()
Dsimulator-mips64.cc4538 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsaI8()
4688 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsaI5()
4724 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsaI10()
4761 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsaELM()
5007 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsaBIT()
5048 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsaMI10()
5429 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsa3R()
5747 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsa3RF()
5948 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsaVec()
5991 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); in DecodeTypeMsa2R()
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/external/v8/src/
Dglobals.h818 MIPS_SIMD, // MSA instructions enumerator