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Searched refs:MRM7r (Results 1 – 25 of 37) sorted by relevance

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/external/swiftshader/third_party/LLVM/utils/TableGen/
DX86RecognizableInstr.cpp52 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, enumerator
137 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) || in needsModRMForDecode()
153 (form >= X86Local::MRM0r && form <= X86Local::MRM7r)) in isRegFormat()
734 case X86Local::MRM7r: in emitInstructionSpecifier()
826 case X86Local::MRM7r: in emitDecodePath()
915 case X86Local::MRM7r: in emitDecodePath()
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h216 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 enumerator
493 case X86II::MRM6r: case X86II::MRM7r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp581 case X86II::MRM6r: case X86II::MRM7r: in EmitVEXOpcodePrefix()
967 case X86II::MRM6r: case X86II::MRM7r: in EncodeInstruction()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrShiftRotate.td199 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
202 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
205 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
208 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
213 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
216 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
220 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
223 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
229 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
232 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrArithmetic.td276 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
279 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
282 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
286 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
1106 defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
DX86CodeEmitter.cpp904 case X86II::MRM6r: case X86II::MRM7r: { in emitInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrShiftRotate.td223 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
226 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
230 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
234 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
239 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
242 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
246 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
250 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
256 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
259 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrFPStack.td291 def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t$op">;
292 def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st(0), $op|$op, st(0)}">;
293 def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t$op">;
DX86InstrArithmetic.td314 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
317 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
320 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
324 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
1176 defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
DX86InstrSystem.td690 def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
693 def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, XS,
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td226 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
230 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
234 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
238 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
244 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
248 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
252 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
256 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
263 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
267 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrFPStack.td284 def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t$op">;
285 def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st(0), $op|$op, st(0)}">;
286 def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t$op">;
DX86InstrArithmetic.td335 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
338 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
341 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
345 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
1211 defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
DX86InstrInfo.td1694 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1697 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1700 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
2131 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
2134 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
2137 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
2403 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h296 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 enumerator
688 case X86II::MRM6r: case X86II::MRM7r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp872 case X86II::MRM6r: case X86II::MRM7r: { in EmitVEXOpcodePrefix()
1023 case X86II::MRM6r: case X86II::MRM7r: in DetermineREXPrefix()
1358 case X86II::MRM6r: case X86II::MRM7r: { in encodeInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h344 MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, // Format /4 /5 /6 /7 enumerator
730 case X86II::MRM6r: case X86II::MRM7r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp945 case X86II::MRM6r: case X86II::MRM7r: { in EmitVEXOpcodePrefix()
1095 case X86II::MRM6r: case X86II::MRM7r: in DetermineREXPrefix()
1489 case X86II::MRM6r: case X86II::MRM7r: in encodeInstruction()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp109 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, enumerator
151 (form >= X86Local::MRM0r && form <= X86Local::MRM7r)); in isRegFormat()
722 case X86Local::MRM7r: in emitInstructionSpecifier()
855 case X86Local::MRM6r: case X86Local::MRM7r: in emitDecodePath()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DX86RecognizableInstr.h118 MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, enumerator
DX86FoldTablesEmitter.cpp262 return FormBitsNum >= X86Local::MRMDestReg && FormBitsNum <= X86Local::MRM7r; in hasRegisterFormat()
422 (MemFormNum == X86Local::MRM7m && RegFormNum == X86Local::MRM7r) || in areOppositeForms()
DX86RecognizableInstr.cpp632 case X86Local::MRM7r: in emitInstructionSpecifier()
746 case X86Local::MRM6r: case X86Local::MRM7r: in emitDecodePath()
/external/swiftshader/third_party/LLVM/test/TableGen/
DTargetInstrInfo.td54 def MRM6r : Format<22>; def MRM7r : Format<23>;
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DTargetInstrInfo.td54 def MRM6r : Format<22>; def MRM7r : Format<23>;
/external/llvm/test/TableGen/
DTargetInstrInfo.td54 def MRM6r : Format<22>; def MRM7r : Format<23>;

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