| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZScheduleZ196.td | 171 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
179 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LHI(Mux)?$")>;
180 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LR(Mux)?$")>;
189 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
213 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LB(H|Mux)?$")>;
215 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
223 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLCR(Mux)?$")>;
224 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLHR(Mux)?$")>;
226 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLC(Mux)?$")>;
227 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLH(Mux)?$")>;
[all …]
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| D | SystemZScheduleZEC12.td | 176 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
184 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LHI(Mux)?$")>;
185 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LR(Mux)?$")>;
197 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
221 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LB(H|Mux)?$")>;
223 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
231 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLCR(Mux)?$")>;
232 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLHR(Mux)?$")>;
234 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLC(Mux)?$")>;
235 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLH(Mux)?$")>;
[all …]
|
| D | SystemZScheduleZ13.td | 188 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
197 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LHI(Mux)?$")>;
198 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR(Mux)?$")>;
213 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
224 def : InstRW<[WLat2, FXa, NormalGr], (instregex "LOC(G|H)?HI(Mux|(Asm.*))?$")>;
226 (instregex "LOC(G|FH|Mux)?(Asm.*)?$")>;
228 (instregex "STOC(G|FH|Mux)?(Asm.*)?$")>;
240 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LB(H|Mux)?$")>;
242 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
250 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLCR(Mux)?$")>;
[all …]
|
| D | SystemZScheduleZ14.td | 189 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
198 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LHI(Mux)?$")>;
199 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR(Mux)?$")>;
214 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
225 def : InstRW<[WLat2, FXa, NormalGr], (instregex "LOC(G|H)?HI(Mux|(Asm.*))?$")>;
227 (instregex "LOC(G|FH|Mux)?(Asm.*)?$")>;
229 (instregex "STOC(G|FH|Mux)?(Asm.*)?$")>;
241 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LB(H|Mux)?$")>;
243 def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
251 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLCR(Mux)?$")>;
[all …]
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| /external/llvm/test/MC/Disassembler/Hexagon/ |
| D | alu32_perm.txt | 22 # Mux
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Hexagon/ |
| D | alu32_perm.txt | 22 # Mux
|
| /external/clang/tools/libclang/ |
| D | Indexing.cpp | 129 llvm::sys::Mutex Mux; member in __anone24f30970211::SessionSkipBodyData
133 SessionSkipBodyData() : Mux(/*recursive=*/false) {} in SessionSkipBodyData()
139 llvm::MutexGuard MG(Mux); in copyTo()
144 llvm::MutexGuard MG(Mux); in update()
|
| /external/u-boot/drivers/i2c/muxes/ |
| D | Kconfig | 29 tristate "TI PCA954x I2C Mux/switches"
|
| /external/u-boot/doc/device-tree-bindings/pinctrl/ |
| D | st,stm32-pinctrl.txt | 1 * STM32 GPIO and Pin Mux/Config controller
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/intrinsics/ |
| D | alu32_perm.ll | 64 ; Mux
|
| /external/llvm/test/CodeGen/Hexagon/intrinsics/ |
| D | alu32_perm.ll | 64 ; Mux
|
| /external/u-boot/board/freescale/m53017evb/ |
| D | README | 19 - arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
|
| /external/u-boot/doc/ |
| D | README.m54418twr | 20 - arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
|
| /external/u-boot/board/freescale/m52277evb/ |
| D | README | 18 - arch/m68k/cpu/mcf5227x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
|
| /external/u-boot/board/freescale/m547xevb/ |
| D | README | 19 - arch/m68k/cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
|
| /external/u-boot/board/freescale/m5373evb/ |
| D | README | 19 - arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
|
| /external/u-boot/arch/arm/dts/ |
| D | tegra20.dtsi | 261 0x70000080 0x20 /* Mux registers */
|
| D | tegra114.dtsi | 251 0x70003000 0x40c>; /* Mux registers */
|
| D | tegra210.dtsi | 413 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
|
| D | tegra30.dtsi | 366 0x70003000 0x3e4>; /* Mux registers */
|
| D | tegra124.dtsi | 315 <0x70003000 0x434>, /* Mux registers */
|
| /external/u-boot/board/freescale/m54455evb/ |
| D | README | 22 - arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonIntrinsics.td | 779 // Mux
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonIntrinsics.td | 801 // Mux
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.td | 346 // We don't define 32-bit Mux stores because the low-only STOC should
|