| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 288 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
291 def rr : F3_1<2, Op3Val,
296 def ri : F3_2<2, Op3Val,
305 multiclass F3_12np<string OpcStr, bits<6> Op3Val, InstrItinClass itin = IIC_iu_instr> {
306 def rr : F3_1<2, Op3Val,
310 def ri : F3_2<2, Op3Val,
317 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
319 def rr : F3_1<3, Op3Val,
324 def ri : F3_2<3, Op3Val,
333 class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
[all …]
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| D | SparcInstrFormats.td | 227 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
230 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
234 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt),
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 292 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
295 def rr : F3_1<2, Op3Val,
300 def ri : F3_2<2, Op3Val,
309 multiclass F3_12np<string OpcStr, bits<6> Op3Val, InstrItinClass itin = IIC_iu_instr> {
310 def rr : F3_1<2, Op3Val,
314 def ri : F3_2<2, Op3Val,
321 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
323 def rr : F3_1<3, Op3Val,
328 def ri : F3_2<3, Op3Val,
337 class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
[all …]
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| D | SparcInstrFormats.td | 227 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
230 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
234 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt),
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 181 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
182 def rr : F3_1<2, Op3Val,
186 def ri : F3_2<2, Op3Val,
194 multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
195 def rr : F3_1<2, Op3Val,
198 def ri : F3_2<2, Op3Val,
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 3756 uint64_t Op3Val = Op3CE->getValue(); in MatchAndEmitInstruction() local
3761 NewOp3Val = (32 - Op3Val) & 0x1f; in MatchAndEmitInstruction()
3762 NewOp4Val = 31 - Op3Val; in MatchAndEmitInstruction()
3764 NewOp3Val = (64 - Op3Val) & 0x3f; in MatchAndEmitInstruction()
3765 NewOp4Val = 63 - Op3Val; in MatchAndEmitInstruction()
3846 uint64_t Op3Val = Op3CE->getValue(); in MatchAndEmitInstruction() local
3856 if (Op3Val >= RegWidth) in MatchAndEmitInstruction()
3865 NewOp3Val = (32 - Op3Val) & 0x1f; in MatchAndEmitInstruction()
3867 NewOp3Val = (64 - Op3Val) & 0x3f; in MatchAndEmitInstruction()
3910 uint64_t Op3Val = Op3CE->getValue(); in MatchAndEmitInstruction() local
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 4354 uint64_t Op3Val = Op3CE->getValue(); in MatchAndEmitInstruction() local
4359 NewOp3Val = (32 - Op3Val) & 0x1f; in MatchAndEmitInstruction()
4360 NewOp4Val = 31 - Op3Val; in MatchAndEmitInstruction()
4362 NewOp3Val = (64 - Op3Val) & 0x3f; in MatchAndEmitInstruction()
4363 NewOp4Val = 63 - Op3Val; in MatchAndEmitInstruction()
4444 uint64_t Op3Val = Op3CE->getValue(); in MatchAndEmitInstruction() local
4454 if (Op3Val >= RegWidth) in MatchAndEmitInstruction()
4463 NewOp3Val = (32 - Op3Val) & 0x1f; in MatchAndEmitInstruction()
4465 NewOp3Val = (64 - Op3Val) & 0x3f; in MatchAndEmitInstruction()
4508 uint64_t Op3Val = Op3CE->getValue(); in MatchAndEmitInstruction() local
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 806 multiclass F3_12 <string OpcStr, bits<6> Op3Val, SDNode OpNode> {
807 def rr : F3_1 <2, Op3Val,
811 def ri : F3_2 <2, Op3Val,
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 806 multiclass F3_12 <string OpcStr, bits<6> Op3Val, SDNode OpNode> {
807 def rr : F3_1 <2, Op3Val,
811 def ri : F3_2 <2, Op3Val,
|