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Searched refs:OpName (Results 1 – 25 of 154) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600InstrInfo.cpp91 NewMI->getOperand(getOperandIdx(*NewMI, R600::OpName::src0)) in copyPhysReg()
157 return isLDSInstr(Opcode) && getOperandIdx(Opcode, R600::OpName::dst) != -1; in isLDSRetInstr()
258 {R600::OpName::src0, R600::OpName::src0_sel}, in getSelIdx()
259 {R600::OpName::src1, R600::OpName::src1_sel}, in getSelIdx()
260 {R600::OpName::src2, R600::OpName::src2_sel}, in getSelIdx()
261 {R600::OpName::src0_X, R600::OpName::src0_sel_X}, in getSelIdx()
262 {R600::OpName::src0_Y, R600::OpName::src0_sel_Y}, in getSelIdx()
263 {R600::OpName::src0_Z, R600::OpName::src0_sel_Z}, in getSelIdx()
264 {R600::OpName::src0_W, R600::OpName::src0_sel_W}, in getSelIdx()
265 {R600::OpName::src1_X, R600::OpName::src1_sel_X}, in getSelIdx()
[all …]
DSIPeepholeSDWA.cpp337 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { in getSrcMods()
338 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) { in getSrcMods()
341 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) { in getSrcMods()
342 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers)) { in getSrcMods()
372 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA()
373 MachineOperand *SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel); in convertToSDWA()
375 TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers); in convertToSDWA()
379 Src = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in convertToSDWA()
380 SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel); in convertToSDWA()
381 SrcMods = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers); in convertToSDWA()
[all …]
DR600ExpandSpecialInstrs.cpp99 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction()
106 R600::OpName::pred_sel); in runOnMachineFunction()
108 R600::OpName::pred_sel); in runOnMachineFunction()
128 TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1); in runOnMachineFunction()
130 TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1); in runOnMachineFunction()
160 TII->getOperandIdx(Opcode, R600::OpName::src0)) in runOnMachineFunction()
163 TII->getOperandIdx(Opcode, R600::OpName::src1)) in runOnMachineFunction()
210 TII->getOperandIdx(MI, R600::OpName::dst)).getReg(); in runOnMachineFunction()
212 TII->getOperandIdx(MI, R600::OpName::src0)).getReg(); in runOnMachineFunction()
217 int Src1Idx = TII->getOperandIdx(MI, R600::OpName::src1); in runOnMachineFunction()
[all …]
DSIFoldOperands.cpp135 int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); in isInlineConstantIfFolded()
169 if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0)) in updateOperand()
170 ModIdx = AMDGPU::OpName::src0_modifiers; in updateOperand()
171 else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1)) in updateOperand()
172 ModIdx = AMDGPU::OpName::src1_modifiers; in updateOperand()
173 else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2)) in updateOperand()
174 ModIdx = AMDGPU::OpName::src2_modifiers; in updateOperand()
234 (int)OpNo == AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)) { in tryAddToFoldList()
542 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1); in tryConstantFoldOp()
546 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); in tryConstantFoldOp()
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DR600ClauseMergePass.cpp88 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
95 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
101 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in cleanPotentialDisabledCFAlu()
120 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in mergeIfPossible()
132 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0); in mergeIfPossible()
134 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0); in mergeIfPossible()
136 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0); in mergeIfPossible()
148 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE1); in mergeIfPossible()
150 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK1); in mergeIfPossible()
152 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR1); in mergeIfPossible()
DSIShrinkInstructions.cpp71 const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in canShrink()
86 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in canShrink()
96 TII->hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers)) in canShrink()
105 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in canShrink()
107 TII->hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers))) in canShrink()
112 if (TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers)) in canShrink()
116 return !TII->hasModifiersSet(MI, AMDGPU::OpName::omod) && in canShrink()
117 !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp); in canShrink()
127 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); in foldImmediates()
451 TII->getNamedOperand(MI, AMDGPU::OpName::src2); in runOnMachineFunction()
[all …]
DSILoadStoreOptimizer.cpp320 AddrOpName[NumAddresses++] = AMDGPU::OpName::addr; in findMatchingInst()
323 AddrOpName[NumAddresses++] = AMDGPU::OpName::sbase; in findMatchingInst()
327 AddrOpName[NumAddresses++] = AMDGPU::OpName::srsrc; in findMatchingInst()
328 AddrOpName[NumAddresses++] = AMDGPU::OpName::vaddr; in findMatchingInst()
329 AddrOpName[NumAddresses++] = AMDGPU::OpName::soffset; in findMatchingInst()
333 AddrOpName[NumAddresses++] = AMDGPU::OpName::srsrc; in findMatchingInst()
334 AddrOpName[NumAddresses++] = AMDGPU::OpName::soffset; in findMatchingInst()
427 AMDGPU::OpName::offset); in findMatchingInst()
436 CI.GLC0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::glc)->getImm(); in findMatchingInst()
437 CI.GLC1 = TII->getNamedOperand(*MBBI, AMDGPU::OpName::glc)->getImm(); in findMatchingInst()
[all …]
DSIInstrInfo.cpp110 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) { in nodesHaveSameOperandValue() argument
114 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName); in nodesHaveSameOperandValue()
115 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); in nodesHaveSameOperandValue()
180 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 || in areLoadsFromSameBasePtr()
181 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1) in areLoadsFromSameBasePtr()
191 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::sbase) == -1 || in areLoadsFromSameBasePtr()
192 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1) in areLoadsFromSameBasePtr()
222 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) || in areLoadsFromSameBasePtr()
224 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) || in areLoadsFromSameBasePtr()
225 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc)) in areLoadsFromSameBasePtr()
[all …]
DR600Packetizer.cpp87 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); in getPreviousVector()
90 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector()
132 R600::OpName::src0, in substitutePV()
133 R600::OpName::src1, in substitutePV()
134 R600::OpName::src2 in substitutePV()
188 int OpI = TII->getOperandIdx(MII->getOpcode(), R600::OpName::pred_sel), in isLegalToPacketizeTogether()
189 OpJ = TII->getOperandIdx(MIJ->getOpcode(), R600::OpName::pred_sel); in isLegalToPacketizeTogether()
223 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), R600::OpName::last); in setIsLastBit()
304 R600::OpName::bank_swizzle); in addToPacket()
308 TII->getOperandIdx(MI.getOpcode(), R600::OpName::bank_swizzle); in addToPacket()
DR600ISelLowering.cpp302 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in EmitInstrWithCustomInserter()
362 int Idx = TII->getOperandIdx(*MIB, R600::OpName::literal); in EmitInstrWithCustomInserter()
371 TII->setImmOperand(*NewMI, R600::OpName::src0_sel, in EmitInstrWithCustomInserter()
2094 bool HasDst = TII->getOperandIdx(Opcode, R600::OpName::dst) > -1; in FoldOperand()
2105 TII->getOperandIdx(Opcode, R600::OpName::src0), in FoldOperand()
2106 TII->getOperandIdx(Opcode, R600::OpName::src1), in FoldOperand()
2107 TII->getOperandIdx(Opcode, R600::OpName::src2), in FoldOperand()
2108 TII->getOperandIdx(Opcode, R600::OpName::src0_X), in FoldOperand()
2109 TII->getOperandIdx(Opcode, R600::OpName::src0_Y), in FoldOperand()
2110 TII->getOperandIdx(Opcode, R600::OpName::src0_Z), in FoldOperand()
[all …]
DVOP2Instructions.td103 class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
104 VOP_SDWA_Pseudo <OpName, P, pattern> {
701 class VOP2_DPP <bits<6> op, VOP2_Pseudo ps, string OpName = ps.OpName, VOPProfile P = ps.Pfl> :
702 VOP_DPP <OpName, P> {
773 multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> {
775 VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.VI>,
776 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
777 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");
782 VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.VI>,
783 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
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DSIRegisterInfo.cpp275 AMDGPU::OpName::offset); in getMUBUFInstrOffset()
285 AMDGPU::OpName::vaddr) && in getFrameIndexInstrOffset()
356 MachineOperand *FIOp = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in resolveFrameIndex()
359 assert(TII->getNamedOperand(MI, AMDGPU::OpName::soffset)->getReg() == in resolveFrameIndex()
364 MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset); in resolveFrameIndex()
497 const MachineOperand *Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata); in buildMUBUFOffsetLoadStore()
500 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)) in buildMUBUFOffsetLoadStore()
501 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)) in buildMUBUFOffsetLoadStore()
509 AMDGPU::OpName::vdata_in); in buildMUBUFOffsetLoadStore()
1029 AMDGPU::OpName::vdata); in eliminateFrameIndex()
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/external/llvm/lib/Target/AMDGPU/
DR600InstrInfo.cpp71 NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0)) in copyPhysReg()
148 return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) == -1; in isLDSNoRetInstr()
152 return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) != -1; in isLDSRetInstr()
253 AMDGPU::OpName::src0, in getSrcIdx()
254 AMDGPU::OpName::src1, in getSrcIdx()
255 AMDGPU::OpName::src2 in getSrcIdx()
264 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel}, in getSelIdx()
265 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel}, in getSelIdx()
266 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel}, in getSelIdx()
267 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X}, in getSelIdx()
[all …]
DR600ExpandSpecialInstrs.cpp83 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); in runOnMachineFunction()
90 AMDGPU::OpName::pred_sel); in runOnMachineFunction()
92 AMDGPU::OpName::pred_sel); in runOnMachineFunction()
112 TII->setImmOperand(*PredSet, AMDGPU::OpName::update_exec_mask, 1); in runOnMachineFunction()
114 TII->setImmOperand(*PredSet, AMDGPU::OpName::update_pred, 1); in runOnMachineFunction()
223 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0)) in runOnMachineFunction()
226 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1)) in runOnMachineFunction()
273 TII->getOperandIdx(MI, AMDGPU::OpName::dst)).getReg(); in runOnMachineFunction()
275 TII->getOperandIdx(MI, AMDGPU::OpName::src0)).getReg(); in runOnMachineFunction()
280 int Src1Idx = TII->getOperandIdx(MI, AMDGPU::OpName::src1); in runOnMachineFunction()
[all …]
DSIShrinkInstructions.cpp84 const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in canShrink()
97 TII->hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers)) in canShrink()
106 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in canShrink()
108 TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers); in canShrink()
115 if (TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers)) in canShrink()
119 if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod)) in canShrink()
122 return !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp); in canShrink()
138 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); in foldImmediates()
349 TII->getNamedOperand(MI, AMDGPU::OpName::src2); in runOnMachineFunction()
369 int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::vdst); in runOnMachineFunction()
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DR600ClauseMergePass.cpp77 .getOperand(TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::COUNT)) in getCFAluSize()
84 .getOperand(TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::Enabled)) in isCFAluEnabled()
90 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT); in cleanPotentialDisabledCFAlu()
109 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT); in mergeIfPossible()
121 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE0); in mergeIfPossible()
123 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK0); in mergeIfPossible()
125 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR0); in mergeIfPossible()
137 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE1); in mergeIfPossible()
139 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK1); in mergeIfPossible()
141 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR1); in mergeIfPossible()
DSIInstrInfo.cpp53 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) { in nodesHaveSameOperandValue() argument
57 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName); in nodesHaveSameOperandValue()
58 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); in nodesHaveSameOperandValue()
123 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 || in areLoadsFromSameBasePtr()
124 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1) in areLoadsFromSameBasePtr()
160 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) || in areLoadsFromSameBasePtr()
162 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) || in areLoadsFromSameBasePtr()
163 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc)) in areLoadsFromSameBasePtr()
166 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset); in areLoadsFromSameBasePtr()
167 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset); in areLoadsFromSameBasePtr()
[all …]
DSILoadStoreOptimizer.cpp171 int AddrIdx = AMDGPU::getNamedOperandIdx(I->getOpcode(), AMDGPU::OpName::addr); in findMatchingDSInst()
180 AMDGPU::OpName::offset); in findMatchingDSInst()
200 const MachineOperand *AddrReg = TII->getNamedOperand(*I, AMDGPU::OpName::addr); in mergeRead2Pair()
202 const MachineOperand *Dest0 = TII->getNamedOperand(*I, AMDGPU::OpName::vdst); in mergeRead2Pair()
203 const MachineOperand *Dest1 = TII->getNamedOperand(*Paired, AMDGPU::OpName::vdst); in mergeRead2Pair()
206 = TII->getNamedOperand(*I, AMDGPU::OpName::offset)->getImm() & 0xffff; in mergeRead2Pair()
208 = TII->getNamedOperand(*Paired, AMDGPU::OpName::offset)->getImm() & 0xffff; in mergeRead2Pair()
295 const MachineOperand *Addr = TII->getNamedOperand(*I, AMDGPU::OpName::addr); in mergeWrite2Pair()
296 const MachineOperand *Data0 = TII->getNamedOperand(*I, AMDGPU::OpName::data0); in mergeWrite2Pair()
298 = TII->getNamedOperand(*Paired, AMDGPU::OpName::data0); in mergeWrite2Pair()
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DR600Packetizer.cpp89 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write); in getPreviousVector()
92 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst); in getPreviousVector()
134 AMDGPU::OpName::src0, in substitutePV()
135 AMDGPU::OpName::src1, in substitutePV()
136 AMDGPU::OpName::src2 in substitutePV()
190 int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::pred_sel), in isLegalToPacketizeTogether()
191 OpJ = TII->getOperandIdx(MIJ->getOpcode(), AMDGPU::OpName::pred_sel); in isLegalToPacketizeTogether()
225 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::last); in setIsLastBit()
306 AMDGPU::OpName::bank_swizzle); in addToPacket()
310 TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::bank_swizzle); in addToPacket()
DR600ISelLowering.cpp223 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); in EmitInstrWithCustomInserter()
288 int Idx = TII->getOperandIdx(*MIB, AMDGPU::OpName::literal); in EmitInstrWithCustomInserter()
296 TII->setImmOperand(*NewMI, AMDGPU::OpName::src0_sel, in EmitInstrWithCustomInserter()
2192 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1; in FoldOperand()
2203 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0), in FoldOperand()
2204 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1), in FoldOperand()
2205 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2), in FoldOperand()
2206 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X), in FoldOperand()
2207 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y), in FoldOperand()
2208 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z), in FoldOperand()
[all …]
DSIRegisterInfo.cpp259 AMDGPU::OpName::vaddr) && in getFrameIndexInstrOffset()
263 AMDGPU::OpName::offset); in getFrameIndexInstrOffset()
324 MachineOperand *FIOp = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in resolveFrameIndex()
329 MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset); in resolveFrameIndex()
640 TII->getNamedOperand(*MI, AMDGPU::OpName::src), in eliminateFrameIndex()
641 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(), in eliminateFrameIndex()
642 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(), in eliminateFrameIndex()
644 TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), RS); in eliminateFrameIndex()
655 TII->getNamedOperand(*MI, AMDGPU::OpName::dst), in eliminateFrameIndex()
656 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(), in eliminateFrameIndex()
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/external/deqp/external/vulkancts/data/vulkan/vkrunner/example/
Dspirv.shader_test7 OpName %main "main"
8 OpName %gl_PerVertex "gl_PerVertex"
10 OpName %_ ""
11 OpName %pos "pos"
12 OpName %norm_coord "norm_coord"
49 OpName %main "main"
50 OpName %color "color"
51 OpName %norm_coord "norm_coord"
/external/tensorflow/tensorflow/core/kernels/
Dlinalg_ops_common.h185 #define REGISTER_LINALG_OP_CPU(OpName, OpClass, Scalar) \ argument
187 Name(OpName).Device(DEVICE_CPU).TypeConstraint<Scalar>("T"), OpClass)
189 #define REGISTER_LINALG_OP_GPU(OpName, OpClass, Scalar) \ argument
191 Name(OpName).Device(DEVICE_GPU).TypeConstraint<Scalar>("T"), OpClass)
194 #define REGISTER_LINALG_OP(OpName, OpClass, Scalar) \ argument
195 REGISTER_LINALG_OP_CPU(OpName, OpClass, Scalar)
/external/swiftshader/third_party/LLVM/utils/TableGen/
DCodeGenInstruction.cpp159 std::string OpName = Op.substr(1); in ParseOperandName() local
163 std::string::size_type DotIdx = OpName.find_first_of("."); in ParseOperandName()
165 SubOpName = OpName.substr(DotIdx+1); in ParseOperandName()
168 OpName = OpName.substr(0, DotIdx); in ParseOperandName()
171 unsigned OpIdx = getOperandNamed(OpName); in ParseOperandName()
271 std::string OpName = P.first; in ProcessDisableEncoding() local
273 if (OpName.empty()) break; in ProcessDisableEncoding()
276 std::pair<unsigned,unsigned> Op = ParseOperandName(OpName, false); in ProcessDisableEncoding()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp252 AMDGPU::OpName::src2_modifiers); in getInstruction()
271 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) in convertSDWAInst()
273 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); in convertSDWAInst()
275 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); in convertSDWAInst()
279 AMDGPU::OpName::sdst); in convertSDWAInst()
282 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); in convertSDWAInst()
294 AMDGPU::OpName::vdst); in convertMIMGInst()
297 AMDGPU::OpName::vdata); in convertMIMGInst()
300 AMDGPU::OpName::dmask); in convertMIMGInst()
303 AMDGPU::OpName::tfe); in convertMIMGInst()
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