| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 1498 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in AddPromotedToType() argument
1499 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; in AddPromotedToType()
1504 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in setOperationPromotedToType() argument
1505 setOperationAction(Opc, OrigVT, Promote); in setOperationPromotedToType()
1506 AddPromotedToType(Opc, OrigVT, DestVT); in setOperationPromotedToType()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetLowering.h | 1871 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in AddPromotedToType() argument
1872 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; in AddPromotedToType()
1877 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in setOperationPromotedToType() argument
1878 setOperationAction(Opc, OrigVT, Promote); in setOperationPromotedToType()
1879 AddPromotedToType(Opc, OrigVT, DestVT); in setOperationPromotedToType()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetLowering.h | 1120 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in AddPromotedToType() argument
1121 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; in AddPromotedToType()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 262 EVT OrigVT = VT; in ExpandConstantFP() local
269 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && in ExpandConstantFP()
270 TLI.ShouldShrinkFPConstant(OrigVT)) { in ExpandConstantFP()
283 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx, in ExpandConstantFP()
289 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, in ExpandConstantFP()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 4263 EVT OrigVT = Op.getOperand(0).getValueType(); in IsMulWideOperandDemotable() local
4264 if (OrigVT.getSizeInBits() <= OptSize) { in IsMulWideOperandDemotable()
4269 EVT OrigVT = Op.getOperand(0).getValueType(); in IsMulWideOperandDemotable() local
4270 if (OrigVT.getSizeInBits() <= OptSize) { in IsMulWideOperandDemotable()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 4117 EVT OrigVT = Op.getOperand(0).getValueType(); in IsMulWideOperandDemotable() local
4118 if (OrigVT.getSizeInBits() <= OptSize) { in IsMulWideOperandDemotable()
4123 EVT OrigVT = Op.getOperand(0).getValueType(); in IsMulWideOperandDemotable() local
4124 if (OrigVT.getSizeInBits() <= OptSize) { in IsMulWideOperandDemotable()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 294 EVT OrigVT = VT; in ExpandConstantFP() local
305 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && in ExpandConstantFP()
306 TLI.ShouldShrinkFPConstant(OrigVT)) { in ExpandConstantFP()
320 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx, in ExpandConstantFP()
326 OrigVT, dl, DAG.getEntryNode(), CPIdx, in ExpandConstantFP()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 2751 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT, in CalculateStackSlotAlignment() argument
2784 if (Flags.isSplit() && OrigVT != MVT::ppcf128) in CalculateStackSlotAlignment()
2785 Align = OrigVT.getStoreSize(); in CalculateStackSlotAlignment()
2797 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT, in CalculateStackSlotUsed() argument
2809 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize); in CalculateStackSlotUsed()
3202 EVT OrigVT = Ins[ArgNo].ArgVT; in LowerFormalArguments_64SVR4() local
3216 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize); in LowerFormalArguments_64SVR4()
5055 EVT OrigVT = Outs[i].ArgVT; in LowerCall_64SVR4() local
5104 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize); in LowerCall_64SVR4()
5170 EVT OrigVT = Outs[i].ArgVT; in LowerCall_64SVR4() local
[all …]
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 354 EVT OrigVT = VT; in ExpandConstantFP() local
362 TLI.ShouldShrinkFPConstant(OrigVT)) { in ExpandConstantFP()
373 return DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, in ExpandConstantFP()
377 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, in ExpandConstantFP()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 3235 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT, in CalculateStackSlotAlignment() argument
3268 if (Flags.isSplit() && OrigVT != MVT::ppcf128) in CalculateStackSlotAlignment()
3269 Align = OrigVT.getStoreSize(); in CalculateStackSlotAlignment()
3281 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT, in CalculateStackSlotUsed() argument
3293 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize); in CalculateStackSlotUsed()
3685 EVT OrigVT = Ins[ArgNo].ArgVT; in LowerFormalArguments_64SVR4() local
3699 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize); in LowerFormalArguments_64SVR4()
5608 EVT OrigVT = Outs[i].ArgVT; in LowerCall_64SVR4() local
5662 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize); in LowerCall_64SVR4()
5732 EVT OrigVT = Outs[i].ArgVT; in LowerCall_64SVR4() local
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 2089 static EVT getExtensionTo64Bits(const EVT &OrigVT) { in getExtensionTo64Bits() argument
2090 if (OrigVT.getSizeInBits() >= 64) in getExtensionTo64Bits()
2091 return OrigVT; in getExtensionTo64Bits()
2093 assert(OrigVT.isSimple() && "Expecting a simple value type"); in getExtensionTo64Bits()
2095 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy; in getExtensionTo64Bits()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 2417 static EVT getExtensionTo64Bits(const EVT &OrigVT) { in getExtensionTo64Bits() argument
2418 if (OrigVT.getSizeInBits() >= 64) in getExtensionTo64Bits()
2419 return OrigVT; in getExtensionTo64Bits()
2421 assert(OrigVT.isSimple() && "Expecting a simple value type"); in getExtensionTo64Bits()
2423 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy; in getExtensionTo64Bits()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 12938 MVT OrigVT = V.getSimpleValueType(); in splitAndLowerVectorShuffle() local
12939 int OrigNumElements = OrigVT.getVectorNumElements(); in splitAndLowerVectorShuffle()
12941 MVT OrigScalarVT = OrigVT.getVectorElementType(); in splitAndLowerVectorShuffle()
25209 MVT OrigVT = VT; in LowerMGATHER() local
25232 SDValue Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OrigVT, in LowerMGATHER()
36984 EVT OrigVT = N->getValueType(0); in combineFneg() local
37004 return DAG.getBitcast(OrigVT, NewNode); in combineFneg()
37026 return DAG.getBitcast(OrigVT, DAG.getNode(NewOpcode, DL, VT, in combineFneg()
39333 MVT OrigVT = OrigV.getSimpleValueType(); in combineVSZext() local
39335 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) { in combineVSZext()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 6507 static EVT getExtensionTo64Bits(const EVT &OrigVT) { in getExtensionTo64Bits() argument
6508 if (OrigVT.getSizeInBits() >= 64) in getExtensionTo64Bits()
6509 return OrigVT; in getExtensionTo64Bits()
6511 assert(OrigVT.isSimple() && "Expecting a simple value type"); in getExtensionTo64Bits()
6513 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy; in getExtensionTo64Bits()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 7331 static EVT getExtensionTo64Bits(const EVT &OrigVT) { in getExtensionTo64Bits() argument
7332 if (OrigVT.getSizeInBits() >= 64) in getExtensionTo64Bits()
7333 return OrigVT; in getExtensionTo64Bits()
7335 assert(OrigVT.isSimple() && "Expecting a simple value type"); in getExtensionTo64Bits()
7337 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy; in getExtensionTo64Bits()
|