| /external/libxaac/decoder/armv8/ |
| D | ixheaacd_overlap_add2.s | 70 REV64 V4.4H, V6.4H
72 REV64 V5.4H, V7.4H
86 REV64 V12.4H, V14.4H
87 REV64 V13.4H, V15.4H
101 REV64 V4.4H, V6.4H
103 REV64 V5.4H, V7.4H
122 REV64 V12.4H, V14.4H
123 REV64 V13.4H, V15.4H
184 REV64 V0.4S, V6.4S
190 REV64 V1.4S, V1.4S
[all …]
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| D | ixheaacd_overlap_add1.s | 68 REV64 V31.8h, V31.8h
69 REV64 V30.8h, V30.8h
73 REV64 V7.8H, V7.8H
74 REV64 V6.8H, V6.8H
83 REV64 V2.4H, V2.4H
84 REV64 V3.4H, V3.4H
132 REV64 V1.8h, V1.8h
133 REV64 V0.8h, V0.8h
137 REV64 V7.8h, V7.8h
138 REV64 V6.8h, V6.8h
[all …]
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| D | ixheaacd_no_lap1.s | 68 REV64 V23.4S, V23.4S
85 REV64 V20.4S, V20.4S
97 REV64 V23.4S, V23.4S
114 REV64 V20.4S, V20.4S
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| D | ixheaacd_inv_dit_fft_8pt.s | 85 REV64 v7.2s, v7.2s //x13_12 = vrev64_s32(x12_13);
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| /external/llvm/docs/ |
| D | BigEndianNEON.rst | 194 …REV64 v0.4s, v0.4s // There is no REV128 instruction, so it must be synthesizedcd
195 EXT v0.16b, v0.16b, v0.16b, #8 // with a REV64 then an EXT to swap the two 64-bit elements.
197 REV64 v0.2d, v0.2d
202 …`. For the example above, a ``REV128 4s`` + ``REV128 2d`` is actually a ``REV64 4s``, as shown in …
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| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | BigEndianNEON.rst | 194 …REV64 v0.4s, v0.4s // There is no REV128 instruction, so it must be synthesizedcd
195 EXT v0.16b, v0.16b, v0.16b, #8 // with a REV64 then an EXT to swap the two 64-bit elements.
197 REV64 v0.2d, v0.2d
202 …`. For the example above, a ``REV128 4s`` + ``REV128 2d`` is actually a ``REV64 4s``, as shown in …
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 109 REV64, enumerator
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| D | AArch64SchedCyclone.td | 498 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
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| D | AArch64ISelLowering.cpp | 885 case AArch64ISD::REV64: return "AArch64ISD::REV64"; in getTargetNodeName()
5445 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
5629 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2); in LowerVECTOR_SHUFFLE()
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| D | AArch64InstrInfo.td | 219 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
2880 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-rev.ll | 221 ; vrev <4 x i16> should use REV32 and not REV64
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-rev.ll | 221 ; vrev <4 x i16> should use REV32 and not REV64
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 109 REV64, enumerator
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| D | AArch64SchedCyclone.td | 500 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
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| D | AArch64ISelLowering.cpp | 1136 case AArch64ISD::REV64: return "AArch64ISD::REV64"; in getTargetNodeName()
6229 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
6413 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2); in LowerVECTOR_SHUFFLE()
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| D | AArch64InstrInfo.td | 250 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
3144 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2756 ### REV64 ### subsection
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenFastISel.inc | 1305 // FastEmit functions for AArch64ISD::REV64.
3976 case AArch64ISD::REV64: return fastEmit_AArch64ISD_REV64_r(VT, RetVT, Op0, Op0IsKill);
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| D | AArch64GenDAGISel.inc | 46085 /* 89718*/ /*SwitchOpcode*/ 105, TARGET_VAL(AArch64ISD::REV64),// ->89826
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