| /external/llvm/lib/CodeGen/ |
| D | LiveInterval.cpp | 973 OS << " updater with gap = " << (ReadI - WriteI) in print()
982 for (const auto &S : make_range(ReadI, LR->end())) in print()
1019 WriteI = ReadI = LR->begin(); in add()
1027 if (ReadI != E && ReadI->end <= Seg.start) { in add()
1029 if (ReadI != WriteI) in add()
1032 if (ReadI == WriteI) in add()
1033 ReadI = WriteI = LR->find(Seg.start); in add()
1035 while (ReadI != E && ReadI->end <= Seg.start) in add()
1036 *WriteI++ = *ReadI++; in add()
1039 assert(ReadI == E || ReadI->end > Seg.start); in add()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | LiveInterval.cpp | 1092 OS << " updater with gap = " << (ReadI - WriteI) in print()
1101 for (const auto &S : make_range(ReadI, LR->end())) in print()
1139 WriteI = ReadI = LR->begin(); in add()
1147 if (ReadI != E && ReadI->end <= Seg.start) { in add()
1149 if (ReadI != WriteI) in add()
1152 if (ReadI == WriteI) in add()
1153 ReadI = WriteI = LR->find(Seg.start); in add()
1155 while (ReadI != E && ReadI->end <= Seg.start) in add()
1156 *WriteI++ = *ReadI++; in add()
1159 assert(ReadI == E || ReadI->end > Seg.start); in add()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedKryoDetails.td | 345 def : InstRW<[KryoWrite_1cyc_XY_63ln, ReadI, ReadI],
357 def : InstRW<[KryoWrite_1cyc_XY_62ln, ReadI],
363 def : InstRW<[KryoWrite_2cyc_XY_XY_64ln, ReadI, ReadI],
483 def : InstRW<[KryoWrite_0cyc_XY_16ln, ReadI],
489 def : InstRW<[KryoWrite_0cyc_XY_16_1ln, ReadI, ReadI],
495 def : InstRW<[KryoWrite_2cyc_XY_3ln, ReadI],
537 def : InstRW<[KryoWrite_3cyc_XY_4ln, ReadI, ReadISReg],
543 def : InstRW<[KryoWrite_1cyc_XY_20ln, ReadI, ReadI],
549 def : InstRW<[KryoWrite_1cyc_X_17ln, ReadI, ReadI],
555 def : InstRW<[KryoWrite_1cyc_XY_18ln, ReadI, ReadI],
[all …]
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| D | AArch64SchedFalkor.td | 105 def : ReadAdvance<ReadI, 0>;
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| D | AArch64Schedule.td | 28 def ReadI : SchedRead; // ALU
|
| D | AArch64SchedKryo.td | 111 def : ReadAdvance<ReadI, 0>;
|
| D | AArch64InstrFormats.td | 1568 Sched<[WriteI, ReadI]> {
1603 Sched<[WriteI, ReadI]> {
1628 Sched<[WriteI, ReadI, ReadI]> {
1643 Sched<[WriteI, ReadI, ReadI]> {
1671 Sched<[WriteI, ReadI, ReadI]> {
1757 Sched<[WriteIS, ReadI]> {
1865 Sched<[WriteISReg, ReadI, ReadISReg]> {
1952 Sched<[WriteI, ReadI]> {
1985 Sched<[WriteI, ReadI]> {
2003 Sched<[WriteI, ReadI, ReadI]>;
[all …]
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| D | AArch64SchedThunderX.td | 202 def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
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| D | AArch64SchedA53.td | 158 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
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| D | AArch64SchedCyclone.td | 864 def : ReadAdvance<ReadI, 0>;
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| D | AArch64SchedExynosM3.td | 275 def : ReadAdvance<ReadI, 0>;
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| D | AArch64SchedExynosM1.td | 231 def : ReadAdvance<ReadI, 0>;
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| D | AArch64SchedA57.td | 111 def : ReadAdvance<ReadI, 0>;
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedKryoDetails.td | 345 def : InstRW<[KryoWrite_1cyc_XY_63ln, ReadI, ReadI],
357 def : InstRW<[KryoWrite_1cyc_XY_62ln, ReadI],
363 def : InstRW<[KryoWrite_2cyc_XY_XY_64ln, ReadI, ReadI],
483 def : InstRW<[KryoWrite_0cyc_XY_16ln, ReadI],
489 def : InstRW<[KryoWrite_0cyc_XY_16_1ln, ReadI, ReadI],
495 def : InstRW<[KryoWrite_2cyc_XY_3ln, ReadI],
537 def : InstRW<[KryoWrite_3cyc_XY_4ln, ReadI, ReadISReg],
543 def : InstRW<[KryoWrite_1cyc_XY_20ln, ReadI, ReadI],
549 def : InstRW<[KryoWrite_1cyc_X_17ln, ReadI, ReadI],
555 def : InstRW<[KryoWrite_1cyc_XY_18ln, ReadI, ReadI],
[all …]
|
| D | AArch64Schedule.td | 28 def ReadI : SchedRead; // ALU
|
| D | AArch64SchedKryo.td | 106 def : ReadAdvance<ReadI, 0>;
|
| D | AArch64InstrFormats.td | 1274 Sched<[WriteI, ReadI]> {
1313 Sched<[WriteI, ReadI, ReadI]> {
1399 Sched<[WriteIS, ReadI]> {
1507 Sched<[WriteISReg, ReadI, ReadISReg]> {
1594 Sched<[WriteI, ReadI]> {
1627 Sched<[WriteI, ReadI]> {
1645 Sched<[WriteI, ReadI, ReadI]>;
1653 Sched<[WriteISReg, ReadI, ReadISReg]> {
1682 Sched<[WriteIEReg, ReadI, ReadIEReg]> {
1707 Sched<[WriteIEReg, ReadI, ReadIEReg]> {
[all …]
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| D | AArch64SchedA53.td | 156 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
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| D | AArch64SchedM1.td | 154 def : ReadAdvance<ReadI, 0>;
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| D | AArch64SchedCyclone.td | 862 def : ReadAdvance<ReadI, 0>;
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| D | AArch64SchedVulcan.td | 192 def : ReadAdvance<ReadI, 0>;
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| D | AArch64SchedA57.td | 109 def : ReadAdvance<ReadI, 0>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 479 auto ReadI = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, in insertComparison() local
482 if (!constrainSelectedInstRegOperands(*ReadI, TII, TRI, RBI)) in insertComparison()
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| /external/llvm/include/llvm/CodeGen/ |
| D | LiveInterval.h | 794 LiveRange::iterator ReadI; variable
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | LiveInterval.h | 858 LiveRange::iterator ReadI; variable
|