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/external/swiftshader/third_party/subzero/pydir/
Dgen_arm32_reg_tables.py60 class Reg(object): class
82 Reg( 'r0', 0, IsScratch=1, CCArg=1, IsGPR = 1, IsInt=1, Aliases= 'r0, r0r1'),
83 Reg( 'r1', 1, IsScratch=1, CCArg=2, IsGPR = 1, IsInt=1, Aliases= 'r1, r0r1'),
84 Reg( 'r2', 2, IsScratch=1, CCArg=3, IsGPR = 1, IsInt=1, Aliases= 'r2, r2r3'),
85 Reg( 'r3', 3, IsScratch=1, CCArg=4, IsGPR = 1, IsInt=1, Aliases= 'r3, r2r3'),
86 Reg( 'r4', 4, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r4, r4r5'),
87 Reg( 'r5', 5, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r5, r4r5'),
88 Reg( 'r6', 6, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r6, r6r7'),
89 Reg( 'r7', 7, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r7, r6r7'),
90 Reg( 'r8', 8, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r8, r8r9'),
[all …]
/external/syzkaller/pkg/ifuzz/generated/
Dinsns.go11 …{Name: "FMUL", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: -3, Reg: 1, Rm:…
12 …{Name: "FCOMP", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: -3, Reg: 3, Rm…
13 …{Name: "FSUB", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: -3, Reg: 4, Rm:…
14 …{Name: "FSUBR", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: -3, Reg: 5, Rm…
15 …{Name: "FDIV", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: -3, Reg: 6, Rm:…
16 …{Name: "FDIVR", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: -3, Reg: 7, Rm…
18 …{Name: "FMUL", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: 3, Reg: 1, Rm: …
19 …{Name: "FCOM", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: -3, Reg: 2, Rm:…
20 …{Name: "FCOM", Extension: "X87", Mode: 15, Opcode: []uint8{220}, Modrm: true, Mod: -1, Reg: 2, Rm:…
21 …{Name: "FCOM", Extension: "X87", Mode: 15, Opcode: []uint8{216}, Modrm: true, Mod: 3, Reg: 2, Rm: …
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/
Dstore.ll20 ; MIPS32-NEXT: # <MCOperand Reg:1>
23 ; MIPS32-NEXT: # <MCOperand Reg:19>>
25 ; MIPS32-NEXT: # <MCOperand Reg:22>
26 ; MIPS32-NEXT: # <MCOperand Reg:1>
32 ; MMR3-NEXT: # <MCOperand Reg:1>
35 ; MMR3-NEXT: # <MCOperand Reg:19>>
37 ; MMR3-NEXT: # <MCOperand Reg:22>
38 ; MMR3-NEXT: # <MCOperand Reg:1>
44 ; MIPS32R6-NEXT: # <MCOperand Reg:1>
47 ; MIPS32R6-NEXT: # <MCOperand Reg:21>
[all …]
Dload.ll21 ; MIPS32-NEXT: # <MCOperand Reg:1>
24 ; MIPS32-NEXT: # <MCOperand Reg:19>>
26 ; MIPS32-NEXT: # <MCOperand Reg:321>
27 ; MIPS32-NEXT: # <MCOperand Reg:1>
33 ; MMR3-NEXT: # <MCOperand Reg:1>
36 ; MMR3-NEXT: # <MCOperand Reg:19>>
38 ; MMR3-NEXT: # <MCOperand Reg:321>
39 ; MMR3-NEXT: # <MCOperand Reg:1>
45 ; MIPS32R6-NEXT: # <MCOperand Reg:1>
48 ; MIPS32R6-NEXT: # <MCOperand Reg:21>
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp59 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() argument
61 VRegInfo[Reg].first = RC; in setRegClass()
64 void MachineRegisterInfo::setRegBank(unsigned Reg, in setRegBank() argument
66 VRegInfo[Reg].first = &RegBank; in setRegBank()
70 constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg, in constrainRegClass() argument
81 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
86 MachineRegisterInfo::constrainRegClass(unsigned Reg, in constrainRegClass() argument
89 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass()
93 MachineRegisterInfo::constrainRegAttrs(unsigned Reg, in constrainRegAttrs() argument
96 auto const *OldRC = getRegClassOrNull(Reg); in constrainRegAttrs()
[all …]
DAggressiveAntiDepBreaker.cpp76 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup() argument
77 unsigned Node = GroupNodeIndices[Reg]; in GetGroup()
89 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
90 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
91 Regs.push_back(Reg); in GetGroupRegs()
110 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) { in LeaveGroup() argument
116 GroupNodeIndices[Reg] = idx; in LeaveGroup()
120 bool AggressiveAntiDepState::IsLive(unsigned Reg) { in IsLive() argument
123 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
166 unsigned Reg = *AI; in StartBlock() local
[all …]
DCriticalAntiDepBreaker.cpp76 unsigned Reg = *AI; in StartBlock() local
77 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
78 KillIndices[Reg] = BBSize; in StartBlock()
79 DefIndices[Reg] = ~0u; in StartBlock()
90 unsigned Reg = *I; in StartBlock() local
91 if (!IsReturnBlock && !Pristine.test(Reg)) in StartBlock()
94 unsigned Reg = *AI; in StartBlock() local
95 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
96 KillIndices[Reg] = BBSize; in StartBlock()
97 DefIndices[Reg] = ~0u; in StartBlock()
[all …]
DLiveVariables.cpp182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr &MI) { in HandleVirtRegDef() argument
183 VarInfo &VRInfo = getVarInfo(Reg); in HandleVirtRegDef()
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, in FindLastPartialDef() argument
197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastPartialDef()
219 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr &MI) { in HandlePhysRegUse() argument
232 MachineInstr *LastDef = PhysRegDef[Reg]; in HandlePhysRegUse()
234 if (!LastDef && !PhysRegUse[Reg]) { in HandlePhysRegUse()
244 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs); in HandlePhysRegUse()
247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
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DLivePhysRegs.cpp50 unsigned Reg = O->getReg(); in removeDefs() local
51 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) in removeDefs()
53 removeReg(Reg); in removeDefs()
64 unsigned Reg = O->getReg(); in addUses() local
65 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) in addUses()
67 addReg(Reg); in addUses()
90 unsigned Reg = O->getReg(); in stepForward() local
91 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) in stepForward()
96 Clobbers.push_back(std::make_pair(Reg, &*O)); in stepForward()
101 removeReg(Reg); in stepForward()
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DRegisterScavenging.cpp53 void RegScavenger::setRegUsed(unsigned Reg, LaneBitmask LaneMask) { in setRegUsed() argument
54 LiveUnits.addRegMasked(Reg, LaneMask); in setRegUsed()
77 SI.Reg = 0; in init()
100 void RegScavenger::addRegUnits(BitVector &BV, unsigned Reg) { in addRegUnits() argument
101 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) in addRegUnits()
105 void RegScavenger::removeRegUnits(BitVector &BV, unsigned Reg) { in removeRegUnits() argument
106 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) in removeRegUnits()
137 unsigned Reg = MO.getReg(); in determineKillsAndDefs() local
138 if (!TargetRegisterInfo::isPhysicalRegister(Reg) || isReserved(Reg)) in determineKillsAndDefs()
146 addRegUnits(KillRegUnits, Reg); in determineKillsAndDefs()
[all …]
DMachineInstrBundle.cpp148 unsigned Reg = MO.getReg(); in finalizeBundle() local
149 if (!Reg) in finalizeBundle()
151 assert(TargetRegisterInfo::isPhysicalRegister(Reg)); in finalizeBundle()
152 if (LocalDefSet.count(Reg)) { in finalizeBundle()
156 KilledDefSet.insert(Reg); in finalizeBundle()
158 if (ExternUseSet.insert(Reg).second) { in finalizeBundle()
159 ExternUses.push_back(Reg); in finalizeBundle()
161 UndefUseSet.insert(Reg); in finalizeBundle()
165 KilledUseSet.insert(Reg); in finalizeBundle()
171 unsigned Reg = MO.getReg(); in finalizeBundle() local
[all …]
/external/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp39 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() argument
41 VRegInfo[Reg].first = RC; in setRegClass()
44 void MachineRegisterInfo::setRegBank(unsigned Reg, in setRegBank() argument
46 VRegInfo[Reg].first = &RegBank; in setRegBank()
50 MachineRegisterInfo::constrainRegClass(unsigned Reg, in constrainRegClass() argument
53 const TargetRegisterClass *OldRC = getRegClass(Reg); in constrainRegClass()
62 setRegClass(Reg, NewRC); in constrainRegClass()
67 MachineRegisterInfo::recomputeRegClass(unsigned Reg) { in recomputeRegClass() argument
69 const TargetRegisterClass *OldRC = getRegClass(Reg); in recomputeRegClass()
78 for (MachineOperand &MO : reg_nodbg_operands(Reg)) { in recomputeRegClass()
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DAggressiveAntiDepBreaker.cpp60 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup() argument
61 unsigned Node = GroupNodeIndices[Reg]; in GetGroup()
73 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
74 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
75 Regs.push_back(Reg); in GetGroupRegs()
95 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) in LeaveGroup() argument
102 GroupNodeIndices[Reg] = idx; in LeaveGroup()
106 bool AggressiveAntiDepState::IsLive(unsigned Reg) in IsLive() argument
110 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
154 unsigned Reg = *AI; in StartBlock() local
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DLiveVariables.cpp182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr &MI) { in HandleVirtRegDef() argument
183 VarInfo &VRInfo = getVarInfo(Reg); in HandleVirtRegDef()
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, in FindLastPartialDef() argument
197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastPartialDef()
219 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr &MI) { in HandlePhysRegUse() argument
232 MachineInstr *LastDef = PhysRegDef[Reg]; in HandlePhysRegUse()
234 if (!LastDef && !PhysRegUse[Reg]) { in HandlePhysRegUse()
244 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs); in HandlePhysRegUse()
247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
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DCriticalAntiDepBreaker.cpp62 unsigned Reg = *AI; in StartBlock() local
63 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
64 KillIndices[Reg] = BBSize; in StartBlock()
65 DefIndices[Reg] = ~0u; in StartBlock()
77 unsigned Reg = *AI; in StartBlock() local
78 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
79 KillIndices[Reg] = BBSize; in StartBlock()
80 DefIndices[Reg] = ~0u; in StartBlock()
103 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local
104 if (KillIndices[Reg] != ~0u) { in Observe()
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DMachineInstrBundle.cpp146 unsigned Reg = MO.getReg(); in finalizeBundle() local
147 if (!Reg) in finalizeBundle()
149 assert(TargetRegisterInfo::isPhysicalRegister(Reg)); in finalizeBundle()
150 if (LocalDefSet.count(Reg)) { in finalizeBundle()
154 KilledDefSet.insert(Reg); in finalizeBundle()
156 if (ExternUseSet.insert(Reg).second) { in finalizeBundle()
157 ExternUses.push_back(Reg); in finalizeBundle()
159 UndefUseSet.insert(Reg); in finalizeBundle()
163 KilledUseSet.insert(Reg); in finalizeBundle()
169 unsigned Reg = MO.getReg(); in finalizeBundle() local
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Lanai/
Dmemory.s10 ! CHECK-NEXT: <MCOperand Reg:13>
11 ! CHECK-NEXT: <MCOperand Reg:14>
18 ! CHECK-NEXT: <MCOperand Reg:13>
19 ! CHECK-NEXT: <MCOperand Reg:13>
26 ! CHECK-NEXT: <MCOperand Reg:13>
27 ! CHECK-NEXT: <MCOperand Reg:14>
34 ! CHECK-NEXT: <MCOperand Reg:13>
35 ! CHECK-NEXT: <MCOperand Reg:14>
42 ! CHECK-NEXT: <MCOperand Reg:13>
43 ! CHECK-NEXT: <MCOperand Reg:14>
[all …]
/external/llvm/test/MC/Lanai/
Dmemory.s10 ! CHECK-NEXT: <MCOperand Reg:13>
11 ! CHECK-NEXT: <MCOperand Reg:14>
18 ! CHECK-NEXT: <MCOperand Reg:13>
19 ! CHECK-NEXT: <MCOperand Reg:13>
26 ! CHECK-NEXT: <MCOperand Reg:13>
27 ! CHECK-NEXT: <MCOperand Reg:14>
34 ! CHECK-NEXT: <MCOperand Reg:13>
35 ! CHECK-NEXT: <MCOperand Reg:14>
42 ! CHECK-NEXT: <MCOperand Reg:13>
43 ! CHECK-NEXT: <MCOperand Reg:14>
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonVectorPrint.cpp74 static bool isVecReg(unsigned Reg) { in isVecReg() argument
75 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) in isVecReg()
76 || (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) in isVecReg()
77 || (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
96 static void addAsmInstr(MachineBasicBlock *MBB, unsigned Reg, in addAsmInstr() argument
100 std::string VDescStr = ".long 0x1dffe0" + getStringReg(Reg); in addAsmInstr()
108 static bool getInstrVecReg(const MachineInstr &MI, unsigned &Reg) { in getInstrVecReg() argument
112 Reg = MI.getOperand(0).getReg(); in getInstrVecReg()
113 if (isVecReg(Reg)) in getInstrVecReg()
118 Reg = MI.getOperand(2).getReg(); in getInstrVecReg()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp61 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup() argument
62 unsigned Node = GroupNodeIndices[Reg]; in GetGroup()
74 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
75 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
76 Regs.push_back(Reg); in GetGroupRegs()
96 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) in LeaveGroup() argument
103 GroupNodeIndices[Reg] = idx; in LeaveGroup()
107 bool AggressiveAntiDepState::IsLive(unsigned Reg) in IsLive() argument
111 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
161 unsigned Reg = *Alias; ++Alias) { in StartBlock()
[all …]
DCriticalAntiDepBreaker.cpp64 unsigned Reg = *I; in StartBlock() local
65 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
66 KillIndices[Reg] = BB->size(); in StartBlock()
67 DefIndices[Reg] = ~0u; in StartBlock()
70 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { in StartBlock()
86 unsigned Reg = *I; in StartBlock() local
87 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
88 KillIndices[Reg] = BB->size(); in StartBlock()
89 DefIndices[Reg] = ~0u; in StartBlock()
92 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { in StartBlock()
[all …]
DMachineRegisterInfo.cpp46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() argument
47 VRegInfo[Reg].first = RC; in setRegClass()
51 MachineRegisterInfo::constrainRegClass(unsigned Reg, in constrainRegClass() argument
54 const TargetRegisterClass *OldRC = getRegClass(Reg); in constrainRegClass()
62 setRegClass(Reg, NewRC); in constrainRegClass()
67 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { in recomputeRegClass() argument
69 const TargetRegisterClass *OldRC = getRegClass(Reg); in recomputeRegClass()
77 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; in recomputeRegClass()
89 setRegClass(Reg, NewRC); in recomputeRegClass()
103 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); in createVirtualRegister() local
[all …]
DLiveVariables.cpp178 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) { in HandleVirtRegDef() argument
179 VarInfo &VRInfo = getVarInfo(Reg); in HandleVirtRegDef()
188 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, in FindLastPartialDef() argument
193 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); in FindLastPartialDef()
215 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
228 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { in HandlePhysRegUse() argument
229 MachineInstr *LastDef = PhysRegDef[Reg]; in HandlePhysRegUse()
231 if (!LastDef && !PhysRegUse[Reg]) { in HandlePhysRegUse()
241 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs); in HandlePhysRegUse()
244 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DMachineRegisterInfo.h61 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
126 return MO->Contents.Reg.Next; in getNextOperandForReg()
236 void disableCalleeSavedRegister(unsigned Reg);
257 void verifyUseList(unsigned Reg) const;
287 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const { in reg_operands() argument
288 return make_range(reg_begin(Reg), reg_end()); in reg_operands()
303 reg_instructions(unsigned Reg) const { in reg_instructions() argument
304 return make_range(reg_instr_begin(Reg), reg_instr_end()); in reg_instructions()
318 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const { in reg_bundles() argument
319 return make_range(reg_bundle_begin(Reg), reg_bundle_end()); in reg_bundles()
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineRegisterInfo.h44 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
94 return MO->Contents.Reg.Next; in getNextOperandForReg()
220 void verifyUseList(unsigned Reg) const;
252 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const { in reg_operands() argument
253 return make_range(reg_begin(Reg), reg_end()); in reg_operands()
268 reg_instructions(unsigned Reg) const { in reg_instructions() argument
269 return make_range(reg_instr_begin(Reg), reg_instr_end()); in reg_instructions()
283 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const { in reg_bundles() argument
284 return make_range(reg_bundle_begin(Reg), reg_bundle_end()); in reg_bundles()
303 reg_nodbg_operands(unsigned Reg) const { in reg_nodbg_operands() argument
[all …]

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