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Searched refs:SLOT0 (Results 1 – 19 of 19) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonDepIICScalar.td178 InstrItinData <tc_00e7c26e, [InstrStage<1, [SLOT0]>]>,
179 InstrItinData <tc_03220ffa, [InstrStage<1, [SLOT0, SLOT1]>]>,
182 InstrItinData <tc_05b6c987, [InstrStage<1, [SLOT0, SLOT1]>]>,
183 InstrItinData <tc_0cd51c76, [InstrStage<1, [SLOT0, SLOT1]>]>,
184 InstrItinData <tc_0dc560de, [InstrStage<1, [SLOT0, SLOT1]>]>,
185 InstrItinData <tc_0fc1ae07, [InstrStage<1, [SLOT0]>]>,
187 InstrItinData <tc_1372bca1, [InstrStage<1, [SLOT0]>]>,
193 InstrItinData <tc_1b82a277, [InstrStage<1, [SLOT0, SLOT1]>]>,
195 InstrItinData <tc_1d5a38a8, [InstrStage<1, [SLOT0, SLOT1]>]>,
198 InstrItinData <tc_238d91d2, [InstrStage<1, [SLOT0, SLOT1]>]>,
[all …]
DHexagonDepIICHVX.td97 InstrItinData <tc_0317c6ca, /*SLOT0,STORE,VA*/
98 [InstrStage<1, [SLOT0], 0>,
103 InstrItinData <tc_1b93bdc6, /*SLOT0,STORE*/
104 [InstrStage<1, [SLOT0], 0>,
109 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
114 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
118 InstrItinData <tc_29841470, /*SLOT0,STORE*/
119 [InstrStage<1, [SLOT0], 0>,
124 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
128 InstrItinData <tc_354299ad, /*SLOT0,NOSLOT1,STORE,VP*/
[all …]
DHexagonScheduleV55.td13 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
17 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
25 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], [2, 1]>,
26 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
35 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
DHexagonScheduleV4.td15 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
18 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>]>,
25 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>,
26 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>
33 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
DHexagonIICScalar.td16 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
20 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
27 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
29 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
DHexagonIICHVX.td16 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
25 [InstrStage<1, [SLOT0], 0>,
DHexagonScheduleV60.td17 // | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM |
65 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonScheduleV62.td21 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonScheduleV65.td23 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonSchedule.td14 def SLOT0 : FuncUnit;
DHexagonInstrFormats.td208 // ST Instruction Class in V2/V3 can take SLOT0 only.
209 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
/external/llvm/lib/Target/Hexagon/
DHexagonScheduleV60.td67 // | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM |
107 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
112 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
114 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
116 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
118 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
120 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
122 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
149 [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
152 InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
[all …]
DHexagonScheduleV55.td17 // | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM |
43 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
46 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
48 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
50 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
52 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
54 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
56 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
83 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
86 InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
[all …]
DHexagonScheduleV4.td17 // | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM |
27 def SLOT0 : FuncUnit;
100 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
103 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
105 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
107 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
109 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
111 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
113 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
137 InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
[all …]
DHexagonInstrFormats.td239 // ST Instruction Class in V2/V3 can take SLOT0 only.
240 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
262 // ST Instruction Class in V2/V3 can take SLOT0 only.
263 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
269 // SYSTEM Instruction Class in V4 can take SLOT0 only
270 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dstack-guard-remat-bitcast.ll12 ; CHECK: stur [[R2]], {{\[}}x29, [[SLOT0:[0-9#\-]+]]{{\]}}
13 ; CHECK: ldur [[R3:x[0-9]+]], {{\[}}x29, [[SLOT0]]{{\]}}
/external/llvm/test/CodeGen/AArch64/
Dstack-guard-remat-bitcast.ll12 ; CHECK: stur [[R2]], {{\[}}x29, [[SLOT0:[0-9#\-]+]]{{\]}}
13 ; CHECK: ldur [[R3:x[0-9]+]], {{\[}}x29, [[SLOT0]]{{\]}}
/external/python/cpython2/Objects/
Dtypeobject.c5018 #define SLOT0(FUNCNAME, OPSTR) \ macro
5322 SLOT0(slot_nb_negative, "__neg__")
5323 SLOT0(slot_nb_positive, "__pos__")
5324 SLOT0(slot_nb_absolute, "__abs__")
5375 SLOT0(slot_nb_invert, "__invert__")
5440 SLOT0(slot_nb_int, "__int__")
5441 SLOT0(slot_nb_long, "__long__")
5442 SLOT0(slot_nb_float, "__float__")
5443 SLOT0(slot_nb_oct, "__oct__")
5444 SLOT0(slot_nb_hex, "__hex__")
/external/python/cpython3/Objects/
Dtypeobject.c5950 #define SLOT0(FUNCNAME, OPSTR) \ macro
6200 SLOT0(slot_nb_negative, "__neg__")
6201 SLOT0(slot_nb_positive, "__pos__")
6202 SLOT0(slot_nb_absolute, "__abs__")
6266 SLOT0(slot_nb_invert, "__invert__")
6273 SLOT0(slot_nb_int, "__int__")
6274 SLOT0(slot_nb_float, "__float__")
6317 SLOT0(slot_tp_str, "__str__")