Searched refs:SMINV (Results 1 – 8 of 8) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 153 SMINV, enumerator
|
| D | AArch64ISelLowering.cpp | 910 case AArch64ISD::SMINV: return "AArch64ISD::SMINV"; in getTargetNodeName()
8547 return combineAcrossLanesIntrinsic(AArch64ISD::SMINV, N, DAG); in performIntrinsicCombine()
9024 Opcode = AArch64ISD::SMINV; in tryMatchAcrossLaneShuffleForReduction()
10123 case AArch64ISD::SMINV: in ReplaceNodeResults()
10124 ReplaceReductionResults(N, Results, DAG, ISD::SMIN, AArch64ISD::SMINV); in ReplaceNodeResults()
|
| D | AArch64InstrInfo.td | 294 def AArch64sminv : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>;
4127 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
4263 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", AArch64sminv>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 153 SMINV, enumerator
|
| D | AArch64ISelLowering.cpp | 1161 case AArch64ISD::SMINV: return "AArch64ISD::SMINV"; in getTargetNodeName()
7657 return getReductionSDNode(AArch64ISD::SMINV, dl, Op, DAG); in LowerVECREDUCE()
9712 return combineAcrossLanesIntrinsic(AArch64ISD::SMINV, N, DAG); in performIntrinsicCombine()
11278 case AArch64ISD::SMINV: in ReplaceNodeResults()
11279 ReplaceReductionResults(N, Results, DAG, ISD::SMIN, AArch64ISD::SMINV); in ReplaceNodeResults()
|
| D | AArch64InstrInfo.td | 327 def AArch64sminv : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>;
4458 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
4594 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", AArch64sminv>;
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2987 ### SMINV ### subsection
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenDAGISel.inc | 15853 /* 30531*/ /*SwitchOpcode*/ 108, TARGET_VAL(AArch64ISD::SMINV),// ->30642
15992 /* 30855*/ /*SwitchOpcode*/ 103, TARGET_VAL(AArch64ISD::SMINV),// ->30961
17717 /* 34193*/ /*SwitchOpcode*/ 98, TARGET_VAL(AArch64ISD::SMINV),// ->34294
18000 /* 34923*/ /*SwitchOpcode*/ 10|128,1/*138*/, TARGET_VAL(AArch64ISD::SMINV),// ->35065
47312 /* 92287*/ /*SwitchOpcode*/ 20|128,1/*148*/, TARGET_VAL(AArch64ISD::SMINV),// ->92439
|