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Searched refs:ShiftVal (Results 1 – 25 of 37) sorted by relevance

12

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp267 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue() local
268 assert((ShiftVal == 0 || ShiftVal == 12) && in getAddSubImmOpValue()
271 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getAddSubImmOpValue()
288 ShiftVal = 12; in getAddSubImmOpValue()
290 return ShiftVal == 0 ? 0 : (1 << ShiftVal); in getAddSubImmOpValue()
528 unsigned ShiftVal = AArch64_AM::getShiftValue(ShiftOpnd); in getImm8OptLsl() local
529 assert((ShiftVal == 0 || ShiftVal == 8) && in getImm8OptLsl()
534 return (Immediate & 0xff) | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getImm8OptLsl()
555 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm()); in getMoveVecShifterOpValue() local
556 assert((ShiftVal == 8 || ShiftVal == 16) && "Invalid shift amount!"); in getMoveVecShifterOpValue()
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/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp252 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue() local
253 assert((ShiftVal == 0 || ShiftVal == 12) && in getAddSubImmOpValue()
256 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << 12)); in getAddSubImmOpValue()
503 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm()); in getMoveVecShifterOpValue() local
504 assert((ShiftVal == 8 || ShiftVal == 16) && "Invalid shift amount!"); in getMoveVecShifterOpValue()
505 return ShiftVal == 8 ? 0 : 1; in getMoveVecShifterOpValue()
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp55 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
56 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
DAArch64FastISel.cpp1183 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitAddSub() local
1189 RHSIsKill, AArch64_AM::LSL, ShiftVal, SetFlags, in emitAddSub()
1207 uint64_t ShiftVal = C->getZExtValue(); in emitAddSub() local
1214 RHSIsKill, ShiftType, ShiftVal, SetFlags, in emitAddSub()
1561 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitLogicalOp() local
1568 RHSIsKill, ShiftVal); in emitLogicalOp()
1578 uint64_t ShiftVal = C->getZExtValue(); in emitLogicalOp() local
1584 RHSIsKill, ShiftVal); in emitLogicalOp()
4523 uint64_t ShiftVal = C->getValue().logBase2(); in selectMul() local
4552 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul()
[all …]
DAArch64ISelDAGToDAG.cpp567 unsigned ShiftVal = 0; in SelectArithExtendedRegister() local
574 ShiftVal = CSD->getZExtValue(); in SelectArithExtendedRegister()
575 if (ShiftVal > 4) in SelectArithExtendedRegister()
598 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N), in SelectArithExtendedRegister()
799 unsigned ShiftVal = CSD->getZExtValue(); in SelectExtendedSHL() local
801 if (ShiftVal != 0 && ShiftVal != LegalShiftVal) in SelectExtendedSHL()
/external/capstone/arch/AArch64/
DAArch64InstPrinter.c810 unsigned ShiftVal = AArch64_AM_getArithShiftValue(Val); in printArithExtend() local
822 if (ShiftVal != 0) { in printArithExtend()
824 printInt32Bang(O, ShiftVal); in printArithExtend()
827 …lat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal; in printArithExtend()
869 if (ShiftVal != 0) { in printArithExtend()
871 printInt32Bang(O, ShiftVal); in printArithExtend()
874 …lat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal; in printArithExtend()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp73 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
74 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
DAArch64FastISel.cpp1229 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitAddSub() local
1235 RHSIsKill, AArch64_AM::LSL, ShiftVal, SetFlags, in emitAddSub()
1253 uint64_t ShiftVal = C->getZExtValue(); in emitAddSub() local
1260 RHSIsKill, ShiftType, ShiftVal, SetFlags, in emitAddSub()
1615 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitLogicalOp() local
1622 RHSIsKill, ShiftVal); in emitLogicalOp()
1632 uint64_t ShiftVal = C->getZExtValue(); in emitLogicalOp() local
1638 RHSIsKill, ShiftVal); in emitLogicalOp()
4609 uint64_t ShiftVal = C->getValue().logBase2(); in selectMul() local
4638 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul()
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DAArch64InstrInfo.cpp946 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
947 if (ShiftVal == 0) in isFalkorShiftExtFast()
949 return AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL && ShiftVal <= 5; in isFalkorShiftExtFast()
973 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
974 return ShiftVal == 0 || in isFalkorShiftExtFast()
975 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 31); in isFalkorShiftExtFast()
981 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
982 return ShiftVal == 0 || in isFalkorShiftExtFast()
983 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 63); in isFalkorShiftExtFast()
DAArch64ISelDAGToDAG.cpp348 unsigned ShiftVal = CSD->getZExtValue(); in isWorthFoldingSHL() local
349 if (ShiftVal > 3) in isWorthFoldingSHL()
617 unsigned ShiftVal = 0; in SelectArithExtendedRegister() local
624 ShiftVal = CSD->getZExtValue(); in SelectArithExtendedRegister()
625 if (ShiftVal > 4) in SelectArithExtendedRegister()
653 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N), in SelectArithExtendedRegister()
856 unsigned ShiftVal = CSD->getZExtValue(); in SelectExtendedSHL() local
858 if (ShiftVal != 0 && ShiftVal != LegalShiftVal) in SelectExtendedSHL()
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp1099 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); in printArithExtend() local
1111 if (ShiftVal != 0) in printArithExtend()
1112 O << ", lsl #" << ShiftVal; in printArithExtend()
1117 if (ShiftVal != 0) in printArithExtend()
1118 O << " #" << ShiftVal; in printArithExtend()
/external/llvm/lib/IR/
DAutoUpgrade.cpp525 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); in UpgradeX86PALIGNRIntrinsics() local
532 if (ShiftVal >= 32) in UpgradeX86PALIGNRIntrinsics()
537 if (ShiftVal > 16) { in UpgradeX86PALIGNRIntrinsics()
538 ShiftVal -= 16; in UpgradeX86PALIGNRIntrinsics()
547 unsigned Idx = ShiftVal + i; in UpgradeX86PALIGNRIntrinsics()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp1265 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
1272 Srl.getOperand(0), ShiftVal, WidthVal)); in SelectS_BFE()
1287 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
1288 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal; in SelectS_BFE()
1294 And.getOperand(0), ShiftVal, WidthVal)); in SelectS_BFE()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp957 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); in printArithExtend() local
969 if (ShiftVal != 0) in printArithExtend()
970 O << ", lsl #" << ShiftVal; in printArithExtend()
975 if (ShiftVal != 0) in printArithExtend()
976 O << " #" << ShiftVal; in printArithExtend()
/external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/
DScalarReplAggregates.cpp2219 Value *ShiftVal = ConstantInt::get(EltVal->getType(), Shift); in RewriteStoreUserOfWholeAlloca() local
2220 EltVal = Builder.CreateLShr(EltVal, ShiftVal, "sroa.store.elt"); in RewriteStoreUserOfWholeAlloca()
2265 Value *ShiftVal = ConstantInt::get(EltVal->getType(), Shift); in RewriteStoreUserOfWholeAlloca() local
2266 EltVal = Builder.CreateLShr(EltVal, ShiftVal, "sroa.store.elt"); in RewriteStoreUserOfWholeAlloca()
2365 Value *ShiftVal = ConstantInt::get(SrcField->getType(), Shift); in RewriteLoadUserOfWholeAlloca() local
2366 SrcField = BinaryOperator::CreateShl(SrcField, ShiftVal, "", LI); in RewriteLoadUserOfWholeAlloca()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/InstCombine/
DInstCombineCalls.cpp455 APInt ShiftVal = COp->getValue(); in simplifyX86varShift() local
456 if (ShiftVal.uge(BitWidth)) { in simplifyX86varShift()
462 ShiftAmts.push_back((int)ShiftVal.getZExtValue()); in simplifyX86varShift()
3390 Value *ShiftVal = Builder.CreateSub(KSize, II->getArgOperand(2)); in visitCallInst() local
3391 ShiftVal = Builder.CreateZExt(ShiftVal, II->getType()); in visitCallInst()
3393 Value *Shl = Builder.CreateShl(Src, ShiftVal); in visitCallInst()
3394 Value *RightShift = Signed ? Builder.CreateAShr(Shl, ShiftVal) in visitCallInst()
3395 : Builder.CreateLShr(Shl, ShiftVal); in visitCallInst()
DInstCombineCasts.cpp464 ConstantInt *ShiftVal = nullptr; in foldVecTruncToExtElt() local
467 m_ConstantInt(ShiftVal)))) || in foldVecTruncToExtElt()
474 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt()
DInstCombineCompares.cpp1869 const APInt *ShiftVal; in foldICmpShlConstant() local
1870 if (Cmp.isEquality() && match(Shl->getOperand(0), m_APInt(ShiftVal))) in foldICmpShlConstant()
1871 return foldICmpShlConstConst(Cmp, Shl->getOperand(1), C, *ShiftVal); in foldICmpShlConstant()
1996 const APInt *ShiftVal; in foldICmpShrConstant() local
1997 if (Cmp.isEquality() && match(Shr->getOperand(0), m_APInt(ShiftVal))) in foldICmpShrConstant()
1998 return foldICmpShrConstConst(Cmp, Shr->getOperand(1), C, *ShiftVal); in foldICmpShrConstant()
/external/llvm/lib/Transforms/InstCombine/
DInstCombineCasts.cpp447 ConstantInt *ShiftVal = nullptr; in foldVecTruncToExtElt() local
450 m_ConstantInt(ShiftVal)))) || in foldVecTruncToExtElt()
457 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp2007 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) { in isSimpleShift() argument
2016 ShiftVal = Amount; in isSimpleShift()
2165 unsigned NewCCMask, ShiftVal; in adjustForTestUnderMask() local
2168 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
2169 (MaskVal >> ShiftVal != 0) && in adjustForTestUnderMask()
2170 ((CmpVal >> ShiftVal) << ShiftVal) == CmpVal && in adjustForTestUnderMask()
2172 MaskVal >> ShiftVal, in adjustForTestUnderMask()
2173 CmpVal >> ShiftVal, in adjustForTestUnderMask()
2176 MaskVal >>= ShiftVal; in adjustForTestUnderMask()
2179 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp1589 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
1596 Srl.getOperand(0), ShiftVal, WidthVal)); in SelectS_BFE()
1611 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
1612 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal; in SelectS_BFE()
1618 And.getOperand(0), ShiftVal, WidthVal)); in SelectS_BFE()
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp1303 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
1304 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/IR/
DAutoUpgrade.cpp860 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); in UpgradeX86ALIGNIntrinsics() local
869 ShiftVal &= (NumElts - 1); in UpgradeX86ALIGNIntrinsics()
873 if (ShiftVal >= 32) in UpgradeX86ALIGNIntrinsics()
878 if (ShiftVal > 16) { in UpgradeX86ALIGNIntrinsics()
879 ShiftVal -= 16; in UpgradeX86ALIGNIntrinsics()
888 unsigned Idx = ShiftVal + i; in UpgradeX86ALIGNIntrinsics()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp1860 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) { in isSimpleShift() argument
1869 ShiftVal = Amount; in isSimpleShift()
2018 unsigned NewCCMask, ShiftVal; in adjustForTestUnderMask() local
2021 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
2023 MaskVal >> ShiftVal, in adjustForTestUnderMask()
2024 CmpVal >> ShiftVal, in adjustForTestUnderMask()
2027 MaskVal >>= ShiftVal; in adjustForTestUnderMask()
2030 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
2032 MaskVal << ShiftVal, in adjustForTestUnderMask()
2033 CmpVal << ShiftVal, in adjustForTestUnderMask()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp2283 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
2284 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()

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