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Searched refs:Src1IsKill (Results 1 – 5 of 5) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SIMDInstrOpt.cpp434 unsigned Src1IsKill = getKillRegState(MI.getOperand(2).isKill()); in optimizeVectElement() local
453 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
460 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
465 .addReg(DupDest, Src1IsKill); in optimizeVectElement()
DAArch64FastISel.cpp2650 bool Src1IsKill = hasTrivialKill(Src1Val); in optimizeSelect() local
2658 Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1); in optimizeSelect()
2659 Src1IsKill = true; in optimizeSelect()
2662 Src1IsKill, Src2Reg, Src2IsKill); in optimizeSelect()
2778 bool Src1IsKill = hasTrivialKill(SI->getTrueValue()); in selectSelect() local
2787 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect()
2791 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect()
4576 bool Src1IsKill = hasTrivialKill(I->getOperand(1)); in selectRem() local
4586 Src1Reg, Src1IsKill, Src0Reg, in selectRem()
4654 bool Src1IsKill = hasTrivialKill(I->getOperand(1)); in selectMul() local
[all …]
DAArch64InstrInfo.cpp4048 bool Src1IsKill = MUL->getOperand(2).isKill(); in genFusedMultiply() local
4074 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genFusedMultiply()
4080 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genFusedMultiply()
4086 .addReg(SrcReg1, getKillRegState(Src1IsKill)); in genFusedMultiply()
4125 bool Src1IsKill = MUL->getOperand(2).isKill(); in genMaddR() local
4139 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genMaddR()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp2561 bool Src1IsKill = hasTrivialKill(Src1Val); in optimizeSelect() local
2569 Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1); in optimizeSelect()
2570 Src1IsKill = true; in optimizeSelect()
2573 Src1IsKill, Src2Reg, Src2IsKill); in optimizeSelect()
2689 bool Src1IsKill = hasTrivialKill(SI->getTrueValue()); in selectSelect() local
2698 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect()
2702 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect()
4490 bool Src1IsKill = hasTrivialKill(I->getOperand(1)); in selectRem() local
4500 Src1Reg, Src1IsKill, Src0Reg, in selectRem()
4568 bool Src1IsKill = hasTrivialKill(I->getOperand(1)); in selectMul() local
[all …]
DAArch64InstrInfo.cpp3293 bool Src1IsKill = MUL->getOperand(2).isKill(); in genFusedMultiply() local
3310 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genFusedMultiply()
3316 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genFusedMultiply()
3322 .addReg(SrcReg1, getKillRegState(Src1IsKill)); in genFusedMultiply()
3357 bool Src1IsKill = MUL->getOperand(2).isKill(); in genMaddR() local
3371 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genMaddR()